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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <baseboard/variants.h>
#include <chip.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <smbios.h>
#include <string.h>
#include <variant/sku.h>
Go to the source code of this file.
Macros | |
#define | R_PCH_OC_WDT_CTL 0x54 |
#define | B_PCH_OC_WDT_CTL_FORCE_ALL BIT15 |
#define | B_PCH_OC_WDT_CTL_EN BIT14 |
#define | B_PCH_OC_WDT_CTL_UNXP_RESET_STS BIT22 |
Functions | |
const char * | smbios_system_sku (void) |
void | variant_devtree_update (void) |
#define B_PCH_OC_WDT_CTL_EN BIT14 |
Definition at line 14 of file mainboard.c.
#define B_PCH_OC_WDT_CTL_FORCE_ALL BIT15 |
Definition at line 13 of file mainboard.c.
#define B_PCH_OC_WDT_CTL_UNXP_RESET_STS BIT22 |
Definition at line 15 of file mainboard.c.
#define R_PCH_OC_WDT_CTL 0x54 |
Definition at line 12 of file mainboard.c.
const char* smbios_system_sku | ( | void | ) |
Definition at line 17 of file mainboard.c.
References snprintf(), and variant_board_sku().
Definition at line 27 of file mainboard.c.
References ABASE, B_PCH_OC_WDT_CTL_EN, B_PCH_OC_WDT_CTL_FORCE_ALL, B_PCH_OC_WDT_CTL_UNXP_RESET_STS, config_of_soc, inl(), OC0, OC1, OC2, outl(), PCH_DEV_PMC, pci_read_config16(), R_PCH_OC_WDT_CTL, SKU_0_NAUTILUS, SKU_1_NAUTILUS_LTE, sku_id(), USB2_BIAS_0MV, USB2_BIAS_39MV, USB2_BIAS_56MV, USB2_HALF_BIT_PRE_EMP, USB2_PRE_EMP_ON, and variant_board_sku().