mdssreg.h File Reference

#include <types.h>

Include dependency graph for mdssreg.h:

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures
struct	dsi_regs
struct	dsi_phy_regs
struct	dsi_phy_pll_qlink_regs
struct	mdp_intf_regs
struct	mdp_ctl_regs
struct	mdp_layer_mixer_regs
struct	mdp_sspp_regs
struct	vbif_rt_regs

Enumerations
enum	{ MDSS_BASE = 0xAE00000 }
enum	{   MDP_0_CTL_BASE = MDSS_BASE + 0x2000 , MDP_VP_0_SSPP_BASE = MDSS_BASE + 0x5000 , MDP_VP_0_LAYER_MIXER_BASE = MDSS_BASE + 0x45000 , MDP_1_INTF_BASE = MDSS_BASE + 0x6b800 ,   MDP_VBIF_RT_BASE = MDSS_BASE + 0xB0000 , DSI0_CTL_BASE = MDSS_BASE + 0x94000 , DSI0_PHY_BASE = MDSS_BASE + 0x94400 , DSI0_PHY_DLN0_BASE = MDSS_BASE + 0x94600 ,   DSI0_PHY_DLN1_BASE = MDSS_BASE + 0x94680 , DSI0_PHY_DLN2_BASE = MDSS_BASE + 0x94700 , DSI0_PHY_DLN3_BASE = MDSS_BASE + 0x94780 , DSI0_PHY_CLKLN_BASE = MDSS_BASE + 0x94800 ,   DSI0_PHY_PLL_QLINK_COM = MDSS_BASE + 0x94a00 }
enum	{   INTF = BIT(31) , PERIPH = BIT(30) , CWB = BIT(28) , ROT = BIT(27) ,   CDM_0 = BIT(26) , DMA_3 = BIT(25) , DMA_2 = BIT(24) , MERGE_3D = BIT(23) ,   DSC = BIT(22) , DSPP_3 = BIT(21) , LAYER_MIXER_5 = BIT(20) , DSPP_PA_LUTV_3 = BIT(19) ,   VIG_3 = BIT(18) , CTL = BIT(17) , WB = BIT(16) , DSPP_2 = BIT(15) ,   DSPP_1 = BIT(14) , DSPP_0 = BIT(13) , DMA_1 = BIT(12) , DMA_0 = BIT(11) ,   LAYER_MIXER_4 = BIT(10) , LAYER_MIXER_3 = BIT(9) , LAYER_MIXER_2 = BIT(8) , LAYER_MIXER_1 = BIT(7) ,   LAYER_MIXER_0 = BIT(6) , DSPP_PA_LUTV_2 = BIT(5) , DSPP_PA_LUTV_1 = BIT(4) , DSPP_PA_LUTV_0 = BIT(3) ,   VIG_2 = BIT(2) , VIG_1 = BIT(1) , VIG_0 = BIT(0) }
enum	{   DSI_AHBS_HCLK_ON = BIT(0) , DSI_AHBM_SCLK_ON = BIT(1) , DSI_PCLK_ON = BIT(2) , DSI_DSICLK_ON = BIT(3) ,   DSI_BYTECLK_ON = BIT(4) , DSI_ESCCLK_ON = BIT(5) , DSI_FORCE_ON_DYN_AHBS_HCLK = BIT(8) , DSI_FORCE_ON_DYN_AHBM_HCLK = BIT(9) ,   DSI_FORCE_ON_DYN_DSICLK = BIT(10) , DSI_FORCE_ON_DYN_BYTECLK = BIT(11) , DSI_AHBS_HCLK_HYSTERISIS1_CTRL = (3 << 11) , DSI_AHBM_HCLK_HYSTERISIS1_CTRL = (3 << 13) ,   DSI_DSICLK_HYSTERISIS1_CTRL = (3 << 15) , DSI_FORCE_ON_DYN_PCLK = BIT(20) , DSI_FORCE_ON_LANE_LAYER_TG_BYTECLK = BIT(21) , DSI_DMA_CLK_STOP = BIT(22) }
enum	{   DSI_CMD_MODE_DMA_DONE_AK = BIT(0) , DSI_CMD_MODE_DMA_DONE_STAT = BIT(0) , DSI_CMD_MODE_DMA_DONE_MASK = BIT(1) , DSI_CMD_MODE_MDP_DONE_AK = BIT(8) ,   DSI_CMD_MODE_MDP_DONE_STAT = BIT(8) , DSI_CMD_MODE_MDP_DONE_MASK = BIT(9) , DSI_CMD_MDP_STREAM0_DONE_AK = BIT(10) , DSI_CMD_MDP_STREAM0_DONE_STAT = BIT(10) ,   DSI_CMD_MDP_STREAM0_DONE_MASK = BIT(11) , DSI_VIDEO_MODE_DONE_AK = BIT(16) , DSI_VIDEO_MODE_DONE_STAT = BIT(16) , DSI_VIDEO_MODE_DONE_MASK = BIT(17) ,   DSI_BTA_DONE_AK = BIT(20) , DSI_BTA_DONE_STAT = BIT(20) , DSI_BTA_DONE_MASK = BIT(21) , DSI_ERROR_AK = BIT(24) ,   DSI_ERROR_STAT = BIT(24) , DSI_ERROR_MASK = BIT(25) , DSI_DYNAMIC_BLANKING_DMA_DONE_AK = BIT(26) , DSI_DYNAMIC_BLANKING_DMA_DONE_STAT = BIT(26) ,   DSI_DYNAMIC_BLANKING_DMA_DONE_MASK = BIT(27) , DSI_DYNAMIC_REFRESH_DONE_AK = BIT(28) , DSI_DYNAMIC_REFRESH_DONE_STAT = BIT(28) , DSI_DYNAMIC_REFRESH_DONE_MASK = BIT(29) ,   DSI_DESKEW_DONE_AK = BIT(30) , DSI_DESKEW_DONE_STAT = BIT(30) , DSI_DESKEW_DONE_MASK = BIT(31) }
enum	{ WR_MEM_START = 255 , WR_MEM_CONTINUE = 255 << 8 , INSERT_DCS_COMMAND = BIT(16) }
enum	{   PACKET_TYPE = BIT(24) , POWER_MODE = BIT(26) , EMBEDDED_MODE = BIT(28) , WC_SEL = BIT(29) ,   BROADCAST_MASTER = BIT(30) , BROADCAST_EN = BIT(31) }

Functions
	check_member (dsi_regs, video_mode_active_h, 0x24)
	check_member (dsi_regs, cmd_mode_mdp_stream0_ctrl, 0x58)
	check_member (dsi_regs, trig_ctrl, 0x84)
	check_member (dsi_regs, cmd_mode_dma_sw_trigger, 0x90)
	check_member (dsi_regs, misr_cmd_ctrl, 0xA0)
	check_member (dsi_regs, hs_timer_ctrl, 0xBC)
	check_member (dsi_regs, err_int_mask0, 0x10C)
	check_member (dsi_regs, test_pattern_gen_ctrl, 0x15c)
	check_member (dsi_regs, test_pattern_gen_cmd_dma_init_val, 0x17c)
	check_member (dsi_regs, cmd_mode_mdp_ctrl2, 0x1B8)
	check_member (dsi_regs, tpg_dma_fifo_reset, 0x1EC)
	check_member (dsi_regs, video_compression_mode_ctrl, 0x2A0)
	check_member (dsi_phy_regs, phy_cmn_clk_cfg0, 0x10)
	check_member (dsi_phy_regs, phy_cmn_dsi_lane_ctrl0, 0x98)
	check_member (dsi_phy_regs, phy_cmn_timing_ctrl[0], 0xAC)
	check_member (dsi_phy_regs, phy_cmn_phy_status, 0xEC)
	check_member (dsi_phy_regs, phy_ln_regs[0], 0x200)
	check_member (dsi_phy_regs, phy_ln_regs[1], 0x280)
	check_member (dsi_phy_regs, phy_ln_regs[2], 0x300)
	check_member (dsi_phy_regs, phy_ln_regs[3], 0x380)
	check_member (dsi_phy_regs, phy_ln_regs[4], 0x400)
	check_member (dsi_phy_pll_qlink_regs, pll_mash_ctrl, 0xEC)
	check_member (dsi_phy_pll_qlink_regs, pll_ssc_mux_ctrl, 0x108)
	check_member (dsi_phy_pll_qlink_regs, pll_ssc_ctrl, 0x13C)
	check_member (dsi_phy_pll_qlink_regs, pll_freq_tune_accum_init_mux, 0x17C)
	check_member (mdp_intf_regs, intf_panel_format, 0x90)
	check_member (mdp_intf_regs, intf_prof_fetch_start, 0x170)
	check_member (mdp_intf_regs, intf_mux, 0x25C)
	check_member (mdp_ctl_regs, ctl_top, 0x14)
	check_member (mdp_ctl_regs, ctl_intf_active, 0xF4)
	check_member (mdp_ctl_regs, ctl_intf_flush, 0x110)
	check_member (mdp_sspp_regs, sspp_sw_pic_ext_c0_req_pixels, 0x108)
	check_member (mdp_sspp_regs, sspp_sw_pic_ext_c1c2_req_pixels, 0x118)
	check_member (mdp_sspp_regs, sspp_sw_pic_ext_c3_req_pixels, 0x128)
	check_member (vbif_rt_regs, vbif_out_axi_amemtype_conf0, 0x160)
	check_member (vbif_rt_regs, qos_rp_remap[0], 0x550)
void	mdp_dsi_video_config (struct edid *edid)
void	mdp_dsi_video_on (void)

Variables
static struct dsi_regs *const	dsi0 = (void *)DSI0_CTL_BASE
static struct dsi_phy_regs *const	dsi0_phy = (void *)DSI0_PHY_BASE
static struct dsi_phy_pll_qlink_regs *const	phy_pll_qlink = (void *)DSI0_PHY_PLL_QLINK_COM
static struct mdp_intf_regs *const	mdp_intf = (void *)MDP_1_INTF_BASE
static struct mdp_ctl_regs *const	mdp_ctl = (void *)MDP_0_CTL_BASE
static struct mdp_layer_mixer_regs *const	mdp_layer_mixer = (void *)MDP_VP_0_LAYER_MIXER_BASE
static struct mdp_sspp_regs *const	mdp_sspp = (void *)MDP_VP_0_SSPP_BASE
static struct vbif_rt_regs *const	vbif_rt = (void *)MDP_VBIF_RT_BASE

Enumeration Type Documentation

anonymous enum

anonymous enum

Enumerator
MDSS_BASE

Definition at line 329 of file mdssreg.h.

anonymous enum

anonymous enum

Enumerator
MDP_0_CTL_BASE
MDP_VP_0_SSPP_BASE
MDP_VP_0_LAYER_MIXER_BASE
MDP_1_INTF_BASE
MDP_VBIF_RT_BASE
DSI0_CTL_BASE
DSI0_PHY_BASE
DSI0_PHY_DLN0_BASE
DSI0_PHY_DLN1_BASE
DSI0_PHY_DLN2_BASE
DSI0_PHY_DLN3_BASE
DSI0_PHY_CLKLN_BASE
DSI0_PHY_PLL_QLINK_COM

Definition at line 333 of file mdssreg.h.

anonymous enum

anonymous enum

Enumerator
INTF
PERIPH
CWB
ROT
CDM_0
DMA_3
DMA_2
MERGE_3D
DSC
DSPP_3
LAYER_MIXER_5
DSPP_PA_LUTV_3
VIG_3
CTL
WB
DSPP_2
DSPP_1
DSPP_0
DMA_1
DMA_0
LAYER_MIXER_4
LAYER_MIXER_3
LAYER_MIXER_2
LAYER_MIXER_1
LAYER_MIXER_0
DSPP_PA_LUTV_2
DSPP_PA_LUTV_1
DSPP_PA_LUTV_0
VIG_2
VIG_1
VIG_0

Definition at line 350 of file mdssreg.h.

anonymous enum

anonymous enum

Enumerator
DSI_AHBS_HCLK_ON
DSI_AHBM_SCLK_ON
DSI_PCLK_ON
DSI_DSICLK_ON
DSI_BYTECLK_ON
DSI_ESCCLK_ON
DSI_FORCE_ON_DYN_AHBS_HCLK
DSI_FORCE_ON_DYN_AHBM_HCLK
DSI_FORCE_ON_DYN_DSICLK
DSI_FORCE_ON_DYN_BYTECLK
DSI_AHBS_HCLK_HYSTERISIS1_CTRL
DSI_AHBM_HCLK_HYSTERISIS1_CTRL
DSI_DSICLK_HYSTERISIS1_CTRL
DSI_FORCE_ON_DYN_PCLK
DSI_FORCE_ON_LANE_LAYER_TG_BYTECLK
DSI_DMA_CLK_STOP

Definition at line 384 of file mdssreg.h.

anonymous enum

anonymous enum

Enumerator
DSI_CMD_MODE_DMA_DONE_AK
DSI_CMD_MODE_DMA_DONE_STAT
DSI_CMD_MODE_DMA_DONE_MASK
DSI_CMD_MODE_MDP_DONE_AK
DSI_CMD_MODE_MDP_DONE_STAT
DSI_CMD_MODE_MDP_DONE_MASK
DSI_CMD_MDP_STREAM0_DONE_AK
DSI_CMD_MDP_STREAM0_DONE_STAT
DSI_CMD_MDP_STREAM0_DONE_MASK
DSI_VIDEO_MODE_DONE_AK
DSI_VIDEO_MODE_DONE_STAT
DSI_VIDEO_MODE_DONE_MASK
DSI_BTA_DONE_AK
DSI_BTA_DONE_STAT
DSI_BTA_DONE_MASK
DSI_ERROR_AK
DSI_ERROR_STAT
DSI_ERROR_MASK
DSI_DYNAMIC_BLANKING_DMA_DONE_AK
DSI_DYNAMIC_BLANKING_DMA_DONE_STAT
DSI_DYNAMIC_BLANKING_DMA_DONE_MASK
DSI_DYNAMIC_REFRESH_DONE_AK
DSI_DYNAMIC_REFRESH_DONE_STAT
DSI_DYNAMIC_REFRESH_DONE_MASK
DSI_DESKEW_DONE_AK
DSI_DESKEW_DONE_STAT
DSI_DESKEW_DONE_MASK

Definition at line 404 of file mdssreg.h.

anonymous enum

anonymous enum

Enumerator
WR_MEM_START
WR_MEM_CONTINUE
INSERT_DCS_COMMAND

Definition at line 435 of file mdssreg.h.

anonymous enum

anonymous enum

Enumerator
PACKET_TYPE
POWER_MODE
EMBEDDED_MODE
WC_SEL
BROADCAST_MASTER
BROADCAST_EN

Definition at line 442 of file mdssreg.h.

Function Documentation

check_member() [1/36]

check_member	(	dsi_phy_pll_qlink_regs	,
		pll_freq_tune_accum_init_mux	,
		0x17C
	)

check_member() [2/36]

check_member	(	dsi_phy_pll_qlink_regs	,
		pll_mash_ctrl	,
		0xEC
	)

check_member() [3/36]

check_member	(	dsi_phy_pll_qlink_regs	,
		pll_ssc_ctrl	,
		0x13C
	)

check_member() [4/36]

check_member	(	dsi_phy_pll_qlink_regs	,
		pll_ssc_mux_ctrl	,
		0x108
	)

check_member() [5/36]

check_member	(	dsi_phy_regs	,
		phy_cmn_clk_cfg0	,
		0x10
	)

check_member() [6/36]

check_member	(	dsi_phy_regs	,
		phy_cmn_dsi_lane_ctrl0	,
		0x98
	)

check_member() [7/36]

check_member	(	dsi_phy_regs	,
		phy_cmn_phy_status	,
		0xEC
	)

check_member() [8/36]

check_member	(	dsi_phy_regs	,
		phy_cmn_timing_ctrl	[0],
		0xAC
	)

check_member() [9/36]

check_member	(	dsi_phy_regs	,
		phy_ln_regs	[0],
		0x200
	)

check_member() [10/36]

check_member	(	dsi_phy_regs	,
		phy_ln_regs	[1],
		0x280
	)

check_member() [11/36]

check_member	(	dsi_phy_regs	,
		phy_ln_regs	[2],
		0x300
	)

check_member() [12/36]

check_member	(	dsi_phy_regs	,
		phy_ln_regs	[3],
		0x380
	)

check_member() [13/36]

check_member	(	dsi_phy_regs	,
		phy_ln_regs	[4],
		0x400
	)

check_member() [14/36]

check_member	(	dsi_regs	,
		cmd_mode_dma_sw_trigger	,
		0x90
	)

check_member() [15/36]

check_member	(	dsi_regs	,
		cmd_mode_mdp_ctrl2	,
		0x1B8
	)

check_member() [16/36]

check_member	(	dsi_regs	,
		cmd_mode_mdp_stream0_ctrl	,
		0x58
	)

check_member() [17/36]

check_member	(	dsi_regs	,
		err_int_mask0	,
		0x10C
	)

check_member() [18/36]

check_member	(	dsi_regs	,
		hs_timer_ctrl	,
		0xBC
	)

check_member() [19/36]

check_member	(	dsi_regs	,
		misr_cmd_ctrl	,
		0xA0
	)

check_member() [20/36]

check_member	(	dsi_regs	,
		test_pattern_gen_cmd_dma_init_val	,
		0x17c
	)

check_member() [21/36]

check_member	(	dsi_regs	,
		test_pattern_gen_ctrl	,
		0x15c
	)

check_member() [22/36]

check_member	(	dsi_regs	,
		tpg_dma_fifo_reset	,
		0x1EC
	)

check_member() [23/36]

check_member	(	dsi_regs	,
		trig_ctrl	,
		0x84
	)

check_member() [24/36]

check_member	(	dsi_regs	,
		video_compression_mode_ctrl	,
		0x2A0
	)

check_member() [25/36]

check_member	(	dsi_regs	,
		video_mode_active_h	,
		0x24
	)

check_member() [26/36]

check_member	(	mdp_ctl_regs	,
		ctl_intf_active	,
		0xF4
	)

check_member() [27/36]

check_member	(	mdp_ctl_regs	,
		ctl_intf_flush	,
		0x110
	)

check_member() [28/36]

check_member	(	mdp_ctl_regs	,
		ctl_top	,
		0x14
	)

check_member() [29/36]

check_member	(	mdp_intf_regs	,
		intf_mux	,
		0x25C
	)

check_member() [30/36]

check_member	(	mdp_intf_regs	,
		intf_panel_format	,
		0x90
	)

check_member() [31/36]

check_member	(	mdp_intf_regs	,
		intf_prof_fetch_start	,
		0x170
	)

check_member() [32/36]

check_member	(	mdp_sspp_regs	,
		sspp_sw_pic_ext_c0_req_pixels	,
		0x108
	)

check_member() [33/36]

check_member	(	mdp_sspp_regs	,
		sspp_sw_pic_ext_c1c2_req_pixels	,
		0x118
	)

check_member() [34/36]

check_member	(	mdp_sspp_regs	,
		sspp_sw_pic_ext_c3_req_pixels	,
		0x128
	)

check_member() [35/36]

check_member	(	vbif_rt_regs	,
		qos_rp_remap	[0],
		0x550
	)

check_member() [36/36]

check_member	(	vbif_rt_regs	,
		vbif_out_axi_amemtype_conf0	,
		0x160
	)

mdp_dsi_video_config()

void mdp_dsi_video_config

(

struct edid *

edid

)

Definition at line 167 of file mdss.c.

References BIT, mdp_ctl_regs::ctl_intf_active, mdp_ctl_regs::ctl_top, mdp_intf_regs::intf_mux, mdp_ctl, mdp_intf, mdss_intf_fetch_start_config(), mdss_intf_tg_setup(), mdss_layer_mixer_setup(), mdss_source_pipe_config(), mdss_vbif_qos_remapper_setup(), mdss_vbif_setup(), and write32().

Here is the call graph for this function:

mdp_dsi_video_on()

void mdp_dsi_video_on

(

void

)

Definition at line 184 of file mdss.c.

References CTL, mdp_ctl_regs::ctl_flush, mdp_ctl_regs::ctl_intf_flush, INTF, LAYER_MIXER_0, mdp_ctl, VIG_0, and write32().

Here is the call graph for this function:

Variable Documentation

dsi0

struct dsi_regs* const dsi0 = (void *)DSI0_CTL_BASE

static

Definition at line 451 of file mdssreg.h.

dsi0_phy

struct dsi_phy_regs* const dsi0_phy = (void *)DSI0_PHY_BASE

static

Definition at line 452 of file mdssreg.h.

Referenced by dsi_phy_calc_clk_divider(), dsi_phy_pll_global_clk_enable(), dsi_phy_pll_set_source(), dsi_phy_resync_fifo(), dsi_phy_toggle_dln3_tx_dctrl(), mdss_dsi_phy_reset(), mdss_dsi_phy_setup_lanephy(), and mdss_dsi_power_down().

mdp_ctl

struct mdp_ctl_regs* const mdp_ctl = (void *)MDP_0_CTL_BASE

static

Definition at line 455 of file mdssreg.h.

Referenced by mdp_dsi_video_config(), mdp_dsi_video_on(), and mdss_layer_mixer_setup().

mdp_intf

struct mdp_intf_regs* const mdp_intf = (void *)MDP_1_INTF_BASE

static

Definition at line 454 of file mdssreg.h.

Referenced by mdp_dsi_video_config(), mdss_intf_fetch_start_config(), and mdss_intf_tg_setup().

mdp_layer_mixer

struct mdp_layer_mixer_regs* const mdp_layer_mixer = (void *)MDP_VP_0_LAYER_MIXER_BASE

static

Definition at line 456 of file mdssreg.h.

Referenced by mdss_layer_mixer_setup().

mdp_sspp

struct mdp_sspp_regs* const mdp_sspp = (void *)MDP_VP_0_SSPP_BASE

static

Definition at line 457 of file mdssreg.h.

Referenced by mdss_source_pipe_config().

phy_pll_qlink

struct dsi_phy_pll_qlink_regs* const phy_pll_qlink = (void *)DSI0_PHY_PLL_QLINK_COM

static

Definition at line 453 of file mdssreg.h.

Referenced by dsi_phy_pll_bias_enable(), dsi_phy_pll_calcandcommit(), dsi_pll_commit(), dsi_pll_config_hzindep_reg(), and dsi_pll_init_val().

vbif_rt

struct vbif_rt_regs* const vbif_rt = (void *)MDP_VBIF_RT_BASE

static

Definition at line 458 of file mdssreg.h.

Referenced by mdss_vbif_qos_remapper_setup(), and mdss_vbif_setup().