coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
fsp_s_params.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
acpi/acpi.h
>
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#include <
amdblocks/apob_cache.h
>
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#include <
device/pci.h
>
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#include <fsp/api.h>
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#include <
program_loading.h
>
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static
void
fsp_assign_vbios_upds
(
FSP_S_CONFIG
*scfg)
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{
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scfg->vbios_buffer =
CONFIG
(RUN_FSP_GOP) ?
PCI_VGA_RAM_IMAGE_START
: 0;
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}
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void
platform_fsp_silicon_init_params_cb
(FSPS_UPD *supd)
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{
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FSP_S_CONFIG
*scfg = &supd->FspsConfig;
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fsp_assign_vbios_upds
(scfg);
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/*
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* At this point FSP-S has been loaded into RAM. If we were to start loading the APOB
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* before FSP-S was loaded, we would introduce contention onto the SPI bus and
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* slow down the FSP-S read from SPI. Since FSP-S takes a while to execute and performs
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* no SPI operations, we can read the APOB while FSP-S executes.
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*/
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start_apob_cache_read
();
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/*
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* We enqueue the payload to be loaded after the APOB. This might cause a bit of
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* bus contention when loading uCode and OPROMs, but since those calls happen at
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* different points in the boot state machine it's a little harder to sequence all the
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* async loading correctly. So in order to keep the complexity down, we enqueue the
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* payload preload here. The end goal will be to add uCode and OPROM preloading
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* before the payload so that the sequencing is correct.
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*
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* While FSP-S is executing, it's not currently possible to enqueue other transactions
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* because FSP-S doesn't call `thread_yield()`. So the payload will start loading
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* right after FSP-S completes.
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*/
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if
(!
acpi_is_wakeup_s3
())
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payload_preload
();
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}
start_apob_cache_read
void start_apob_cache_read(void)
Definition:
apob_cache.c:100
apob_cache.h
acpi_is_wakeup_s3
static int acpi_is_wakeup_s3(void)
Definition:
acpi.h:9
platform_fsp_silicon_init_params_cb
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
Definition:
fsp_s_params.c:14
fsp_assign_vbios_upds
static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
Definition:
fsp_s_params.c:9
CONFIG
@ CONFIG
Definition:
dsi_common.h:201
FSP_S_CONFIG
#define FSP_S_CONFIG
Definition:
fsp_upd.h:9
acpi.h
pci.h
PCI_VGA_RAM_IMAGE_START
#define PCI_VGA_RAM_IMAGE_START
Definition:
pci_rom.h:12
program_loading.h
payload_preload
void payload_preload(void)
src
soc
amd
cezanne
fsp_s_params.c
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