coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
mmu_operations.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/mmio.h>
4 #include <arch/mmu.h>
5 #include <symbols.h>
6 #include <soc/symbols.h>
7 #include <soc/infracfg.h>
8 #include <soc/mcucfg.h>
9 #include <soc/mmu_operations.h>
10 
12 {
13  mmu_config_range(_dram_dma, REGION_SIZE(dram_dma),
16 }
17 
19 {
20  /* Return L2C SRAM back to L2 cache. Set it to 512KiB which is the max
21  * available L2 cache for A53 in MT8173. */
23  /* turn off the l2c sram clock */
25 }
void mmu_config_range(u32 start_mb, u32 size_mb, enum dcache_policy policy)
Definition: mmu.c:221
static void write32(void *addr, uint32_t val)
Definition: mmio.h:40
#define REGION_SIZE(name)
Definition: symbols.h:10
@ NONSECURE_UNCACHED_MEM
__weak void mtk_soc_after_dram(void)
Definition: mmu_operations.c:8
void mtk_mmu_disable_l2c_sram(void)
void mtk_soc_disable_l2c_sram(void)
@ L2C_SRAM_PDN
Definition: infracfg.h:105
static struct mt8173_infracfg_regs *const mt8173_infracfg
Definition: infracfg.h:100
static struct mt8173_mcucfg_regs *const mt8173_mcucfg
Definition: mcucfg.h:92
u32 mp0_ca7l_cache_config
Definition: mcucfg.h:9