3 #ifndef AMD_PICASSO_SOUTHBRIDGE_H
4 #define AMD_PICASSO_SOUTHBRIDGE_H
17 #define PM_PCI_CTRL 0x08
18 #define FORCE_SLPSTATE_RETRY BIT(25)
20 #define PWR_RESET_CFG 0x10
21 #define TOGGLE_ALL_PWR_GOOD BIT(1)
23 #define PM_SERIRQ_CONF 0x54
24 #define PM_SERIRQ_NUM_BITS_17 0x0000
25 #define PM_SERIRQ_NUM_BITS_18 0x0004
26 #define PM_SERIRQ_NUM_BITS_19 0x0008
27 #define PM_SERIRQ_NUM_BITS_20 0x000c
28 #define PM_SERIRQ_NUM_BITS_21 0x0010
29 #define PM_SERIRQ_NUM_BITS_22 0x0014
30 #define PM_SERIRQ_NUM_BITS_23 0x0018
31 #define PM_SERIRQ_NUM_BITS_24 0x001c
32 #define PM_SERIRQ_MODE BIT(6)
33 #define PM_SERIRQ_ENABLE BIT(7)
35 #define PM_EVT_BLK 0x60
36 #define WAK_STS BIT(15)
37 #define PCIEXPWAK_STS BIT(14)
38 #define RTC_STS BIT(10)
39 #define PWRBTN_STS BIT(8)
40 #define GBL_STS BIT(5)
42 #define TIMER_STS BIT(0)
43 #define PCIEXPWAK_DIS BIT(14)
44 #define RTC_EN BIT(10)
45 #define PWRBTN_EN BIT(8)
47 #define TIMER_STS BIT(0)
48 #define PM1_CNT_BLK 0x62
49 #define PM_TMR_BLK 0x64
50 #define PM_CPU_CTRL 0x66
51 #define PM_GPE0_BLK 0x68
52 #define PM_ACPI_SMI_CMD 0x6a
53 #define PM_ACPI_CONF 0x74
54 #define PM_ACPI_DECODE_STD BIT(0)
55 #define PM_ACPI_GLOBAL_EN BIT(1)
56 #define PM_ACPI_RTC_EN_EN BIT(2)
57 #define PM_ACPI_TIMER_EN_EN BIT(4)
58 #define PM_ACPI_MASK_ARB_DIS BIT(6)
59 #define PM_ACPI_BIOS_RLS BIT(7)
60 #define PM_ACPI_PWRBTNEN_EN BIT(8)
61 #define PM_ACPI_REDUCED_HW_EN BIT(9)
62 #define PM_ACPI_BLOCK_PCIE_PME BIT(24)
63 #define PM_ACPI_PCIE_WAK_MASK BIT(25)
64 #define PM_ACPI_WAKE_AS_GEVENT BIT(27)
65 #define PM_ACPI_NB_PME_GEVENT BIT(28)
66 #define PM_ACPI_RTC_WAKE_EN BIT(29)
67 #define PM_LPC_GATING 0xec
68 #define PM_LPC_AB_NO_BYPASS_EN BIT(2)
69 #define PM_LPC_A20_EN BIT(1)
70 #define PM_LPC_ENABLE BIT(0)
74 #define TOTAL_BITS(a) (8 * sizeof(a))
77 #define GPP_CLK_CNTRL 0x00
78 #define GPP_CLK0_REQ_SHIFT 0
79 #define GPP_CLK1_REQ_SHIFT 2
80 #define GPP_CLK4_REQ_SHIFT 4
81 #define GPP_CLK2_REQ_SHIFT 6
82 #define GPP_CLK3_REQ_SHIFT 8
83 #define GPP_CLK5_REQ_SHIFT 10
84 #define GPP_CLK6_REQ_SHIFT 12
85 #define GPP_CLK_OUTPUT_COUNT 7
86 #define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift))
87 #define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift))
88 #define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift))
89 #define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift))
91 #define MISC_CGPLL_CONFIG1 0x08
92 #define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)
93 #define MISC_CLK_CNTL1 0x40
94 #define BP_X48M0_OUTPUT_EN BIT(2)
96 #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20)
99 #define SATA_MISC_CONTROL_REG 0x40
100 #define SATA_MISC_SUBCLASS_WREN BIT(0)
102 #define SATA_CAPABILITIES_REG 0xfc
103 #define SATA_CAPABILITY_SPM BIT(12)
void fch_init(void *chip_info)
void enable_aoac_devices(void)
void fch_final(void *chip_info)
void wait_for_aoac_enabled(unsigned int dev)
void fch_early_init(void)