coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Functions | |
void | fch_pre_init (void) |
void | fch_early_init (void) |
void | fch_init (void *chip_info) |
void | fch_final (void *chip_info) |
void | enable_aoac_devices (void) |
void | wait_for_aoac_enabled (unsigned int dev) |
#define BM_STS BIT(4) |
Definition at line 41 of file southbridge.h.
#define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ |
Definition at line 94 of file southbridge.h.
#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) |
Definition at line 92 of file southbridge.h.
#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ |
Definition at line 96 of file southbridge.h.
#define FORCE_SLPSTATE_RETRY BIT(25) |
Definition at line 18 of file southbridge.h.
#define GBL_EN BIT(5) |
Definition at line 46 of file southbridge.h.
#define GBL_STS BIT(5) |
Definition at line 40 of file southbridge.h.
#define GPE0_LIMIT 32 |
Definition at line 73 of file southbridge.h.
#define GPP_CLK0_REQ_SHIFT 0 |
Definition at line 78 of file southbridge.h.
#define GPP_CLK1_REQ_SHIFT 2 |
Definition at line 79 of file southbridge.h.
#define GPP_CLK2_REQ_SHIFT 6 |
Definition at line 81 of file southbridge.h.
#define GPP_CLK3_REQ_SHIFT 8 |
Definition at line 82 of file southbridge.h.
#define GPP_CLK4_REQ_SHIFT 4 |
Definition at line 80 of file southbridge.h.
#define GPP_CLK5_REQ_SHIFT 10 |
Definition at line 83 of file southbridge.h.
#define GPP_CLK6_REQ_SHIFT 12 |
Definition at line 84 of file southbridge.h.
#define GPP_CLK_CNTRL 0x00 |
Definition at line 77 of file southbridge.h.
#define GPP_CLK_OUTPUT_COUNT 7 |
Definition at line 85 of file southbridge.h.
#define GPP_CLK_REQ_EXT | ( | clk_shift | ) | (0x1 << (clk_shift)) |
Definition at line 88 of file southbridge.h.
#define GPP_CLK_REQ_MASK | ( | clk_shift | ) | (0x3 << (clk_shift)) |
Definition at line 86 of file southbridge.h.
#define GPP_CLK_REQ_OFF | ( | clk_shift | ) | (0x0 << (clk_shift)) |
Definition at line 89 of file southbridge.h.
#define GPP_CLK_REQ_ON | ( | clk_shift | ) | (0x3 << (clk_shift)) |
Definition at line 87 of file southbridge.h.
#define MISC_CGPLL_CONFIG1 0x08 |
Definition at line 91 of file southbridge.h.
#define MISC_CLK_CNTL1 0x40 |
Definition at line 93 of file southbridge.h.
#define PCIEXPWAK_DIS BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */ |
Definition at line 43 of file southbridge.h.
#define PCIEXPWAK_STS BIT(14) |
Definition at line 37 of file southbridge.h.
#define PM1_CNT_BLK 0x62 |
Definition at line 48 of file southbridge.h.
#define PM1_LIMIT 16 |
Definition at line 72 of file southbridge.h.
#define PM_ACPI_BIOS_RLS BIT(7) |
Definition at line 59 of file southbridge.h.
#define PM_ACPI_BLOCK_PCIE_PME BIT(24) |
Definition at line 62 of file southbridge.h.
#define PM_ACPI_CONF 0x74 |
Definition at line 53 of file southbridge.h.
#define PM_ACPI_DECODE_STD BIT(0) |
Definition at line 54 of file southbridge.h.
#define PM_ACPI_GLOBAL_EN BIT(1) |
Definition at line 55 of file southbridge.h.
#define PM_ACPI_MASK_ARB_DIS BIT(6) |
Definition at line 58 of file southbridge.h.
#define PM_ACPI_NB_PME_GEVENT BIT(28) |
Definition at line 65 of file southbridge.h.
#define PM_ACPI_PCIE_WAK_MASK BIT(25) |
Definition at line 63 of file southbridge.h.
#define PM_ACPI_PWRBTNEN_EN BIT(8) |
Definition at line 60 of file southbridge.h.
#define PM_ACPI_REDUCED_HW_EN BIT(9) |
Definition at line 61 of file southbridge.h.
#define PM_ACPI_RTC_EN_EN BIT(2) |
Definition at line 56 of file southbridge.h.
#define PM_ACPI_RTC_WAKE_EN BIT(29) |
Definition at line 66 of file southbridge.h.
#define PM_ACPI_SMI_CMD 0x6a |
Definition at line 52 of file southbridge.h.
#define PM_ACPI_TIMER_EN_EN BIT(4) |
Definition at line 57 of file southbridge.h.
#define PM_ACPI_WAKE_AS_GEVENT BIT(27) |
Definition at line 64 of file southbridge.h.
#define PM_CPU_CTRL 0x66 |
Definition at line 50 of file southbridge.h.
#define PM_EVT_BLK 0x60 |
Definition at line 35 of file southbridge.h.
#define PM_GPE0_BLK 0x68 |
Definition at line 51 of file southbridge.h.
#define PM_LPC_A20_EN BIT(1) |
Definition at line 69 of file southbridge.h.
#define PM_LPC_AB_NO_BYPASS_EN BIT(2) |
Definition at line 68 of file southbridge.h.
#define PM_LPC_ENABLE BIT(0) |
Definition at line 70 of file southbridge.h.
#define PM_LPC_GATING 0xec |
Definition at line 67 of file southbridge.h.
#define PM_PCI_CTRL 0x08 |
Definition at line 17 of file southbridge.h.
#define PM_SERIRQ_CONF 0x54 |
Definition at line 23 of file southbridge.h.
#define PM_SERIRQ_ENABLE BIT(7) |
Definition at line 33 of file southbridge.h.
#define PM_SERIRQ_MODE BIT(6) |
Definition at line 32 of file southbridge.h.
#define PM_SERIRQ_NUM_BITS_17 0x0000 |
Definition at line 24 of file southbridge.h.
#define PM_SERIRQ_NUM_BITS_18 0x0004 |
Definition at line 25 of file southbridge.h.
#define PM_SERIRQ_NUM_BITS_19 0x0008 |
Definition at line 26 of file southbridge.h.
#define PM_SERIRQ_NUM_BITS_20 0x000c |
Definition at line 27 of file southbridge.h.
#define PM_SERIRQ_NUM_BITS_21 0x0010 |
Definition at line 28 of file southbridge.h.
#define PM_SERIRQ_NUM_BITS_22 0x0014 |
Definition at line 29 of file southbridge.h.
#define PM_SERIRQ_NUM_BITS_23 0x0018 |
Definition at line 30 of file southbridge.h.
#define PM_SERIRQ_NUM_BITS_24 0x001c |
Definition at line 31 of file southbridge.h.
#define PM_TMR_BLK 0x64 |
Definition at line 49 of file southbridge.h.
#define PWR_RESET_CFG 0x10 |
Definition at line 20 of file southbridge.h.
#define PWRBTN_EN BIT(8) |
Definition at line 45 of file southbridge.h.
#define PWRBTN_STS BIT(8) |
Definition at line 39 of file southbridge.h.
#define RTC_EN BIT(10) |
Definition at line 44 of file southbridge.h.
#define RTC_STS BIT(10) |
Definition at line 38 of file southbridge.h.
#define SATA_CAPABILITIES_REG 0xfc |
Definition at line 102 of file southbridge.h.
#define SATA_CAPABILITY_SPM BIT(12) |
Definition at line 103 of file southbridge.h.
#define SATA_MISC_CONTROL_REG 0x40 |
Definition at line 99 of file southbridge.h.
#define SATA_MISC_SUBCLASS_WREN BIT(0) |
Definition at line 100 of file southbridge.h.
#define TIMER_STS BIT(0) |
Definition at line 47 of file southbridge.h.
#define TIMER_STS BIT(0) |
Definition at line 47 of file southbridge.h.
#define TOGGLE_ALL_PWR_GOOD BIT(1) |
Definition at line 21 of file southbridge.h.
#define TOTAL_BITS | ( | a | ) | (8 * sizeof(a)) |
Definition at line 74 of file southbridge.h.
#define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */ |
Definition at line 36 of file southbridge.h.
Definition at line 71 of file early_fch.c.
Definition at line 35 of file early_fch.c.