coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _SOC_QUALCOMM_QCS405_GPIO_H_
4 #define _SOC_QUALCOMM_QCS405_GPIO_H_
5 
6 #include <types.h>
7 #include <soc/addressmap.h>
8 
9 typedef struct {
10  u32 addr;
11 } gpio_t;
12 
13 #define TLMM_TILE_SIZE 0x00400000
14 #define TLMM_GPIO_OFF_DELTA 0x00001000
15 #define TLMM_GPIO_TILE_NUM 3
16 
17 #define TLMM_GPIO_IN_OUT_OFF 0x4
18 #define TLMM_GPIO_ID_STATUS_OFF 0x10
19 
20 /* GPIO INTR CFG MASK */
21 #define GPIO_INTR_DECT_CTL_MASK 0x3
22 #define GPIO_INTR_RAW_STATUS_EN_MASK 0x1
23 
24 /* GPIO INTR CFG SHIFT */
25 #define GPIO_INTR_DECT_CTL_SHIFT 2
26 #define GPIO_INTR_RAW_STATUS_EN_SHIFT 4
27 
28 /* GPIO INTR STATUS MASK */
29 #define GPIO_INTR_STATUS_MASK 0x1
30 
31 /* GPIO INTR RAW STATUS */
32 #define GPIO_INTR_RAW_STATUS_ENABLE 1
33 #define GPIO_INTR_RAW_STATUS_DISABLE 0
34 
35 /* GPIO INTR STATUS */
36 #define GPIO_INTR_STATUS_ENABLE 1
37 #define GPIO_INTR_STATUS_DISABLE 0
38 
39 /* GPIO TLMM: Direction */
40 #define GPIO_INPUT 0
41 #define GPIO_OUTPUT 1
42 
43 /* GPIO TLMM: Pullup/Pulldown */
44 #define GPIO_NO_PULL 0
45 #define GPIO_PULL_DOWN 1
46 #define GPIO_KEEPER 2
47 #define GPIO_PULL_UP 3
48 
49 /* GPIO TLMM: Drive Strength */
50 #define GPIO_2MA 0
51 #define GPIO_4MA 1
52 #define GPIO_6MA 2
53 #define GPIO_8MA 3
54 #define GPIO_10MA 4
55 #define GPIO_12MA 5
56 #define GPIO_14MA 6
57 #define GPIO_16MA 7
58 
59 /* GPIO TLMM: Status */
60 #define GPIO_DISABLE 0
61 #define GPIO_ENABLE 1
62 
63 /* GPIO TLMM: Mask */
64 #define GPIO_CFG_PULL_BMSK 0x3
65 #define GPIO_CFG_FUNC_BMSK 0xF
66 #define GPIO_CFG_DRV_BMSK 0x7
67 #define GPIO_CFG_OE_BMSK 0x1
68 
69 /* GPIO TLMM: Shift */
70 #define GPIO_CFG_PULL_SHFT 0
71 #define GPIO_CFG_FUNC_SHFT 2
72 #define GPIO_CFG_DRV_SHFT 6
73 #define GPIO_CFG_OE_SHFT 9
74 
75 /* GPIO IO: Mask */
76 #define GPIO_IO_IN_BMSK 0x1
77 #define GPIO_IO_OUT_BMSK 0x1
78 
79 /* GPIO IO: Shift */
80 #define GPIO_IO_IN_SHFT 0
81 #define GPIO_IO_OUT_SHFT 1
82 
83 /* GPIO ID STATUS: Mask */
84 #define GPIO_ID_STATUS_BMSK 0x1
85 
86 /* GPIO MAX Valid # */
87 #define GPIO_NUM_MAX 149
88 
89 #define GPIO_FUNC_GPIO 0
90 
91 #define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR})
92 
93 #define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \
94 GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \
95 GPIO##index##_FUNC_##func1 = 1, \
96 GPIO##index##_FUNC_##func2 = 2, \
97 GPIO##index##_FUNC_##func3 = 3, \
98 GPIO##index##_FUNC_##func4 = 4, \
99 GPIO##index##_FUNC_##func5 = 5, \
100 GPIO##index##_FUNC_##func6 = 6, \
101 GPIO##index##_FUNC_##func7 = 7
102 
103 enum {
104  PIN(0, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
105  PIN(1, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
106  PIN(2, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
107  PIN(3, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
108  PIN(4, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
109  PIN(5, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
110  PIN(6, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
111  PIN(7, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
112  PIN(8, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
113  PIN(9, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
114  PIN(10, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
115  PIN(11, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
116  PIN(12, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
117  PIN(13, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
118  PIN(14, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
119  PIN(15, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
120  PIN(16, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
121  PIN(17, NORTH, BLSP_UART_TX_A, BLSP_SPI_MOSI, RES_3, RES_4, RES_5,
122  RES_6, RES_7),
123  PIN(18, NORTH, BLSP_UART_RX_A, BLSP_SPI_MISO, RES_3, RES_4, RES_5,
124  RES_6, RES_7),
125  PIN(19, NORTH, BLSP_UART_CTS_N, AUD_CDC_INT2, RES_3, BLSP_SPI_CS_N,
126  RES_5, RES_6, RES_7),
127  PIN(20, NORTH, BLSP_UART_RFR_N, RES_2, RES_3, BLSP_SPI_CLK, RES_5,
128  RES_6, RES_7),
129  PIN(21, SOUTH, M_VOC_EXT_VFR_REF_IRQ_2, RES_2, RES_3, RES_4,
130  RES_5, RES_6, RES_7),
131  PIN(22, NORTH, BLSP_UART_TX, BLSP_SPI_MOSI_A, ASDIV1, RES_4,
132  RES_5, RES_6, RES_7),
133  PIN(23, NORTH, BLSP_UART_RX, BLSP_SPI_MISO_A, ASDIV2, RES_4,
134  RES_5, RES_6, RES_7),
135  PIN(24, NORTH, BLSP_UART_CTS_N, BLSP_I2C_SDA, BLSP_SPI_CS_N_A,
136  RES_4, RES_5, RES_6, RES_7),
137  PIN(25, NORTH, BLSP_UART_RFR_N, BLSP_I2C_SCL, BLSP_SPI_CLK_A,
138  RES_4, RES_5, RES_6, RES_7),
139  PIN(26, EAST, RES_1, BLSP_UART_TX, BLSP_SPI_MOSI, RES_4, RES_5,
140  RES_6, RES_7),
141  PIN(27, EAST, RES_1, BLSP_UART_RX, BLSP_SPI_MISO, RES_4, RES_5,
142  RES_6, RES_7),
143  PIN(28, EAST, RES_1, BLSP_UART_CTS_N, RES_3, BLSP_SPI_CS_N, RES_5,
144  RES_6, RES_7),
145  PIN(29, EAST, RES_1, BLSP_UART_RFR_N, RES_3, BLSP_SPI_CLK, RES_5,
146  RES_6, RES_7),
147  PIN(30, NORTH, RES_1, BLSP_UART_TX, RES_3, RES_4, RES_5, RES_6,
148  RES_7),
149  PIN(31, NORTH, RES_1, BLSP_UART_RX, RES_3, RES_4, RES_5, RES_6,
150  RES_7),
151  PIN(32, NORTH, RES_1, BLSP_UART_CTS_N, BLSP_I2C_SDA, RES_4, RES_5,
152  RES_6, RES_7),
153  PIN(33, NORTH, RES_1, BLSP_UART_RFR_N, BLSP_I2C_SCL, RES_4, RES_5,
154  RES_6, RES_7),
155  PIN(34, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
156  PIN(35, SOUTH, PCIE_CLK_REQ, RES_2, RES_3, RES_4, RES_5, RES_6,
157  RES_7),
158  PIN(36, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
159  PIN(37, NORTH, NFC_IRQ, BLSP_SPI_MOSI, RES_3, RES_4, RES_5, RES_6,
160  RES_7),
161  PIN(38, NORTH, RES_1, BLSP_SPI_MISO, AUDIO_TS_IN, RES_4, RES_5,
162  RES_6, RES_7),
163  PIN(39, EAST, RES_1, RES_2, BLSP_UART_TX_B, RES_4, RES_5, RES_6,
164  RES_7),
165  PIN(40, EAST, RES_1, RES_2, BLSP_UART_RX_B, RES_4, RES_5, RES_6,
166  RES_7),
167  PIN(41, EAST, RES_1, BLSP_I2C_SDA_B, RES_3, RES_4, RES_5, RES_6,
168  RES_7),
169  PIN(42, EAST, RES_1, BLSP_I2C_SCL_B, RES_3, RES_4, RES_5, RES_6,
170  RES_7),
171  PIN(43, EAST, RES_1, PWM_LED11, RES_3, RES_4, RES_5, RES_6, RES_7),
172  PIN(44, EAST, RES_1, PWM_LED12, BLSP_SPI_CS1_N, RES_4, RES_5,
173  RES_6, RES_7),
174  PIN(45, EAST, RES_1, PWM_LED13, BLSP_SPI_CS2_N, RES_4, RES_5,
175  RES_6, RES_7),
176  PIN(46, EAST, RES_1, PWM_LED14, BLSP_SPI_CS3_N, RES_4, RES_5,
177  RES_6, RES_7),
178  PIN(47, EAST, RES_1, PWM_LED15, BLSP_SPI_MOSI_B, RES_4, RES_5,
179  RES_6, RES_7),
180  PIN(48, EAST, RES_1, PWM_LED16, BLSP_SPI_MISO_B, RES_4, RES_5,
181  RES_6, RES_7),
182  PIN(49, EAST, RES_1, PWM_LED17, BLSP_SPI_CS_N_B, RES_4, RES_5,
183  RES_6, RES_7),
184  PIN(50, EAST, RES_1, PWM_LED18, BLSP_SPI_CLK_B, RES_4, RES_5,
185  RES_6, RES_7),
186  PIN(51, EAST, RES_1, PWM_LED19, EXT_MCLK1_B, RES_4, RES_5, RES_6,
187  RES_7),
188  PIN(52, EAST, RES_1, PWM_LED20, RES_3, I2S_3_SCK_B, RES_5, RES_6,
189  RES_7),
190  PIN(53, EAST, RES_1, PWM_LED21, I2S_3_WS_B, RES_4, RES_5, RES_6,
191  RES_7),
192  PIN(54, EAST, RES_1, I2S_3_DATA0_B, RES_3, RES_4, RES_5, RES_6,
193  RES_7),
194  PIN(55, EAST, RES_1, I2S_3_DATA1_B, RES_3, RES_4, RES_5, RES_6,
195  RES_7),
196  PIN(56, EAST, RES_1, RES_2, I2S_3_DATA2_B, RES_4, RES_5, RES_6,
197  RES_7),
198  PIN(57, EAST, RES_1, RES_2, I2S_3_DATA3_B, RES_4, RES_5, RES_6,
199  RES_7),
200  PIN(58, EAST, RGB_DATA_B, RES_2, RES_3, RES_4, RES_5, RES_6,
201  RES_7),
202  PIN(59, EAST, RGB_DATA_B, RES_2, RES_3, RES_4, RES_5, RES_6,
203  RES_7),
204  PIN(60, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
205  PIN(61, NORTH, RGMII_INT, RES_2, RES_3, RES_4, RES_5, RES_6,
206  RES_7),
207  PIN(62, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
208  PIN(63, NORTH, RGMII_CK_TX, RES_2, RES_3, RES_4, RES_5, RES_6,
209  RES_7),
210  PIN(64, NORTH, RGMII_TX_3, RES_2, RES_3, RES_4, RES_5, RES_6,
211  RES_7),
212  PIN(65, NORTH, RGMII_TX_2, RES_2, RES_3, RES_4, RES_5, RES_6,
213  RES_7),
214  PIN(66, NORTH, RGMII_TX_1, RES_2, RES_3, RES_4, RES_5, RES_6,
215  RES_7),
216  PIN(67, NORTH, RGMII_TX_0, RES_2, RES_3, RES_4, RES_5, RES_6,
217  RES_7),
218  PIN(68, NORTH, RGMII_CTL_TX, RES_2, RES_3, RES_4, RES_5, RES_6,
219  RES_7),
220  PIN(69, NORTH, RGMII_CK_RX, RES_2, RES_3, RES_4, RES_5, RES_6,
221  RES_7),
222  PIN(70, NORTH, RGMII_RX_3, RES_2, RES_3, RES_4, RES_5, RES_6,
223  RES_7),
224  PIN(71, NORTH, RGMII_RX_2, RES_2, RES_3, RES_4, RES_5, RES_6,
225  RES_7),
226  PIN(72, NORTH, RGMII_RX_1, RES_2, RES_3, RES_4, RES_5, RES_6,
227  RES_7),
228  PIN(73, NORTH, RGMII_RX_0, RES_2, RES_3, RES_4, RES_5, RES_6,
229  RES_7),
230  PIN(74, NORTH, RGMII_CTL_RX, RES_2, RES_3, RES_4, RES_5, RES_6,
231  RES_7),
232  PIN(75, NORTH, RGMII_MDIO, RES_2, RES_3, RES_4, RES_5, RES_6,
233  RES_7),
234  PIN(76, NORTH, RGMII_MDC, RES_2, RES_3, RES_4, RES_5, RES_6,
235  RES_7),
236  PIN(77, NORTH, IR_IN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
237  PIN(78, EAST, RGB_DATA_G, RES_2, RES_3, RES_4, RES_5, RES_6,
238  RES_7),
239  PIN(79, EAST, RGB_DATA_G, RES_2, RES_3, RES_4, RES_5, RES_6,
240  RES_7),
241  PIN(80, EAST, RGB_DATA_R, RES_2, RES_3, RES_4, RES_5, RES_6,
242  RES_7),
243  PIN(81, EAST, RGB_DATA_R, RES_2, RES_3, RES_4, RES_5, RES_6,
244  RES_7),
245  PIN(82, NORTH, BLSP_UART_TX, BLSP_SPI_MOSI, SD_WRITE_PROTECT,
246  RES_4, RES_5, RES_6, RES_7),
247  PIN(83, NORTH, BLSP_UART_RX, BLSP_SPI_MISO, RES_3, RES_4, RES_5,
248  RES_6, RES_7),
249  PIN(84, NORTH, BLSP_UART_CTS_N, BLSP_I2C_SDA, BLSP_SPI_CS_N,
250  RES_4, RES_5, RES_6, RES_7),
251  PIN(85, NORTH, BLSP_UART_RFR_N, BLSP_I2C_SCL, BLSP_SPI_CLK, RES_4,
252  RES_5, RES_6, RES_7),
253  PIN(86, EAST, RES_1, MCLK_IN1, RES_3, RES_4, RES_5, RES_6, RES_7),
254  PIN(87, EAST, I2S_1_SCK, DSD_CLK_A, RES_3, RES_4, RES_5, RES_6,
255  RES_7),
256  PIN(88, EAST, I2S_1_WS, I2S_1_DATA0_DSD0, RES_3, RES_4, RES_5,
257  RES_6, RES_7),
258  PIN(89, EAST, I2S_1_DATA0, I2S_1_DATA1_DSD1, RES_3, RES_4, RES_5,
259  RES_6, RES_7),
260  PIN(90, EAST, I2S_1_DATA1, I2S_1_DATA2_DSD2, RES_3, RES_4, RES_5,
261  RES_6, RES_7),
262  PIN(91, EAST, I2S_1_DATA2, I2S_1_DATA3_DSD3, RES_3, RES_4, RES_5,
263  RES_6, RES_7),
264  PIN(92, EAST, I2S_1_DATA3, I2S_1_DATA4_DSD4, RES_3, RES_4, RES_5,
265  RES_6, RES_7),
266  PIN(93, EAST, I2S_1_DATA4, PWM_LED22, I2S_1_DATA5_DSD5, RES_4,
267  RES_5, RES_6, RES_7),
268  PIN(94, EAST, I2S_1_DATA5, PWM_LED23, I2S_1_DATA6_MIR, RES_4,
269  RES_5, RES_6, RES_7),
270  PIN(95, EAST, RES_1, PWM_LED1, I2S_1_DATA7_MIR, RES_4, RES_5,
271  RES_6, RES_7),
272  PIN(96, EAST, RES_1, PWM_LED2, RES_3, RES_4, RES_5, RES_6, RES_7),
273  PIN(97, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
274  PIN(98, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
275  PIN(99, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
276  PIN(100, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
277  PIN(101, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
278  PIN(102, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
279  PIN(103, EAST, RES_1, MCLK_IN2, RES_3, RES_4, RES_5, RES_6, RES_7),
280  PIN(104, EAST, I2S_3_SCK_A, RES_2, RES_3, RES_4, RES_5, RES_6,
281  RES_7),
282  PIN(105, EAST, I2S_3_WS_A, RES_2, RES_3, RES_4, RES_5, RES_6,
283  RES_7),
284  PIN(106, EAST, I2S_3_DATA0_A, RES_2, HDMI_HOT_PLUG_MIR, RES_4,
285  RES_5, RES_6, RES_7),
286  PIN(107, EAST, I2S_3_DATA1_A, RES_2, RES_3, RES_4, RES_5, RES_6,
287  RES_7),
288  PIN(108, EAST, I2S_3_DATA2_A, RES_2, RES_3, PWM_LED3, RES_5,
289  RES_6, RES_7),
290  PIN(109, EAST, I2S_3_DATA3_A, RES_2, PWM_LED4, RES_4, RES_5,
291  RES_6, RES_7),
292  PIN(110, EAST, RES_1, RES_2, DSD_CLK_B, PWM_LED5, RES_5, RES_6,
293  RES_7),
294  PIN(111, EAST, RES_1, I2S_4_DATA0_DSD0, PWM_LED6, RES_4, RES_5,
295  RES_6, RES_7),
296  PIN(112, EAST, RES_1, I2S_4_DATA1_DSD1, PWM_LED7, RES_4, RES_5,
297  RES_6, RES_7),
298  PIN(113, EAST, RES_1, I2S_4_DATA2_DSD2, PWM_LED8, RES_4, RES_5,
299  RES_6, RES_7),
300  PIN(114, EAST, RES_1, I2S_4_DATA3_DSD3, PWM_LED24, RES_4, RES_5,
301  RES_6, RES_7),
302  PIN(115, EAST, RES_1, I2S_4_DATA4_DSD4, RES_3, RES_4, RES_5,
303  RES_6, RES_7),
304  PIN(116, EAST, I2S_4_DATA5_DSD5, SPKR_DAC0, RES_3, RES_4, RES_5,
305  RES_6, RES_7),
306  PIN(117, NORTH, BLSP_I2C_SDA, BLSP_SPI_CS_N, PWM_LED9, RES_4,
307  RES_5, RES_6, RES_7),
308  PIN(118, NORTH, BLSP_I2C_SCL, BLSP_SPI_CLK, PWM_LED10, RES_4,
309  RES_5, RES_6, RES_7),
310  PIN(119, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
311 };
312 
313 enum gpio_irq_type {
314  IRQ_TYPE_LEVEL = 0,
315  IRQ_TYPE_RISING_EDGE = 1,
316  IRQ_TYPE_FALLING_EDGE = 2,
317  IRQ_TYPE_DUAL_EDGE = 3,
318 };
319 
320 struct tlmm_gpio {
321  uint32_t cfg;
322  uint32_t in_out;
323  uint32_t intr_cfg;
324  uint32_t intr_status;
325 };
326 
327 void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,
328  uint32_t drive_str, uint32_t enable);
329 void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull);
330 int gpio_irq_status(gpio_t gpio);
331 
332 #endif // _SOC_QUALCOMM_QCS405_GPIO_H_
pull
#define pull
Definition: asmlib.h:26
addr
static u32 addr
Definition: cirrus.c:14
type
unsigned int type
Definition: edid.c:57
gpio_irq_type
gpio_irq_type
Definition: gpio_common.h:54
gpio_t
uint32_t gpio_t
Definition: gpio.h:9
gpio_input_irq
void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull)
Definition: gpio.c:65
IRQ_TYPE_DUAL_EDGE
@ IRQ_TYPE_DUAL_EDGE
Definition: gpio.h:317
IRQ_TYPE_RISING_EDGE
@ IRQ_TYPE_RISING_EDGE
Definition: gpio.h:315
IRQ_TYPE_FALLING_EDGE
@ IRQ_TYPE_FALLING_EDGE
Definition: gpio.h:316
IRQ_TYPE_LEVEL
@ IRQ_TYPE_LEVEL
Definition: gpio.h:314
gpio_irq_status
int gpio_irq_status(gpio_t gpio)
Definition: gpio.c:79
PIN
#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7)
Definition: gpio.h:93
gpio_configure
void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, uint32_t drive_str, uint32_t enable)
Definition: gpio.c:7
uint32_t
unsigned int uint32_t
Definition: stdint.h:14
u32
uint32_t u32
Definition: stdint.h:51
gpio_t
Definition: gpio_base.h:7
gpio
Definition: pinmux.c:36
tlmm_gpio
Definition: gpio_common.h:91
tlmm_gpio::intr_cfg
uint32_t intr_cfg
Definition: gpio_common.h:94
tlmm_gpio::intr_status
uint32_t intr_status
Definition: gpio_common.h:95
tlmm_gpio::cfg
uint32_t cfg
Definition: gpio_common.h:92
tlmm_gpio::in_out
uint32_t in_out
Definition: gpio_common.h:93