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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <acpi/acpi.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <device/mmio.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <intelblocks/pmc.h>
#include <soc/iomap.h>
#include <soc/pm.h>
#include <soc/pmc.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
Go to the source code of this file.
Functions | |
static void | pch_power_options (struct device *dev) |
int | pmc_soc_get_resources (struct pmc_resource_config *cfg) |
static void | pch_set_acpi_mode (void) |
void | pmc_soc_init (struct device *dev) |
Definition at line 18 of file pmc.c.
Referenced by pmc_soc_init().
Definition at line 33 of file pmc.c.
References acpi_is_wakeup_s3(), APM_CNT_ACPI_DISABLE, and apm_control().
Referenced by pmc_soc_init().
int pmc_soc_get_resources | ( | struct pmc_resource_config * | cfg | ) |
Definition at line 21 of file pmc.c.
References pmc_resource_config::abase_addr, pmc_resource_config::abase_offset, pmc_resource_config::abase_size, DEFAULT_PMBASE, DEFAULT_PMBASE_SIZE, DEFAULT_PWRM_BASE, DEFAULT_PWRM_SIZE, PMC_ACPI_BASE, PMC_PWRM_BASE, pmc_resource_config::pwrmbase_addr, pmc_resource_config::pwrmbase_offset, and pmc_resource_config::pwrmbase_size.
Definition at line 40 of file pmc.c.
References ACPI_TIM_DIS, BIOS_DEBUG, CONFIG, MASK_PMC_PWRM_BASE, pch_power_options(), PCH_PWRM_ACPI_TMR_CTL, pch_set_acpi_mode(), PCI_COMMAND, PCI_COMMAND_IO, PCI_COMMAND_MASTER, PCI_COMMAND_MEMORY, pci_read_config32(), pci_write_config16(), PMC_PWRM_BASE, printk, and setbits8.