coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
smihandler.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <acpi/acpi.h>
4 #include <arch/io.h>
5 #include <console/console.h>
6 #include <cpu/x86/smm.h>
7 #include <elog.h>
8 
10 #include "ec.h"
11 
12 #include <soc/nvs.h>
13 #include <soc/pm.h>
14 
15 /* The wake gpio is SUS_GPIO[0]. */
16 #define WAKE_GPIO_EN SUS_GPIO_EN0
17 
19 {
22  uint32_t pm1_cnt;
23 
24  /* Log this event */
25  if (cmd)
27 
28  switch (cmd) {
30  printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
31 
32  /* Go to S5 */
33  pm1_cnt = inl(pmbase + PM1_CNT);
34  pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
35  outl(pm1_cnt, pmbase + PM1_CNT);
36  break;
37  }
38 
39  return cmd;
40 }
41 
42 /* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
43  * this includes the enable bits in the lower 16 bits. */
44 void mainboard_smi_gpi(uint32_t alt_gpio_smi)
45 {
46  if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
47  /* Process all pending events */
48  while (mainboard_smi_ec() != 0);
49  }
50 }
51 
53 {
54  /* Disable USB charging if required */
55  switch (slp_typ) {
56  case ACPI_S3:
57  if (gnvs->s3u0 == 0)
60  if (gnvs->s3u1 == 0)
63 
64  /* Enable wake events */
66  /* Enable wake pin in GPE block. */
68  break;
69  case ACPI_S5:
70  if (gnvs->s5u0 == 0)
73  if (gnvs->s5u1 == 0)
76 
77  /* Enable wake events */
79  break;
80  }
81 
82  /* Disable SCI and SMI events */
85 
86  /* Clear pending events that may trigger immediate wake */
88  ;
89 }
90 
92 {
93  switch (apmc) {
96  /* Clear all pending events */
98  ;
100  break;
103  /* Clear all pending events */
105  ;
107  break;
108  }
109  return 0;
110 }
#define PM1_CNT
Definition: pm.h:27
void enable_gpe(uint32_t mask)
Definition: pmutil.c:194
#define ELOG_TYPE_EC_EVENT
Definition: elog.h:90
#define printk(level,...)
Definition: stdlib.h:16
void __weak mainboard_smi_sleep(u8 slp_typ)
Definition: smihandler.c:210
int __weak mainboard_smi_apmc(u8 data)
Definition: smihandler.c:209
void __weak mainboard_smi_gpi(u32 gpi_sts)
Definition: smihandler.c:208
u32 inl(u16 port)
void outl(u32 val, u16 port)
int google_chromeec_set_wake_mask(uint64_t mask)
Definition: ec.c:1131
int google_chromeec_set_smi_mask(uint64_t mask)
Definition: ec.c:1125
int google_chromeec_set_usb_charge_mode(uint8_t port_id, enum usb_charge_mode mode)
Definition: ec.c:1143
int google_chromeec_set_sci_mask(uint64_t mask)
Definition: ec.c:1119
enum host_event_code google_chromeec_get_event(void)
Definition: ec_i2c.c:242
@ EC_HOST_EVENT_NONE
Definition: ec_commands.h:654
@ EC_HOST_EVENT_LID_CLOSED
Definition: ec_commands.h:655
@ USB_CHARGE_MODE_DISABLED
Definition: ec_commands.h:3240
@ ACPI_S5
Definition: acpi.h:1385
@ ACPI_S3
Definition: acpi.h:1383
#define APM_CNT_ACPI_DISABLE
Definition: smm.h:21
#define APM_CNT_ACPI_ENABLE
Definition: smm.h:22
static int elog_gsmi_add_event_byte(u8 event_type, u8 data)
Definition: elog.h:46
#define SLP_EN
Definition: pmc.h:62
#define SLP_TYP_S5
Definition: pmc.h:69
#define SLP_TYP_SHIFT
Definition: pmc.h:63
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
#define MAINBOARD_EC_S5_WAKE_EVENTS
Definition: ec.h:32
#define MAINBOARD_EC_SCI_EVENTS
Definition: ec.h:12
#define MAINBOARD_EC_SMI_EVENTS
Definition: ec.h:28
#define EC_SMI_GPI
Definition: ec.h:10
#define MAINBOARD_EC_S3_WAKE_EVENTS
Definition: ec.h:37
static uint8_t mainboard_smi_ec(void)
Definition: smihandler.c:18
#define WAKE_GPIO_EN
Definition: smihandler.c:16
struct global_nvs * gnvs
u16 get_pmbase(void)
Definition: smihandler.c:20
u16 pmbase
Definition: smihandler.c:25
unsigned short uint16_t
Definition: stdint.h:11
unsigned int uint32_t
Definition: stdint.h:14
unsigned char uint8_t
Definition: stdint.h:8
u8 s5u1
Definition: nvs.h:33
u8 s3u0
Definition: nvs.h:34
u8 s3u1
Definition: nvs.h:35
u8 s5u0
Definition: nvs.h:32