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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mp.h>
#include <cpu/intel/common/common.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h>
#include <cpu/x86/name.h>
#include <cpu/intel/smm_reloc.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/sgx.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/systemagent.h>
#include <types.h>
#include "chip.h"
Go to the source code of this file.
Functions | |
bool | cpu_soc_is_in_untrusted_mode (void) |
static void | configure_misc (void) |
static void | configure_c_states (void) |
void | soc_core_init (struct device *cpu) |
static void | per_cpu_smm_trigger (void) |
void | smm_lock (void) |
static void | vmx_configure (void *unused) |
static void | fc_lock_configure (void *unused) |
static void | post_mp_init (void) |
static void | soc_fsp_load (void) |
void | soc_init_cpus (struct bus *cpu_bus) |
int | soc_skip_ucode_update (u32 current_patch_id, u32 new_patch_id) |
Variables | |
static const struct mp_ops | mp_ops |
Definition at line 69 of file cpu.c.
References C_STATE_LATENCY_CONTROL_0_LIMIT, C_STATE_LATENCY_CONTROL_1_LIMIT, C_STATE_LATENCY_CONTROL_2_LIMIT, C_STATE_LATENCY_CONTROL_3_LIMIT, C_STATE_LATENCY_CONTROL_4_LIMIT, C_STATE_LATENCY_CONTROL_5_LIMIT, msr_struct::hi, IRTL_1024_NS, IRTL_VALID, msr_struct::lo, MSR_C_STATE_LATENCY_CONTROL_0, MSR_C_STATE_LATENCY_CONTROL_1, MSR_C_STATE_LATENCY_CONTROL_2, MSR_C_STATE_LATENCY_CONTROL_3, MSR_C_STATE_LATENCY_CONTROL_4, MSR_C_STATE_LATENCY_CONTROL_5, and wrmsr().
Referenced by soc_core_init().
Definition at line 38 of file cpu.c.
References config_of_soc, cpu_set_eist(), msr_struct::hi, IA32_MISC_ENABLE, IA32_PACKAGE_THERM_INTERRUPT, IA32_THERM_INTERRUPT, msr_struct::lo, MSR_POWER_CTL, POWER_CTL_C1E_MASK, rdmsr(), and wrmsr().
Referenced by soc_core_init().
Definition at line 28 of file cpu.c.
References CONFIG, ENABLE_IA_UNTRUSTED, msr_struct::lo, MSR_BIOS_DONE, and rdmsr().
Definition at line 166 of file cpu.c.
References set_feature_ctrl_lock().
Referenced by post_mp_init().
Definition at line 143 of file cpu.c.
References smm_relocate().
Definition at line 171 of file cpu.c.
References BIOS_CRIT, CB_SUCCESS, CONFIG, cpu_set_max_ratio(), fc_lock_configure(), global_smi_enable_no_pwrbtn(), mp_run_on_all_cpus(), NULL, printk, sgx_configure(), smm_lock(), and vmx_configure().
Definition at line 149 of file cpu.c.
References BIOS_DEBUG, C_BASE_SEG, D_LCK, G_SMRAME, pci_write_config8(), pcidev_path_on_root(), printk, SA_DEVFN_ROOT, and SMRAM.
Definition at line 108 of file cpu.c.
References CONFIG, configure_c_states(), configure_dca_cap(), configure_misc(), enable_lapic_tpr(), enable_pm_timer_emulation(), enable_turbo(), ENERGY_POLICY_NORMAL, mca_configure(), prmrr_core_configure(), set_aesni_lock(), and set_energy_perf_bias().
Definition at line 223 of file cpu.c.
References configure_tcc_thermal_target(), and mp_init_with_smm().
Definition at line 232 of file cpu.c.
References msr_struct::lo, MSR_PRMRR_PHYS_BASE, MTRR_CAP_MSR, MTRR_CAP_PRMRR, and rdmsr().
Referenced by intel_microcode_load_unlocked().
Definition at line 161 of file cpu.c.
References set_feature_ctrl_vmx().
Referenced by post_mp_init().