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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include "variant.h"
Go to the source code of this file.
Functions | |
void | mainboard_config_rcba (void) |
void | mb_get_spd_map (struct spd_info *spdi) |
Definition at line 8 of file romstage.c.
References D20IP, D20IP_XHCI, D20IR, D21IR, D22IP, D22IP_MEI1IP, D22IR, D23IR, D26IP, D26IP_E2P, D27IP, D27IP_ZIP, D27IR, D28IP, D28IP_P1IP, D28IP_P3IP, D28IP_P4IP, D28IR, D29IP, D29IP_E1P, D29IR, D31IP, D31IP_SIP, D31IP_SIP2, D31IP_SMIP, D31IP_TTIP, D31IR, DIR_ROUTE, INTA, INTB, INTC, NOINT, PIRQA, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH, RCBA16, and RCBA32.
Definition at line 43 of file romstage.c.
References spd_info::addresses, spd_info::spd_index, SPD_MEMORY_DOWN, variant_get_spd_index(), and variant_is_dual_channel().