coreboot
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spm.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef SOC_MEDIATEK_MT8192_SPM_H
4 #define SOC_MEDIATEK_MT8192_SPM_H
5 
6 #include <soc/addressmap.h>
7 #include <soc/mtcmos.h>
8 #include <types.h>
9 
10 /* SPM READ/WRITE CFG */
11 #define SPM_PROJECT_CODE 0xb16
12 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
13 
14 /* POWERON_CONFIG_EN (0x10006000+0x000) */
15 #define BCLK_CG_EN_LSB (1U << 0) /* 1b */
16 
17 /* SPM_CLK_CON (0x10006000+0x00C) */
18 #define REG_SYSCLK1_SRC_MD2_SRCCLKENA (1U << 28) /* 1b */
19 
20 /* PCM_CON0 (0x10006000+0x018) */
21 #define PCM_CK_EN_LSB (1U << 2) /* 1b */
22 #define PCM_SW_RESET_LSB (1U << 15) /* 1b */
23 
24 /* PCM_CON1 (0x10006000+0x01C) */
25 #define RG_IM_SLAVE_LSB (1U << 0) /* 1b */
26 #define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */
27 #define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */
28 #define SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */
29 #define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */
30 #define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */
31 #define REG_EVENT_LOCK_EN_LSB (1U << 12) /* 1b */
32 #define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */
33 
34 /* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */
35 #define SPM_WAKEUP_EVENT_MASK_BIT0 (1U << 0) /* 1b */
36 #define SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B (1U << 24) /* 1b */
37 
38 /* DDR_EN_DBC_CON1 (0x10006000+0x0EC) */
39 #define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 0) /* 1b */
40 
41 /* SPM_DVFS_MISC (0x10006000+0x4AC) */
42 #define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */
43 #define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */
44 
45 /* SPM_SW_FLAG_0 (0x10006000+0x600) */
46 #define SPM_FLAG_DISABLE_VCORE_DVS (1U << 3) /* 1b */
47 #define SPM_FLAG_DISABLE_VCORE_DFS (1U << 4) /* 1b */
48 #define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10) /* 1b */
49 
50 /* SYS_TIMER_CON (0x10006000+0x98C) */
51 #define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */
52 
53 /* MD32PCM_CFGREG_SW_RSTN (0x10006000+0xA00) */
54 #define MD32PCM_CFGREG_SW_RSTN_RESET (1U << 0) /* 1b */
55 
56 /**************************************
57  * Config and Parameter
58  **************************************/
59 #define POWER_ON_VAL1_DEF 0x80015860
60 #define SPM_WAKEUP_EVENT_MASK_DEF 0xefffffff
61 #define SPM_ACK_CHK_3_SEL_HW_S1 0x00350098
62 #define SPM_ACK_CHK_3_HW_S1_CNT 0x1
63 #define SPM_ACK_CHK_3_CON_HW_MODE_TRIG 0x800
64 #define SPM_ACK_CHK_3_CON_EN 0x110
65 #define SPM_ACK_CHK_3_CON_CLR_ALL 0x2
66 #define SPM_BUS_PROTECT_MASK_B_DEF 0xffffffff
67 #define SPM_BUS_PROTECT2_MASK_B_DEF 0xffffffff
68 #define MD32PCM_DMA0_CON_VAL 0x0003820e
69 #define MD32PCM_DMA0_START_VAL 0x00008000
70 #define MD32PCM_CFGREG_SW_RSTN_RUN 0x1
71 #define SPM_DVFS_LEVEL_DEF 0x00000001
72 #define SPM_DVS_DFS_LEVEL_DEF 0x00010001
73 #define SPM_RESOURCE_ACK_CON0_DEF 0x00000000
74 #define SPM_RESOURCE_ACK_CON1_DEF 0x00000000
75 #define SPM_RESOURCE_ACK_CON2_DEF 0xcccc4e4e
76 #define SPM_RESOURCE_ACK_CON3_DEF 0x00000000
77 #define ARMPLL_CLK_SEL_DEF 0x3ff
78 #define DDR_EN_DBC_CON0_DEF 0x154
79 #define SPM_SYSCLK_SETTLE 0x60fe
80 #define SPM_INIT_DONE_US 20
81 #define PCM_WDT_TIMEOUT (30 * 32768)
82 #define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
83 
84 /**************************************
85  * Define and Declare
86  **************************************/
87 /* SPM_IRQ_MASK */
88 #define ISRM_TWAM (1U << 2)
89 #define ISRM_PCM_RETURN (1U << 3)
90 #define ISRM_RET_IRQ_AUX 0x3fe00
91 #define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX)
92 #define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
93 
94 /* SPM_IRQ_STA */
95 #define ISRS_TWAM (1U << 2)
96 #define ISRS_PCM_RETURN (1U << 3)
97 #define ISRC_TWAM ISRS_TWAM
98 #define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN
99 #define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
100 
101 /* PCM_PWR_IO_EN */
102 #define PCM_PWRIO_EN_R0 (1U << 0)
103 #define PCM_PWRIO_EN_R7 (1U << 7)
104 #define PCM_RF_SYNC_R0 (1U << 16)
105 #define PCM_RF_SYNC_R6 (1U << 22)
106 #define PCM_RF_SYNC_R7 (1U << 23)
107 
108 /* SPM_SWINT */
109 #define PCM_SW_INT_ALL 0x3ff
110 
111 struct pwr_ctrl {
112  u32 pcm_flags;
113  u32 pcm_flags_cust;
114  u32 pcm_flags_cust_set;
115  u32 pcm_flags_cust_clr;
116  u32 pcm_flags1;
117  u32 pcm_flags1_cust;
118  u32 pcm_flags1_cust_set;
119  u32 pcm_flags1_cust_clr;
120  u32 timer_val;
121  u32 timer_val_cust;
122  u32 timer_val_ramp_en;
123  u32 timer_val_ramp_en_sec;
124  u32 wake_src;
125  u32 wake_src_cust;
126  u32 wakelock_timer_val;
127  u8 wdt_disable;
128 
129  /* Auto-gen Start */
130 
131  /* SPM_CLK_CON */
132  u8 reg_srcclken0_ctl;
133  u8 reg_srcclken1_ctl;
134  u8 reg_spm_lock_infra_dcm;
135  u8 reg_srcclken_mask;
136  u8 reg_md1_c32rm_en;
137  u8 reg_md2_c32rm_en;
138  u8 reg_clksq0_sel_ctrl;
139  u8 reg_clksq1_sel_ctrl;
140  u8 reg_srcclken0_en;
141  u8 reg_srcclken1_en;
142  u32 reg_sysclk0_src_mask_b;
143  u32 reg_sysclk1_src_mask_b;
144 
145  /* SPM_AP_STANDBY_CON */
146  u8 reg_wfi_op;
147  u8 reg_wfi_type;
148  u8 reg_mp0_cputop_idle_mask;
149  u8 reg_mp1_cputop_idle_mask;
150  u8 reg_mcusys_idle_mask;
151  u8 reg_md_apsrc_1_sel;
152  u8 reg_md_apsrc_0_sel;
153  u8 reg_conn_apsrc_sel;
154 
155  /* SPM_SRC6_MASK */
156  u8 reg_dpmaif_srcclkena_mask_b;
157  u8 reg_dpmaif_infra_req_mask_b;
158  u8 reg_dpmaif_apsrc_req_mask_b;
159  u8 reg_dpmaif_vrf18_req_mask_b;
160  u8 reg_dpmaif_ddr_en_mask_b;
161 
162  /* SPM_SRC_REQ */
163  u8 reg_spm_apsrc_req;
164  u8 reg_spm_f26m_req;
165  u8 reg_spm_infra_req;
166  u8 reg_spm_vrf18_req;
167  u8 reg_spm_ddr_en_req;
168  u8 reg_spm_dvfs_req;
169  u8 reg_spm_sw_mailbox_req;
170  u8 reg_spm_sspm_mailbox_req;
171  u8 reg_spm_adsp_mailbox_req;
172  u8 reg_spm_scp_mailbox_req;
173 
174  /* SPM_SRC_MASK */
175  u8 reg_md_srcclkena_0_mask_b;
176  u8 reg_md_srcclkena2infra_req_0_mask_b;
177  u8 reg_md_apsrc2infra_req_0_mask_b;
178  u8 reg_md_apsrc_req_0_mask_b;
179  u8 reg_md_vrf18_req_0_mask_b;
180  u8 reg_md_ddr_en_0_mask_b;
181  u8 reg_md_srcclkena_1_mask_b;
182  u8 reg_md_srcclkena2infra_req_1_mask_b;
183  u8 reg_md_apsrc2infra_req_1_mask_b;
184  u8 reg_md_apsrc_req_1_mask_b;
185  u8 reg_md_vrf18_req_1_mask_b;
186  u8 reg_md_ddr_en_1_mask_b;
187  u8 reg_conn_srcclkena_mask_b;
188  u8 reg_conn_srcclkenb_mask_b;
189  u8 reg_conn_infra_req_mask_b;
190  u8 reg_conn_apsrc_req_mask_b;
191  u8 reg_conn_vrf18_req_mask_b;
192  u8 reg_conn_ddr_en_mask_b;
193  u8 reg_conn_vfe28_mask_b;
194  u8 reg_srcclkeni0_srcclkena_mask_b;
195  u8 reg_srcclkeni0_infra_req_mask_b;
196  u8 reg_srcclkeni1_srcclkena_mask_b;
197  u8 reg_srcclkeni1_infra_req_mask_b;
198  u8 reg_srcclkeni2_srcclkena_mask_b;
199  u8 reg_srcclkeni2_infra_req_mask_b;
200  u8 reg_infrasys_apsrc_req_mask_b;
201  u8 reg_infrasys_ddr_en_mask_b;
202  u8 reg_md32_srcclkena_mask_b;
203  u8 reg_md32_infra_req_mask_b;
204  u8 reg_md32_apsrc_req_mask_b;
205  u8 reg_md32_vrf18_req_mask_b;
206  u8 reg_md32_ddr_en_mask_b;
207 
208  /* SPM_SRC2_MASK */
209  u8 reg_scp_srcclkena_mask_b;
210  u8 reg_scp_infra_req_mask_b;
211  u8 reg_scp_apsrc_req_mask_b;
212  u8 reg_scp_vrf18_req_mask_b;
213  u8 reg_scp_ddr_en_mask_b;
214  u8 reg_audio_dsp_srcclkena_mask_b;
215  u8 reg_audio_dsp_infra_req_mask_b;
216  u8 reg_audio_dsp_apsrc_req_mask_b;
217  u8 reg_audio_dsp_vrf18_req_mask_b;
218  u8 reg_audio_dsp_ddr_en_mask_b;
219  u8 reg_ufs_srcclkena_mask_b;
220  u8 reg_ufs_infra_req_mask_b;
221  u8 reg_ufs_apsrc_req_mask_b;
222  u8 reg_ufs_vrf18_req_mask_b;
223  u8 reg_ufs_ddr_en_mask_b;
224  u8 reg_disp0_apsrc_req_mask_b;
225  u8 reg_disp0_ddr_en_mask_b;
226  u8 reg_disp1_apsrc_req_mask_b;
227  u8 reg_disp1_ddr_en_mask_b;
228  u8 reg_gce_infra_req_mask_b;
229  u8 reg_gce_apsrc_req_mask_b;
230  u8 reg_gce_vrf18_req_mask_b;
231  u8 reg_gce_ddr_en_mask_b;
232  u8 reg_apu_srcclkena_mask_b;
233  u8 reg_apu_infra_req_mask_b;
234  u8 reg_apu_apsrc_req_mask_b;
235  u8 reg_apu_vrf18_req_mask_b;
236  u8 reg_apu_ddr_en_mask_b;
237  u8 reg_cg_check_srcclkena_mask_b;
238  u8 reg_cg_check_apsrc_req_mask_b;
239  u8 reg_cg_check_vrf18_req_mask_b;
240  u8 reg_cg_check_ddr_en_mask_b;
241 
242  /* SPM_SRC3_MASK */
243  u8 reg_dvfsrc_event_trigger_mask_b;
244  u8 reg_sw2spm_int0_mask_b;
245  u8 reg_sw2spm_int1_mask_b;
246  u8 reg_sw2spm_int2_mask_b;
247  u8 reg_sw2spm_int3_mask_b;
248  u8 reg_sc_adsp2spm_wakeup_mask_b;
249  u8 reg_sc_sspm2spm_wakeup_mask_b;
250  u8 reg_sc_scp2spm_wakeup_mask_b;
251  u8 reg_csyspwrreq_mask;
252  u8 reg_spm_srcclkena_reserved_mask_b;
253  u8 reg_spm_infra_req_reserved_mask_b;
254  u8 reg_spm_apsrc_req_reserved_mask_b;
255  u8 reg_spm_vrf18_req_reserved_mask_b;
256  u8 reg_spm_ddr_en_reserved_mask_b;
257  u8 reg_mcupm_srcclkena_mask_b;
258  u8 reg_mcupm_infra_req_mask_b;
259  u8 reg_mcupm_apsrc_req_mask_b;
260  u8 reg_mcupm_vrf18_req_mask_b;
261  u8 reg_mcupm_ddr_en_mask_b;
262  u8 reg_msdc0_srcclkena_mask_b;
263  u8 reg_msdc0_infra_req_mask_b;
264  u8 reg_msdc0_apsrc_req_mask_b;
265  u8 reg_msdc0_vrf18_req_mask_b;
266  u8 reg_msdc0_ddr_en_mask_b;
267  u8 reg_msdc1_srcclkena_mask_b;
268  u8 reg_msdc1_infra_req_mask_b;
269  u8 reg_msdc1_apsrc_req_mask_b;
270  u8 reg_msdc1_vrf18_req_mask_b;
271  u8 reg_msdc1_ddr_en_mask_b;
272 
273  /* SPM_SRC4_MASK */
274  u32 ccif_event_mask_b;
275  u8 reg_bak_psri_srcclkena_mask_b;
276  u8 reg_bak_psri_infra_req_mask_b;
277  u8 reg_bak_psri_apsrc_req_mask_b;
278  u8 reg_bak_psri_vrf18_req_mask_b;
279  u8 reg_bak_psri_ddr_en_mask_b;
280  u8 reg_dramc0_md32_infra_req_mask_b;
281  u8 reg_dramc0_md32_vrf18_req_mask_b;
282  u8 reg_dramc1_md32_infra_req_mask_b;
283  u8 reg_dramc1_md32_vrf18_req_mask_b;
284  u8 reg_conn_srcclkenb2pwrap_mask_b;
285  u8 reg_dramc0_md32_wakeup_mask;
286  u8 reg_dramc1_md32_wakeup_mask;
287 
288  /* SPM_SRC5_MASK */
289  u32 reg_mcusys_merge_apsrc_req_mask_b;
290  u32 reg_mcusys_merge_ddr_en_mask_b;
291  u8 reg_msdc2_srcclkena_mask_b;
292  u8 reg_msdc2_infra_req_mask_b;
293  u8 reg_msdc2_apsrc_req_mask_b;
294  u8 reg_msdc2_vrf18_req_mask_b;
295  u8 reg_msdc2_ddr_en_mask_b;
296  u8 reg_pcie_srcclkena_mask_b;
297  u8 reg_pcie_infra_req_mask_b;
298  u8 reg_pcie_apsrc_req_mask_b;
299  u8 reg_pcie_vrf18_req_mask_b;
300  u8 reg_pcie_ddr_en_mask_b;
301 
302  /* SPM_WAKEUP_EVENT_MASK */
303  u32 reg_wakeup_event_mask;
304 
305  /* SPM_WAKEUP_EVENT_EXT_MASK */
306  u32 reg_ext_wakeup_event_mask;
307 
308  /* Auto-gen End */
309 };
310 
311 enum {
312  DISP_PWR_STA_MASK = 0x1 << 20,
313  DISP_SRAM_PDN_MASK = 0x1 << 8,
314  DISP_SRAM_ACK_MASK = 0x1 << 12,
315  AUDIO_PWR_STA_MASK = 0x1 << 21,
316  AUDIO_SRAM_PDN_MASK = 0x1 << 8,
317  AUDIO_SRAM_ACK_MASK = 0x1 << 12,
318 };
319 
320 struct mtk_spm_regs {
321  u32 poweron_config_set;
322  u32 spm_power_on_val0;
323  u32 spm_power_on_val1;
324  u32 spm_clk_con;
325  u32 spm_clk_settle;
326  u32 spm_ap_standby_con;
327  u32 pcm_con0;
328  u32 pcm_con1;
329  u32 spm_power_on_val2;
330  u32 spm_power_on_val3;
331  u32 pcm_reg_data_ini;
332  u32 pcm_pwr_io_en;
333  u32 pcm_timer_val;
334  u32 pcm_wdt_val;
335  u32 spm_src6_mask;
336  u32 reserved0;
337  u32 spm_sw_rst_con;
338  u32 spm_sw_rst_con_set;
339  u32 spm_sw_rst_con_clr;
340  u32 vs1_psr_mask_b;
341  u32 vs2_psr_mask_b;
342  u32 reserved1[12];
343  u32 md32_clk_con;
344  u32 spm_sram_rsv_con;
345  u32 spm_swint;
346  u32 spm_swint_set;
347  u32 spm_swint_clr;
348  u32 spm_scp_mailbox;
349  u32 scp_spm_mailbox;
350  u32 spm_twam_con;
351  u32 spm_twam_window_len;
352  u32 spm_twam_idle_sel;
353  u32 spm_scp_irq;
354  u32 spm_cpu_wakeup_event;
355  u32 spm_irq_mask;
356  u32 spm_src_req;
357  u32 spm_src_mask;
358  u32 spm_src2_mask;
359  u32 spm_src3_mask;
360  u32 spm_src4_mask;
361  u32 spm_src5_mask;
362  u32 spm_wakeup_event_mask;
363  u32 spm_wakeup_event_ext_mask;
364  u32 spm_twam_event_clear;
365  u32 scp_clk_con;
366  u32 pcm_debug_con;
367  u32 ahb_bus_con;
368  u32 ddr_en_dbc_con0;
369  u32 ddr_en_dbc_con1;
370  u32 spm_resource_ack_con0;
371  u32 spm_resource_ack_con1;
372  u32 spm_resource_ack_con2;
373  u32 spm_resource_ack_con3;
374  u32 pcm_reg0_data;
375  u32 pcm_reg2_data;
376  u32 pcm_reg6_data;
377  u32 pcm_reg7_data;
378  u32 pcm_reg13_data;
379  u32 src_req_sta0;
380  u32 src_req_sta1;
381  u32 src_req_sta2;
382  u32 pcm_timer_out;
383  u32 pcm_wdt_out;
384  u32 spm_irq_sta;
385  u32 src_req_sta4;
386  u32 md32pcm_wakeup_sta;
387  u32 md32pcm_event_sta;
388  u32 spm_wakeup_sta;
389  u32 spm_wakeup_ext_sta;
390  u32 spm_wakeup_misc;
391  u32 mm_dvfs_halt;
392  u32 reserved2[2];
393  u32 bus_protect_rdy;
394  u32 bus_protect1_rdy;
395  u32 bus_protect2_rdy;
396  u32 bus_protect3_rdy;
397  u32 subsys_idle_sta;
398  u32 pcm_sta;
399  u32 src_req_sta3;
400  u32 pwr_status;
401  u32 pwr_status_2nd;
402  u32 cpu_pwr_status;
403  u32 other_pwr_status;
404  u32 spm_vtcxo_event_count_sta;
405  u32 spm_infra_event_count_sta;
406  u32 spm_vrf18_event_count_sta;
407  u32 spm_apsrc_event_count_sta;
408  u32 spm_ddren_event_count_sta;
409  u32 md32pcm_sta;
410  u32 md32pcm_pc;
411  u32 reserved3[3];
412  u32 dvfsrc_event_sta;
413  u32 bus_protect4_rdy;
414  u32 bus_protect5_rdy;
415  u32 bus_protect6_rdy;
416  u32 bus_protect7_rdy;
417  u32 bus_protect8_rdy;
418  u32 reserved4[5];
419  u32 spm_twam_last_sta0;
420  u32 spm_twam_last_sta1;
421  u32 spm_twam_last_sta2;
422  u32 spm_twam_last_sta3;
423  u32 spm_twam_curr_sta0;
424  u32 spm_twam_curr_sta1;
425  u32 spm_twam_curr_sta2;
426  u32 spm_twam_curr_sta3;
427  u32 spm_twam_timer_out;
428  u32 spm_cg_check_sta;
429  u32 spm_dvfs_sta;
430  u32 spm_dvfs_opp_sta;
431  u32 spm_mcusys_pwr_con;
432  u32 spm_cputop_pwr_con;
433  u32 spm_cpu0_pwr_con;
434  u32 spm_cpu1_pwr_con;
435  u32 spm_cpu2_pwr_con;
436  u32 spm_cpu3_pwr_con;
437  u32 spm_cpu4_pwr_con;
438  u32 spm_cpu5_pwr_con;
439  u32 spm_cpu6_pwr_con;
440  u32 spm_cpu7_pwr_con;
441  u32 reserved5;
442  u32 armpll_clk_con;
443  u32 mcusys_idle_sta;
444  u32 gic_wakeup_sta;
445  u32 cpu_spare_con;
446  u32 cpu_spare_con_set;
447  u32 cpu_spare_con_clr;
448  u32 armpll_clk_sel;
449  u32 ext_int_wakeup_req;
450  u32 ext_int_wakeup_req_set;
451  u32 ext_int_wakeup_req_clr;
452  u32 reserved6[3];
453  u32 mp0_cpu0_irq_mask;
454  u32 mp0_cpu1_irq_mask;
455  u32 mp0_cpu2_irq_mask;
456  u32 mp0_cpu3_irq_mask;
457  u32 mp1_cpu0_irq_mask;
458  u32 mp1_cpu1_irq_mask;
459  u32 mp1_cpu2_irq_mask;
460  u32 mp1_cpu3_irq_mask;
461  u32 mp0_cpu0_wfi_en;
462  u32 mp0_cpu1_wfi_en;
463  u32 mp0_cpu2_wfi_en;
464  u32 mp0_cpu3_wfi_en;
465  u32 mp0_cpu4_wfi_en;
466  u32 mp0_cpu5_wfi_en;
467  u32 mp0_cpu6_wfi_en;
468  u32 mp0_cpu7_wfi_en;
469  u32 root_cputop_addr;
470  u32 root_core_addr;
471  u32 reserved7[10];
472  u32 spm2sw_mailbox_0;
473  u32 spm2sw_mailbox_1;
474  u32 spm2sw_mailbox_2;
475  u32 spm2sw_mailbox_3;
476  u32 sw2spm_int;
477  u32 sw2spm_int_set;
478  u32 sw2spm_int_clr;
479  u32 sw2spm_mailbox_0;
480  u32 sw2spm_mailbox_1;
481  u32 sw2spm_mailbox_2;
482  u32 sw2spm_mailbox_3;
483  u32 sw2spm_cfg;
484  u32 md1_pwr_con;
485  u32 conn_pwr_con;
486  u32 mfg0_pwr_con;
487  u32 mfg1_pwr_con;
488  u32 mfg2_pwr_con;
489  u32 mfg3_pwr_con;
490  u32 mfg4_pwr_con;
491  u32 mfg5_pwr_con;
492  u32 mfg6_pwr_con;
493  u32 ifr_pwr_con;
494  u32 ifr_sub_pwr_con;
495  u32 dpy_pwr_con;
496  u32 isp_pwr_con;
497  u32 isp2_pwr_con;
498  u32 ipe_pwr_con;
499  u32 vde_pwr_con;
500  u32 vde2_pwr_con;
501  u32 ven_pwr_con;
502  u32 ven_core1_pwr_con;
503  u32 mdp_pwr_con;
504  u32 dis_pwr_con;
505  u32 audio_pwr_con;
506  u32 adsp_pwr_con;
507  u32 cam_pwr_con;
508  u32 cam_rawa_pwr_con;
509  u32 cam_rawb_pwr_con;
510  u32 cam_rawc_pwr_con;
511  u32 sysram_con;
512  u32 sysrom_con;
513  u32 sspm_sram_con;
514  u32 scp_sram_con;
515  u32 dpy_shu_sram_con;
516  u32 ufs_sram_con;
517  u32 devapc_ifr_sram_con;
518  u32 devapc_subifr_sram_con;
519  u32 devapc_acp_sram_con;
520  u32 usb_sram_con;
521  u32 dummy_sram_con;
522  u32 md_ext_buck_iso_con;
523  u32 ext_buck_iso;
524  u32 dxcc_sram_con;
525  u32 msdc_pwr_con;
526  u32 debugtop_sram_con;
527  u32 dp_tx_pwr_con;
528  u32 dpmaif_sram_con;
529  u32 dpy_shu2_con;
530  u32 dramc_mcu2_sram_con;
531  u32 dramc_mcu_sram_con;
532  u32 mcupm_pwr_con;
533  u32 dpy2_pwr_con;
534  u32 peri_pwr_con;
535  u32 reserved8[13];
536  u32 spm_mem_ck_sel;
537  u32 spm_bus_protect_mask_b;
538  u32 spm_bus_protect1_mask_b;
539  u32 spm_bus_protect2_mask_b;
540  u32 spm_bus_protect3_mask_b;
541  u32 spm_bus_protect4_mask_b;
542  u32 spm_emi_bw_mode;
543  u32 ap2md_peer_wakeup;
544  u32 ulposc_con;
545  u32 spm2mm_con;
546  u32 spm_bus_protect5_mask_b;
547  u32 spm2mcupm_con;
548  u32 ap_mdsrc_req;
549  u32 spm2emi_enter_ulpm;
550  u32 spm2md_dvfs_con;
551  u32 md2spm_dvfs_con;
552  u32 spm_bus_protect6_mask_b;
553  u32 spm_bus_protect7_mask_b;
554  u32 spm_bus_protect8_mask_b;
555  u32 spm_pll_con;
556  u32 cpu_dvfs_req;
557  u32 spm_dram_mcu_sw_con0;
558  u32 spm_dram_mcu_sw_con1;
559  u32 spm_dram_mcu_sw_con2;
560  u32 spm_dram_mcu_sw_con3;
561  u32 spm_dram_mcu_sw_con4;
562  u32 spm_dram_mcu_sta_0;
563  u32 spm_dram_mcu_sta_1;
564  u32 spm_dram_mcu_sta_2;
565  u32 spm_dram_mcu_sw_sel_0;
566  u32 relay_dvfs_level;
567  u32 reserved9;
568  u32 dramc_dpy_clk_sw_con_0;
569  u32 dramc_dpy_clk_sw_con_1;
570  u32 dramc_dpy_clk_sw_con_2;
571  u32 dramc_dpy_clk_sw_con_3;
572  u32 dramc_dpy_clk_sw_sel_0;
573  u32 dramc_dpy_clk_sw_sel_1;
574  u32 dramc_dpy_clk_sw_sel_2;
575  u32 dramc_dpy_clk_sw_sel_3;
576  u32 dramc_dpy_clk_spm_con;
577  u32 spm_dvfs_level;
578  u32 spm_cirq_con;
579  u32 spm_dvfs_misc;
580  u32 spm_vs1_vs2_rc_con;
581  u32 rg_module_sw_cg_0_mask_req_0;
582  u32 rg_module_sw_cg_0_mask_req_1;
583  u32 rg_module_sw_cg_0_mask_req_2;
584  u32 rg_module_sw_cg_1_mask_req_0;
585  u32 rg_module_sw_cg_1_mask_req_1;
586  u32 rg_module_sw_cg_1_mask_req_2;
587  u32 rg_module_sw_cg_2_mask_req_0;
588  u32 rg_module_sw_cg_2_mask_req_1;
589  u32 rg_module_sw_cg_2_mask_req_2;
590  u32 rg_module_sw_cg_3_mask_req_0;
591  u32 rg_module_sw_cg_3_mask_req_1;
592  u32 rg_module_sw_cg_3_mask_req_2;
593  u32 pwr_status_mask_req_0;
594  u32 pwr_status_mask_req_1;
595  u32 pwr_status_mask_req_2;
596  u32 spm_cg_check_con;
597  u32 spm_src_rdy_sta;
598  u32 spm_dvs_dfs_level;
599  u32 spm_force_dvfs;
600  u32 reserved10[64];
601  u32 spm_sw_flag_0;
602  u32 spm_sw_debug_0;
603  u32 spm_sw_flag_1;
604  u32 reserved11[8];
605  u32 spm_sw_rsv_7;
606  u32 spm_sw_rsv_8;
607  u32 reserved12[203];
608  u32 spm_ack_chk_con_3;
609  u32 spm_ack_chk_pc_3;
610  u32 spm_ack_chk_sel_3;
611  u32 spm_ack_chk_timer_3;
612  u32 reserved13[7];
613  u32 sys_timer_con;
614  u32 reserved14[28];
615  u32 md32pcm_cfgreg_sw_rstn;
616  u32 reserved15[127];
617  u32 md32pcm_dma0_src;
618  u32 md32pcm_dma0_dst;
619  u32 md32pcm_dma0_wppt;
620  u32 md32pcm_dma0_wpto;
621  u32 md32pcm_dma0_count;
622  u32 md32pcm_dma0_con;
623  u32 md32pcm_dma0_start;
624  u32 reserved16[2];
625  u32 md32pcm_dma0_rlct;
626 };
627 check_member(mtk_spm_regs, poweron_config_set, 0x0);
628 check_member(mtk_spm_regs, vs2_psr_mask_b, 0x50);
629 check_member(mtk_spm_regs, md32_clk_con, 0x84);
630 check_member(mtk_spm_regs, mm_dvfs_halt, 0x144);
631 check_member(mtk_spm_regs, bus_protect_rdy, 0x150);
632 check_member(mtk_spm_regs, md32pcm_pc, 0x194);
633 check_member(mtk_spm_regs, dvfsrc_event_sta, 0x1a4);
634 check_member(mtk_spm_regs, bus_protect8_rdy, 0x1b8);
635 check_member(mtk_spm_regs, spm_twam_last_sta0, 0x1d0);
636 check_member(mtk_spm_regs, ext_int_wakeup_req_clr, 0x250);
637 check_member(mtk_spm_regs, mp0_cpu0_irq_mask, 0x260);
638 check_member(mtk_spm_regs, root_core_addr, 0x2a4);
639 check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x2d0);
640 check_member(mtk_spm_regs, peri_pwr_con, 0x3c8);
641 check_member(mtk_spm_regs, spm_mem_ck_sel, 0x400);
642 check_member(mtk_spm_regs, ulposc_con, 0x420);
643 check_member(mtk_spm_regs, spm_force_dvfs, 0x4fc);
644 check_member(mtk_spm_regs, spm_sw_flag_0, 0x600);
645 check_member(mtk_spm_regs, spm_sw_flag_1, 0x608);
646 check_member(mtk_spm_regs, spm_sw_rsv_7, 0x62c);
647 check_member(mtk_spm_regs, spm_sw_rsv_8, 0x630);
648 check_member(mtk_spm_regs, spm_ack_chk_con_3, 0x960);
649 check_member(mtk_spm_regs, spm_ack_chk_timer_3, 0x96c);
650 check_member(mtk_spm_regs, sys_timer_con, 0x98c);
651 check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xa00);
652 check_member(mtk_spm_regs, md32pcm_dma0_src, 0xc00);
653 check_member(mtk_spm_regs, md32pcm_dma0_dst, 0xc04);
654 check_member(mtk_spm_regs, md32pcm_dma0_wppt, 0xc08);
655 check_member(mtk_spm_regs, md32pcm_dma0_wpto, 0xc0c);
656 check_member(mtk_spm_regs, md32pcm_dma0_count, 0xc10);
657 check_member(mtk_spm_regs, md32pcm_dma0_con, 0xc14);
658 check_member(mtk_spm_regs, md32pcm_dma0_start, 0xc18);
659 check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xc24);
660 
661 static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
662 
663 struct pcm_desc {
664  u32 pmem_words;
665  u32 total_words;
666  u32 pmem_start;
667  u32 dmem_start;
668 };
669 
670 struct dyna_load_pcm {
671  u8 *buf; /* binary array */
672  struct pcm_desc desc;
673 };
674 
675 int spm_init(void);
676 
677 static const struct power_domain_data disp[] = {
678  {
679  .pwr_con = &mtk_spm->dis_pwr_con,
680  .pwr_sta_mask = DISP_PWR_STA_MASK,
681  .sram_pdn_mask = DISP_SRAM_PDN_MASK,
682  .sram_ack_mask = DISP_SRAM_ACK_MASK,
683  },
684 };
685 
686 static const struct power_domain_data audio[] = {
687  {
688  .pwr_con = &mtk_spm->audio_pwr_con,
689  .pwr_sta_mask = AUDIO_PWR_STA_MASK,
690  .sram_pdn_mask = AUDIO_SRAM_PDN_MASK,
691  .sram_ack_mask = AUDIO_SRAM_ACK_MASK,
692  },
693 };
694 
695 #endif /* SOC_MEDIATEK_MT8192_SPM_H */
check_member
check_member(mtk_spm_regs, sleep_ca15_wfi_en[3], 0xf1c)
DISP_SRAM_ACK_MASK
@ DISP_SRAM_ACK_MASK
Definition: spm.h:17
DISP_PWR_STA_MASK
@ DISP_PWR_STA_MASK
Definition: spm.h:15
DISP_SRAM_PDN_MASK
@ DISP_SRAM_PDN_MASK
Definition: spm.h:16
AUDIO_SRAM_ACK_MASK
@ AUDIO_SRAM_ACK_MASK
Definition: spm.h:20
AUDIO_PWR_STA_MASK
@ AUDIO_PWR_STA_MASK
Definition: spm.h:18
AUDIO_SRAM_PDN_MASK
@ AUDIO_SRAM_PDN_MASK
Definition: spm.h:19
spm_init
int spm_init(void)
Definition: spm.c:298
disp
static const struct power_domain_data disp[]
Definition: spm.h:677
mtk_spm
static struct mtk_spm_regs *const mtk_spm
Definition: spm.h:661
audio
static const struct power_domain_data audio[]
Definition: spm.h:686
SPM_BASE
@ SPM_BASE
Definition: addressmap.h:19
u32
uint32_t u32
Definition: stdint.h:51
u8
uint8_t u8
Definition: stdint.h:45
dyna_load_pcm
Definition: spm.h:577
dyna_load_pcm::buf
u32 * buf
Definition: spm.h:578
dyna_load_pcm::desc
struct pcm_desc desc
Definition: spm.h:579
mtk_spm_regs
Definition: spm.h:23
mtk_spm_regs::sw2spm_int_clr
u32 sw2spm_int_clr
Definition: spm.h:402
mtk_spm_regs::sw2spm_mailbox_0
u32 sw2spm_mailbox_0
Definition: spm.h:403
mtk_spm_regs::pwr_status
u32 pwr_status
Definition: spm.h:105
mtk_spm_regs::dramc_dpy_clk_spm_con
u32 dramc_dpy_clk_spm_con
Definition: spm.h:576
mtk_spm_regs::armpll_clk_sel
u32 armpll_clk_sel
Definition: spm.h:448
mtk_spm_regs::reserved10
u32 reserved10[15]
Definition: spm.h:264
mtk_spm_regs::scp_clk_con
u32 scp_clk_con
Definition: spm.h:169
mtk_spm_regs::spm2emi_enter_ulpm
u32 spm2emi_enter_ulpm
Definition: spm.h:349
mtk_spm_regs::pwr_status_mask_req_1
u32 pwr_status_mask_req_1
Definition: spm.h:594
mtk_spm_regs::spm_cpu2_pwr_con
u32 spm_cpu2_pwr_con
Definition: spm.h:435
mtk_spm_regs::rg_module_sw_cg_0_mask_req_2
u32 rg_module_sw_cg_0_mask_req_2
Definition: spm.h:583
mtk_spm_regs::reserved13
u32 reserved13[17]
Definition: spm.h:69
mtk_spm_regs::spm_twam_curr_sta3
u32 spm_twam_curr_sta3
Definition: spm.h:224
mtk_spm_regs::spm_clk_settle
u32 spm_clk_settle
Definition: spm.h:136
mtk_spm_regs::spm_cpu_wakeup_event
u32 spm_cpu_wakeup_event
Definition: spm.h:161
mtk_spm_regs::reserved15
u32 reserved15
Definition: spm.h:80
mtk_spm_regs::spm_ddren_event_count_sta
u32 spm_ddren_event_count_sta
Definition: spm.h:408
mtk_spm_regs::mm_dvfs_halt
u32 mm_dvfs_halt
Definition: spm.h:391
mtk_spm_regs::spm_twam_last_sta3
u32 spm_twam_last_sta3
Definition: spm.h:220
mtk_spm_regs::spm_twam_timer_out
u32 spm_twam_timer_out
Definition: spm.h:225
mtk_spm_regs::md32pcm_dma0_count
u32 md32pcm_dma0_count
Definition: spm.h:621
mtk_spm_regs::dummy_sram_con
u32 dummy_sram_con
Definition: spm.h:292
mtk_spm_regs::sw2spm_int
u32 sw2spm_int
Definition: spm.h:400
mtk_spm_regs::cpu_pwr_status
u32 cpu_pwr_status
Definition: spm.h:211
mtk_spm_regs::spm_vs1_vs2_rc_con
u32 spm_vs1_vs2_rc_con
Definition: spm.h:580
mtk_spm_regs::ap_mdsrc_req
u32 ap_mdsrc_req
Definition: spm.h:314
mtk_spm_regs::bus_protect3_rdy
u32 bus_protect3_rdy
Definition: spm.h:228
mtk_spm_regs::dramc_dpy_clk_sw_sel_1
u32 dramc_dpy_clk_sw_sel_1
Definition: spm.h:573
mtk_spm_regs::ddr_en_dbc_con0
u32 ddr_en_dbc_con0
Definition: spm.h:368
mtk_spm_regs::spm_power_on_val2
u32 spm_power_on_val2
Definition: spm.h:329
mtk_spm_regs::spm_wakeup_ext_sta
u32 spm_wakeup_ext_sta
Definition: spm.h:201
mtk_spm_regs::spm_dram_mcu_sw_con3
u32 spm_dram_mcu_sw_con3
Definition: spm.h:560
mtk_spm_regs::reserved7
u32 reserved7[5]
Definition: spm.h:243
mtk_spm_regs::dpy_shu2_con
u32 dpy_shu2_con
Definition: spm.h:529
mtk_spm_regs::pcm_con1
u32 pcm_con1
Definition: spm.h:71
mtk_spm_regs::spm2sw_mailbox_3
u32 spm2sw_mailbox_3
Definition: spm.h:399
mtk_spm_regs::pcm_sta
u32 pcm_sta
Definition: spm.h:398
mtk_spm_regs::mp1_cpu1_irq_mask
u32 mp1_cpu1_irq_mask
Definition: spm.h:371
mtk_spm_regs::conn_pwr_con
u32 conn_pwr_con
Definition: spm.h:276
mtk_spm_regs::spm_bus_protect_mask_b
u32 spm_bus_protect_mask_b
Definition: spm.h:537
mtk_spm_regs::reserved12
u32 reserved12
Definition: spm.h:65
mtk_spm_regs::pcm_pwr_io_en
u32 pcm_pwr_io_en
Definition: spm.h:82
mtk_spm_regs::dramc_mcu2_sram_con
u32 dramc_mcu2_sram_con
Definition: spm.h:530
mtk_spm_regs::dpy_pwr_con
u32 dpy_pwr_con
Definition: spm.h:45
mtk_spm_regs::spm_resource_ack_con2
u32 spm_resource_ack_con2
Definition: spm.h:372
mtk_spm_regs::rg_module_sw_cg_1_mask_req_0
u32 rg_module_sw_cg_1_mask_req_0
Definition: spm.h:584
mtk_spm_regs::md32pcm_wakeup_sta
u32 md32pcm_wakeup_sta
Definition: spm.h:386
mtk_spm_regs::mfg6_pwr_con
u32 mfg6_pwr_con
Definition: spm.h:492
mtk_spm_regs::spm_dram_mcu_sw_con2
u32 spm_dram_mcu_sw_con2
Definition: spm.h:559
mtk_spm_regs::mp0_cpu2_irq_mask
u32 mp0_cpu2_irq_mask
Definition: spm.h:368
mtk_spm_regs::mp1_cpu2_irq_mask
u32 mp1_cpu2_irq_mask
Definition: spm.h:372
mtk_spm_regs::reserved16
u32 reserved16[7]
Definition: spm.h:85
mtk_spm_regs::spm_resource_ack_con1
u32 spm_resource_ack_con1
Definition: spm.h:371
mtk_spm_regs::mfg5_pwr_con
u32 mfg5_pwr_con
Definition: spm.h:491
mtk_spm_regs::cpu_spare_con
u32 cpu_spare_con
Definition: spm.h:392
mtk_spm_regs::spm_scp_irq
u32 spm_scp_irq
Definition: spm.h:160
mtk_spm_regs::mfg2_pwr_con
u32 mfg2_pwr_con
Definition: spm.h:488
mtk_spm_regs::spm2mcupm_con
u32 spm2mcupm_con
Definition: spm.h:547
mtk_spm_regs::bus_protect4_rdy
u32 bus_protect4_rdy
Definition: spm.h:413
mtk_spm_regs::bus_protect8_rdy
u32 bus_protect8_rdy
Definition: spm.h:417
mtk_spm_regs::spm2sw_mailbox_1
u32 spm2sw_mailbox_1
Definition: spm.h:397
mtk_spm_regs::md32pcm_cfgreg_sw_rstn
u32 md32pcm_cfgreg_sw_rstn
Definition: spm.h:615
mtk_spm_regs::mp0_cpu1_wfi_en
u32 mp0_cpu1_wfi_en
Definition: spm.h:376
mtk_spm_regs::vde_pwr_con
u32 vde_pwr_con
Definition: spm.h:35
mtk_spm_regs::spm_bus_protect5_mask_b
u32 spm_bus_protect5_mask_b
Definition: spm.h:546
mtk_spm_regs::spm_cpu3_pwr_con
u32 spm_cpu3_pwr_con
Definition: spm.h:436
mtk_spm_regs::dramc_dpy_clk_sw_con_1
u32 dramc_dpy_clk_sw_con_1
Definition: spm.h:569
mtk_spm_regs::scp_spm_mailbox
u32 scp_spm_mailbox
Definition: spm.h:156
mtk_spm_regs::vs2_psr_mask_b
u32 vs2_psr_mask_b
Definition: spm.h:341
mtk_spm_regs::ven_pwr_con
u32 ven_pwr_con
Definition: spm.h:41
mtk_spm_regs::mp0_cpu7_wfi_en
u32 mp0_cpu7_wfi_en
Definition: spm.h:468
mtk_spm_regs::mp0_cpu2_wfi_en
u32 mp0_cpu2_wfi_en
Definition: spm.h:377
mtk_spm_regs::mp1_cpu3_irq_mask
u32 mp1_cpu3_irq_mask
Definition: spm.h:373
mtk_spm_regs::spm_power_on_val1
u32 spm_power_on_val1
Definition: spm.h:134
mtk_spm_regs::reserved6
u32 reserved6[4]
Definition: spm.h:48
mtk_spm_regs::ven_core1_pwr_con
u32 ven_core1_pwr_con
Definition: spm.h:502
mtk_spm_regs::spm_bus_protect8_mask_b
u32 spm_bus_protect8_mask_b
Definition: spm.h:554
mtk_spm_regs::pwr_status_mask_req_2
u32 pwr_status_mask_req_2
Definition: spm.h:595
mtk_spm_regs::spm_bus_protect2_mask_b
u32 spm_bus_protect2_mask_b
Definition: spm.h:539
mtk_spm_regs::md32pcm_dma0_wppt
u32 md32pcm_dma0_wppt
Definition: spm.h:619
mtk_spm_regs::other_pwr_status
u32 other_pwr_status
Definition: spm.h:403
mtk_spm_regs::mp1_cpu0_irq_mask
u32 mp1_cpu0_irq_mask
Definition: spm.h:370
mtk_spm_regs::spm_bus_protect3_mask_b
u32 spm_bus_protect3_mask_b
Definition: spm.h:540
mtk_spm_regs::spm_irq_mask
u32 spm_irq_mask
Definition: spm.h:162
mtk_spm_regs::spm_pll_con
u32 spm_pll_con
Definition: spm.h:321
mtk_spm_regs::spm2sw_mailbox_0
u32 spm2sw_mailbox_0
Definition: spm.h:396
mtk_spm_regs::rg_module_sw_cg_3_mask_req_1
u32 rg_module_sw_cg_3_mask_req_1
Definition: spm.h:591
mtk_spm_regs::dpy_shu_sram_con
u32 dpy_shu_sram_con
Definition: spm.h:515
mtk_spm_regs::spm_bus_protect6_mask_b
u32 spm_bus_protect6_mask_b
Definition: spm.h:552
mtk_spm_regs::mcupm_pwr_con
u32 mcupm_pwr_con
Definition: spm.h:532
mtk_spm_regs::spm_swint
u32 spm_swint
Definition: spm.h:152
mtk_spm_regs::dpmaif_sram_con
u32 dpmaif_sram_con
Definition: spm.h:528
mtk_spm_regs::dis_pwr_con
u32 dis_pwr_con
Definition: spm.h:44
mtk_spm_regs::spm_dram_mcu_sw_con0
u32 spm_dram_mcu_sw_con0
Definition: spm.h:557
mtk_spm_regs::spm_vtcxo_event_count_sta
u32 spm_vtcxo_event_count_sta
Definition: spm.h:404
mtk_spm_regs::spm_cg_check_con
u32 spm_cg_check_con
Definition: spm.h:596
mtk_spm_regs::pwr_status_2nd
u32 pwr_status_2nd
Definition: spm.h:106
mtk_spm_regs::md1_pwr_con
u32 md1_pwr_con
Definition: spm.h:273
mtk_spm_regs::pcm_wdt_val
u32 pcm_wdt_val
Definition: spm.h:145
mtk_spm_regs::spm_dram_mcu_sta_2
u32 spm_dram_mcu_sta_2
Definition: spm.h:564
mtk_spm_regs::spm_swint_clr
u32 spm_swint_clr
Definition: spm.h:154
mtk_spm_regs::sysram_con
u32 sysram_con
Definition: spm.h:285
mtk_spm_regs::src_req_sta4
u32 src_req_sta4
Definition: spm.h:385
mtk_spm_regs::md32pcm_event_sta
u32 md32pcm_event_sta
Definition: spm.h:387
mtk_spm_regs::spm_mcusys_pwr_con
u32 spm_mcusys_pwr_con
Definition: spm.h:431
mtk_spm_regs::mfg1_pwr_con
u32 mfg1_pwr_con
Definition: spm.h:487
mtk_spm_regs::spm_dvs_dfs_level
u32 spm_dvs_dfs_level
Definition: spm.h:598
mtk_spm_regs::spm_src_req
u32 spm_src_req
Definition: spm.h:163
mtk_spm_regs::spm_vrf18_event_count_sta
u32 spm_vrf18_event_count_sta
Definition: spm.h:406
mtk_spm_regs::spm_power_on_val3
u32 spm_power_on_val3
Definition: spm.h:330
mtk_spm_regs::dramc_mcu_sram_con
u32 dramc_mcu_sram_con
Definition: spm.h:531
mtk_spm_regs::spm_src_rdy_sta
u32 spm_src_rdy_sta
Definition: spm.h:214
mtk_spm_regs::isp_pwr_con
u32 isp_pwr_con
Definition: spm.h:43
mtk_spm_regs::dramc_dpy_clk_sw_sel_2
u32 dramc_dpy_clk_sw_sel_2
Definition: spm.h:574
mtk_spm_regs::cpu_spare_con_clr
u32 cpu_spare_con_clr
Definition: spm.h:394
mtk_spm_regs::bus_protect_rdy
u32 bus_protect_rdy
Definition: spm.h:203
mtk_spm_regs::md32pcm_sta
u32 md32pcm_sta
Definition: spm.h:409
mtk_spm_regs::relay_dvfs_level
u32 relay_dvfs_level
Definition: spm.h:566
mtk_spm_regs::spm_src4_mask
u32 spm_src4_mask
Definition: spm.h:360
mtk_spm_regs::cam_rawc_pwr_con
u32 cam_rawc_pwr_con
Definition: spm.h:510
mtk_spm_regs::spm_bus_protect7_mask_b
u32 spm_bus_protect7_mask_b
Definition: spm.h:553
mtk_spm_regs::src_req_sta3
u32 src_req_sta3
Definition: spm.h:399
mtk_spm_regs::scp_sram_con
u32 scp_sram_con
Definition: spm.h:288
mtk_spm_regs::bus_protect1_rdy
u32 bus_protect1_rdy
Definition: spm.h:394
mtk_spm_regs::spm_mem_ck_sel
u32 spm_mem_ck_sel
Definition: spm.h:536
mtk_spm_regs::spm_sw_rst_con_clr
u32 spm_sw_rst_con_clr
Definition: spm.h:339
mtk_spm_regs::spm_twam_window_len
u32 spm_twam_window_len
Definition: spm.h:158
mtk_spm_regs::spm_cpu7_pwr_con
u32 spm_cpu7_pwr_con
Definition: spm.h:440
mtk_spm_regs::reserved14
u32 reserved14[7]
Definition: spm.h:75
mtk_spm_regs::md32pcm_dma0_rlct
u32 md32pcm_dma0_rlct
Definition: spm.h:625
mtk_spm_regs::md32pcm_dma0_wpto
u32 md32pcm_dma0_wpto
Definition: spm.h:620
mtk_spm_regs::audio_pwr_con
u32 audio_pwr_con
Definition: spm.h:60
mtk_spm_regs::spm_twam_curr_sta1
u32 spm_twam_curr_sta1
Definition: spm.h:222
mtk_spm_regs::spm_sram_rsv_con
u32 spm_sram_rsv_con
Definition: spm.h:151
mtk_spm_regs::reserved4
u32 reserved4
Definition: spm.h:34
mtk_spm_regs::pcm_reg_data_ini
u32 pcm_reg_data_ini
Definition: spm.h:74
mtk_spm_regs::reserved3
u32 reserved3[63]
Definition: spm.h:30
mtk_spm_regs::spm_dram_mcu_sta_1
u32 spm_dram_mcu_sta_1
Definition: spm.h:563
mtk_spm_regs::mp0_cpu0_irq_mask
u32 mp0_cpu0_irq_mask
Definition: spm.h:366
mtk_spm_regs::sw2spm_cfg
u32 sw2spm_cfg
Definition: spm.h:407
mtk_spm_regs::src_req_sta1
u32 src_req_sta1
Definition: spm.h:380
mtk_spm_regs::spm_cpu5_pwr_con
u32 spm_cpu5_pwr_con
Definition: spm.h:438
mtk_spm_regs::devapc_acp_sram_con
u32 devapc_acp_sram_con
Definition: spm.h:519
mtk_spm_regs::spm_wakeup_event_ext_mask
u32 spm_wakeup_event_ext_mask
Definition: spm.h:167
mtk_spm_regs::rg_module_sw_cg_3_mask_req_2
u32 rg_module_sw_cg_3_mask_req_2
Definition: spm.h:592
mtk_spm_regs::spm_cpu6_pwr_con
u32 spm_cpu6_pwr_con
Definition: spm.h:439
mtk_spm_regs::reserved2
u32 reserved2[58]
Definition: spm.h:28
mtk_spm_regs::ext_int_wakeup_req
u32 ext_int_wakeup_req
Definition: spm.h:449
mtk_spm_regs::spm_src3_mask
u32 spm_src3_mask
Definition: spm.h:173
mtk_spm_regs::spm_irq_sta
u32 spm_irq_sta
Definition: spm.h:199
mtk_spm_regs::mdp_pwr_con
u32 mdp_pwr_con
Definition: spm.h:503
mtk_spm_regs::dpy2_pwr_con
u32 dpy2_pwr_con
Definition: spm.h:54
mtk_spm_regs::spm_dram_mcu_sw_con4
u32 spm_dram_mcu_sw_con4
Definition: spm.h:561
mtk_spm_regs::pcm_wdt_out
u32 pcm_wdt_out
Definition: spm.h:198
mtk_spm_regs::mp0_cpu5_wfi_en
u32 mp0_cpu5_wfi_en
Definition: spm.h:466
mtk_spm_regs::ufs_sram_con
u32 ufs_sram_con
Definition: spm.h:290
mtk_spm_regs::spm2md_dvfs_con
u32 spm2md_dvfs_con
Definition: spm.h:316
mtk_spm_regs::sw2spm_mailbox_2
u32 sw2spm_mailbox_2
Definition: spm.h:405
mtk_spm_regs::msdc_pwr_con
u32 msdc_pwr_con
Definition: spm.h:525
mtk_spm_regs::rg_module_sw_cg_0_mask_req_0
u32 rg_module_sw_cg_0_mask_req_0
Definition: spm.h:581
mtk_spm_regs::spm_infra_event_count_sta
u32 spm_infra_event_count_sta
Definition: spm.h:405
mtk_spm_regs::spm_sw_rsv_7
u32 spm_sw_rsv_7
Definition: spm.h:428
mtk_spm_regs::dvfsrc_event_sta
u32 dvfsrc_event_sta
Definition: spm.h:412
mtk_spm_regs::cam_rawa_pwr_con
u32 cam_rawa_pwr_con
Definition: spm.h:508
mtk_spm_regs::spm_src6_mask
u32 spm_src6_mask
Definition: spm.h:335
mtk_spm_regs::spm_twam_con
u32 spm_twam_con
Definition: spm.h:157
mtk_spm_regs::spm_wakeup_misc
u32 spm_wakeup_misc
Definition: spm.h:202
mtk_spm_regs::spm_sw_debug_0
u32 spm_sw_debug_0
Definition: spm.h:602
mtk_spm_regs::rg_module_sw_cg_1_mask_req_1
u32 rg_module_sw_cg_1_mask_req_1
Definition: spm.h:585
mtk_spm_regs::dramc_dpy_clk_sw_con_0
u32 dramc_dpy_clk_sw_con_0
Definition: spm.h:568
mtk_spm_regs::mfg4_pwr_con
u32 mfg4_pwr_con
Definition: spm.h:490
mtk_spm_regs::rg_module_sw_cg_2_mask_req_0
u32 rg_module_sw_cg_2_mask_req_0
Definition: spm.h:587
mtk_spm_regs::sys_timer_con
u32 sys_timer_con
Definition: spm.h:613
mtk_spm_regs::spm_twam_last_sta2
u32 spm_twam_last_sta2
Definition: spm.h:219
mtk_spm_regs::src_req_sta0
u32 src_req_sta0
Definition: spm.h:379
mtk_spm_regs::spm_cpu4_pwr_con
u32 spm_cpu4_pwr_con
Definition: spm.h:437
mtk_spm_regs::md32_clk_con
u32 md32_clk_con
Definition: spm.h:175
mtk_spm_regs::usb_sram_con
u32 usb_sram_con
Definition: spm.h:520
mtk_spm_regs::spm_sw_rsv_8
u32 spm_sw_rsv_8
Definition: spm.h:429
mtk_spm_regs::reserved11
u32 reserved11[2]
Definition: spm.h:56
mtk_spm_regs::spm_clk_con
u32 spm_clk_con
Definition: spm.h:135
mtk_spm_regs::spm_twam_last_sta1
u32 spm_twam_last_sta1
Definition: spm.h:218
mtk_spm_regs::spm_power_on_val0
u32 spm_power_on_val0
Definition: spm.h:133
mtk_spm_regs::mcusys_idle_sta
u32 mcusys_idle_sta
Definition: spm.h:443
mtk_spm_regs::md32pcm_dma0_dst
u32 md32pcm_dma0_dst
Definition: spm.h:618
mtk_spm_regs::mp0_cpu1_irq_mask
u32 mp0_cpu1_irq_mask
Definition: spm.h:367
mtk_spm_regs::spm_dvfs_sta
u32 spm_dvfs_sta
Definition: spm.h:227
mtk_spm_regs::spm_ack_chk_timer_3
u32 spm_ack_chk_timer_3
Definition: spm.h:611
mtk_spm_regs::sspm_sram_con
u32 sspm_sram_con
Definition: spm.h:287
mtk_spm_regs::spm_cirq_con
u32 spm_cirq_con
Definition: spm.h:578
mtk_spm_regs::cam_pwr_con
u32 cam_pwr_con
Definition: spm.h:282
mtk_spm_regs::isp2_pwr_con
u32 isp2_pwr_con
Definition: spm.h:497
mtk_spm_regs::spm_twam_event_clear
u32 spm_twam_event_clear
Definition: spm.h:168
mtk_spm_regs::spm_bus_protect1_mask_b
u32 spm_bus_protect1_mask_b
Definition: spm.h:538
mtk_spm_regs::mp0_cpu3_wfi_en
u32 mp0_cpu3_wfi_en
Definition: spm.h:378
mtk_spm_regs::md_ext_buck_iso_con
u32 md_ext_buck_iso_con
Definition: spm.h:294
mtk_spm_regs::cpu_spare_con_set
u32 cpu_spare_con_set
Definition: spm.h:393
mtk_spm_regs::ext_buck_iso
u32 ext_buck_iso
Definition: spm.h:523
mtk_spm_regs::ahb_bus_con
u32 ahb_bus_con
Definition: spm.h:172
mtk_spm_regs::adsp_pwr_con
u32 adsp_pwr_con
Definition: spm.h:506
mtk_spm_regs::cpu_dvfs_req
u32 cpu_dvfs_req
Definition: spm.h:320
mtk_spm_regs::reserved9
u32 reserved9[7]
Definition: spm.h:258
mtk_spm_regs::pcm_timer_val
u32 pcm_timer_val
Definition: spm.h:83
mtk_spm_regs::mfg3_pwr_con
u32 mfg3_pwr_con
Definition: spm.h:489
mtk_spm_regs::mp0_cpu0_wfi_en
u32 mp0_cpu0_wfi_en
Definition: spm.h:375
mtk_spm_regs::spm_resource_ack_con0
u32 spm_resource_ack_con0
Definition: spm.h:370
mtk_spm_regs::pwr_status_mask_req_0
u32 pwr_status_mask_req_0
Definition: spm.h:593
mtk_spm_regs::debugtop_sram_con
u32 debugtop_sram_con
Definition: spm.h:526
mtk_spm_regs::devapc_ifr_sram_con
u32 devapc_ifr_sram_con
Definition: spm.h:517
mtk_spm_regs::subsys_idle_sta
u32 subsys_idle_sta
Definition: spm.h:205
mtk_spm_regs::dramc_dpy_clk_sw_sel_0
u32 dramc_dpy_clk_sw_sel_0
Definition: spm.h:572
mtk_spm_regs::armpll_clk_con
u32 armpll_clk_con
Definition: spm.h:262
mtk_spm_regs::dramc_dpy_clk_sw_con_3
u32 dramc_dpy_clk_sw_con_3
Definition: spm.h:571
mtk_spm_regs::spm_twam_idle_sel
u32 spm_twam_idle_sel
Definition: spm.h:159
mtk_spm_regs::rg_module_sw_cg_1_mask_req_2
u32 rg_module_sw_cg_1_mask_req_2
Definition: spm.h:586
mtk_spm_regs::md32pcm_dma0_con
u32 md32pcm_dma0_con
Definition: spm.h:622
mtk_spm_regs::spm_apsrc_event_count_sta
u32 spm_apsrc_event_count_sta
Definition: spm.h:407
mtk_spm_regs::spm_sw_flag_1
u32 spm_sw_flag_1
Definition: spm.h:603
mtk_spm_regs::sysrom_con
u32 sysrom_con
Definition: spm.h:286
mtk_spm_regs::md32pcm_pc
u32 md32pcm_pc
Definition: spm.h:410
mtk_spm_regs::bus_protect5_rdy
u32 bus_protect5_rdy
Definition: spm.h:414
mtk_spm_regs::bus_protect2_rdy
u32 bus_protect2_rdy
Definition: spm.h:204
mtk_spm_regs::pcm_reg7_data
u32 pcm_reg7_data
Definition: spm.h:184
mtk_spm_regs::spm_sw_flag_0
u32 spm_sw_flag_0
Definition: spm.h:601
mtk_spm_regs::vs1_psr_mask_b
u32 vs1_psr_mask_b
Definition: spm.h:340
mtk_spm_regs::reserved5
u32 reserved5[3]
Definition: spm.h:40
mtk_spm_regs::ap2md_peer_wakeup
u32 ap2md_peer_wakeup
Definition: spm.h:323
mtk_spm_regs::md32pcm_dma0_src
u32 md32pcm_dma0_src
Definition: spm.h:617
mtk_spm_regs::mfg0_pwr_con
u32 mfg0_pwr_con
Definition: spm.h:486
mtk_spm_regs::spm_src_mask
u32 spm_src_mask
Definition: spm.h:164
mtk_spm_regs::gic_wakeup_sta
u32 gic_wakeup_sta
Definition: spm.h:444
mtk_spm_regs::pcm_timer_out
u32 pcm_timer_out
Definition: spm.h:84
mtk_spm_regs::spm_wakeup_event_mask
u32 spm_wakeup_event_mask
Definition: spm.h:166
mtk_spm_regs::root_core_addr
u32 root_core_addr
Definition: spm.h:390
mtk_spm_regs::spm_dram_mcu_sw_sel_0
u32 spm_dram_mcu_sw_sel_0
Definition: spm.h:565
mtk_spm_regs::spm_dram_mcu_sw_con1
u32 spm_dram_mcu_sw_con1
Definition: spm.h:558
mtk_spm_regs::spm_cg_check_sta
u32 spm_cg_check_sta
Definition: spm.h:428
mtk_spm_regs::pcm_reg6_data
u32 pcm_reg6_data
Definition: spm.h:183
mtk_spm_regs::ipe_pwr_con
u32 ipe_pwr_con
Definition: spm.h:498
mtk_spm_regs::spm_twam_last_sta0
u32 spm_twam_last_sta0
Definition: spm.h:217
mtk_spm_regs::ifr_sub_pwr_con
u32 ifr_sub_pwr_con
Definition: spm.h:494
mtk_spm_regs::root_cputop_addr
u32 root_cputop_addr
Definition: spm.h:389
mtk_spm_regs::reserved1
u32 reserved1[3]
Definition: spm.h:25
mtk_spm_regs::rg_module_sw_cg_3_mask_req_0
u32 rg_module_sw_cg_3_mask_req_0
Definition: spm.h:590
mtk_spm_regs::dramc_dpy_clk_sw_sel_3
u32 dramc_dpy_clk_sw_sel_3
Definition: spm.h:575
mtk_spm_regs::peri_pwr_con
u32 peri_pwr_con
Definition: spm.h:534
mtk_spm_regs::pcm_debug_con
u32 pcm_debug_con
Definition: spm.h:141
mtk_spm_regs::spm_wakeup_sta
u32 spm_wakeup_sta
Definition: spm.h:200
mtk_spm_regs::spm2mm_con
u32 spm2mm_con
Definition: spm.h:325
mtk_spm_regs::pcm_reg2_data
u32 pcm_reg2_data
Definition: spm.h:179
mtk_spm_regs::rg_module_sw_cg_0_mask_req_1
u32 rg_module_sw_cg_0_mask_req_1
Definition: spm.h:582
mtk_spm_regs::poweron_config_set
u32 poweron_config_set
Definition: spm.h:24
mtk_spm_regs::spm_dvfs_misc
u32 spm_dvfs_misc
Definition: spm.h:446
mtk_spm_regs::pcm_reg13_data
u32 pcm_reg13_data
Definition: spm.h:190
mtk_spm_regs::rg_module_sw_cg_2_mask_req_2
u32 rg_module_sw_cg_2_mask_req_2
Definition: spm.h:589
mtk_spm_regs::spm_cpu1_pwr_con
u32 spm_cpu1_pwr_con
Definition: spm.h:434
mtk_spm_regs::reserved0
u32 reserved0
Definition: spm.h:336
mtk_spm_regs::bus_protect6_rdy
u32 bus_protect6_rdy
Definition: spm.h:415
mtk_spm_regs::spm_dvfs_level
u32 spm_dvfs_level
Definition: spm.h:441
mtk_spm_regs::spm2sw_mailbox_2
u32 spm2sw_mailbox_2
Definition: spm.h:398
mtk_spm_regs::dxcc_sram_con
u32 dxcc_sram_con
Definition: spm.h:524
mtk_spm_regs::spm_sw_rst_con
u32 spm_sw_rst_con
Definition: spm.h:337
mtk_spm_regs::spm_ack_chk_sel_3
u32 spm_ack_chk_sel_3
Definition: spm.h:610
mtk_spm_regs::reserved8
u32 reserved8[8]
Definition: spm.h:256
mtk_spm_regs::spm_bus_protect4_mask_b
u32 spm_bus_protect4_mask_b
Definition: spm.h:541
mtk_spm_regs::spm_dram_mcu_sta_0
u32 spm_dram_mcu_sta_0
Definition: spm.h:562
mtk_spm_regs::ifr_pwr_con
u32 ifr_pwr_con
Definition: spm.h:42
mtk_spm_regs::spm_sw_rst_con_set
u32 spm_sw_rst_con_set
Definition: spm.h:338
mtk_spm_regs::src_req_sta2
u32 src_req_sta2
Definition: spm.h:381
mtk_spm_regs::spm_resource_ack_con3
u32 spm_resource_ack_con3
Definition: spm.h:373
mtk_spm_regs::spm_dvfs_opp_sta
u32 spm_dvfs_opp_sta
Definition: spm.h:430
mtk_spm_regs::md2spm_dvfs_con
u32 md2spm_dvfs_con
Definition: spm.h:317
mtk_spm_regs::ext_int_wakeup_req_clr
u32 ext_int_wakeup_req_clr
Definition: spm.h:451
mtk_spm_regs::spm_src2_mask
u32 spm_src2_mask
Definition: spm.h:165
mtk_spm_regs::spm_twam_curr_sta2
u32 spm_twam_curr_sta2
Definition: spm.h:223
mtk_spm_regs::spm_cputop_pwr_con
u32 spm_cputop_pwr_con
Definition: spm.h:432
mtk_spm_regs::spm_twam_curr_sta0
u32 spm_twam_curr_sta0
Definition: spm.h:221
mtk_spm_regs::rg_module_sw_cg_2_mask_req_1
u32 rg_module_sw_cg_2_mask_req_1
Definition: spm.h:588
mtk_spm_regs::dramc_dpy_clk_sw_con_2
u32 dramc_dpy_clk_sw_con_2
Definition: spm.h:570
mtk_spm_regs::spm_swint_set
u32 spm_swint_set
Definition: spm.h:153
mtk_spm_regs::spm_ap_standby_con
u32 spm_ap_standby_con
Definition: spm.h:137
mtk_spm_regs::spm_cpu0_pwr_con
u32 spm_cpu0_pwr_con
Definition: spm.h:433
mtk_spm_regs::ext_int_wakeup_req_set
u32 ext_int_wakeup_req_set
Definition: spm.h:450
mtk_spm_regs::spm_ack_chk_con_3
u32 spm_ack_chk_con_3
Definition: spm.h:608
mtk_spm_regs::spm_src5_mask
u32 spm_src5_mask
Definition: spm.h:361
mtk_spm_regs::spm_ack_chk_pc_3
u32 spm_ack_chk_pc_3
Definition: spm.h:609
mtk_spm_regs::sw2spm_mailbox_3
u32 sw2spm_mailbox_3
Definition: spm.h:406
mtk_spm_regs::md32pcm_dma0_start
u32 md32pcm_dma0_start
Definition: spm.h:623
mtk_spm_regs::vde2_pwr_con
u32 vde2_pwr_con
Definition: spm.h:500
mtk_spm_regs::pcm_con0
u32 pcm_con0
Definition: spm.h:70
mtk_spm_regs::sw2spm_mailbox_1
u32 sw2spm_mailbox_1
Definition: spm.h:404
mtk_spm_regs::mp0_cpu6_wfi_en
u32 mp0_cpu6_wfi_en
Definition: spm.h:467
mtk_spm_regs::spm_scp_mailbox
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Definition: spm.h:168
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Definition: spm.h:175
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Definition: spm.h:217
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u32 reg_mcusys_merge_ddr_en_mask_b
Definition: spm.h:290
pwr_ctrl::reg_msdc2_apsrc_req_mask_b
u8 reg_msdc2_apsrc_req_mask_b
Definition: spm.h:293
pwr_ctrl::reg_msdc0_apsrc_req_mask_b
u8 reg_msdc0_apsrc_req_mask_b
Definition: spm.h:264
pwr_ctrl::reg_msdc2_srcclkena_mask_b
u8 reg_msdc2_srcclkena_mask_b
Definition: spm.h:291
pwr_ctrl::reg_conn_apsrc_sel
u8 reg_conn_apsrc_sel
Definition: spm.h:153
pwr_ctrl::reg_spm_scp_mailbox_req
u8 reg_spm_scp_mailbox_req
Definition: spm.h:172
pwr_ctrl::reg_clksq0_sel_ctrl
u8 reg_clksq0_sel_ctrl
Definition: spm.h:138
pwr_ctrl::reg_gce_vrf18_req_mask_b
u8 reg_gce_vrf18_req_mask_b
Definition: spm.h:230
pwr_ctrl::reg_md_apsrc2infra_req_1_mask_b
u8 reg_md_apsrc2infra_req_1_mask_b
Definition: spm.h:183
pwr_ctrl::reg_conn_ddr_en_mask_b
u8 reg_conn_ddr_en_mask_b
Definition: spm.h:192
pwr_ctrl::reg_conn_vfe28_mask_b
u8 reg_conn_vfe28_mask_b
Definition: spm.h:193