coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_gpio.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <soc/gpio.h>
4 
5 #include "gpio.h"
6 
7 /* Early pad configuration in bootblock */
8 static const struct pad_config early_gpio_table[] = {
9  /* SMB_CLK */
10  PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
11  /* SMB_DATA */
12  PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
13 
14  /* EC_SMI_N */
15  PAD_CFG_GPI(GPP_E7, NONE, DEEP),
16 
17  /* PCH HSID */
18  PAD_CFG_GPI(GPP_A8, NONE, DEEP),
19  PAD_CFG_GPI(GPP_F19, NONE, DEEP),
20  PAD_CFG_GPI(GPP_H19, NONE, DEEP),
21  PAD_CFG_GPI(GPP_H23, NONE, DEEP),
22 
23  /* UART0 RX */
24  PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
25  /* UART0 TX */
26  PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
27  /* UART1 RX */
28  PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
29  /* UART1 TX */
30  PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
31 };
32 
34 {
36 }
#define GPP_H19
#define GPP_D17
#define GPP_H11
#define GPP_E7
#define GPP_D18
#define GPP_A8
#define GPP_C1
#define GPP_H10
#define GPP_C0
#define GPP_F19
#define GPP_H23
#define ARRAY_SIZE(a)
Definition: helpers.h:12
void configure_early_gpio_pads(void)
Definition: early_gpio.c:33
static const struct pad_config early_gpio_table[]
Definition: early_gpio.c:8
void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
program a particular set of GPIO
Definition: gpio.c:307
#define PAD_CFG_GPI(pad, pull, rst)
Definition: gpio_defs.h:284
#define PAD_CFG_NF(pad, pull, rst, func)
Definition: gpio_defs.h:197