#include <arch/io.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/smbus.h>
#include "chip.h"
#include "i82371eb.h"
Go to the source code of this file.
◆ pwrmgt_enable()
Definition at line 14 of file smbus.c.
References BIOS_SPEW, device::chip_info, DEFAULT_PMBASE, DEVCTL, DEVSTS, GLBCTL, GLBEN, GLBSTS, southbridge_intel_i82371eb_config::gpo, GPO0, GPO1, GPO2, GPO3, GPSTS, southbridge_intel_i82371eb_config::lid_polarity, outb(), outl(), outw(), pci_read_config8(), pci_write_config16(), pci_write_config8(), PCNTRL, PMBA, PMCNTRL, PMREGMISC, PMSTS, printk, SCI_EN, SUS_TYP_S0, southbridge_intel_i82371eb_config::thrm_polarity, and val.
◆ pwrmgt_read_resources()
static void pwrmgt_read_resources |
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struct device * |
dev | ) |
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static |
◆ __pci_driver
const struct pci_driver smbus_driver __pci_driver |
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static |
Initial value:= {
}
#define PCI_DID_INTEL_82371AB_SMB_ACPI
static const struct device_operations smbus_ops
Definition at line 74 of file smbus.c.
◆ lops_smbus_bus
Initial value:
Definition at line 74 of file smbus.c.
◆ smbus_ops
Initial value:= {
.ops_pci = 0,
}
void pci_dev_enable_resources(struct device *dev)
void pci_dev_set_resources(struct device *dev)
void scan_smbus(struct device *bus)
static void pwrmgt_enable(struct device *dev)
static void pwrmgt_read_resources(struct device *dev)
static const struct smbus_bus_operations lops_smbus_bus
Definition at line 74 of file smbus.c.