coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ramstage.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _BAYTRAIL_RAMSTAGE_H_
4 #define _BAYTRAIL_RAMSTAGE_H_
5 
6 #include <device/device.h>
8 
9 /* The baytrail_init_pre_device() function is called prior to device
10  * initialization, but it's after console and cbmem has been reinitialized. */
12 void southcluster_enable_dev(struct device *dev);
13 /* The baytrail_run_reference_code() function is provided by either
14  * native refcode or the ChromeBook refcode wrapper */
16 void baytrail_init_scc(void);
17 void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
18 
19 extern struct pci_operations soc_pci_ops;
20 
21 #endif /* _BAYTRAIL_RAMSTAGE_H_ */
enum board_config config
Definition: memory.c:448
struct pci_operations soc_pci_ops
Definition: chip.c:51
void baytrail_init_pre_device(struct soc_intel_baytrail_config *config)
Definition: ramstage.c:170
void southcluster_enable_dev(struct device *dev)
Definition: southcluster.c:452
void baytrail_init_scc(void)
Definition: scc.c:54
void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
Definition: scc.c:71
void baytrail_run_reference_code(void)
Definition: refcode.c:45
Definition: device.h:107