coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
xdci.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/mmio.h>
4 #include <console/console.h>
5 #include <device/device.h>
6 #include <device/pci.h>
7 #include <intelblocks/xdci.h>
8 #include <soc/pci_devs.h>
9 #include <timer.h>
10 
11 #define DUAL_ROLE_CFG0 0x80d8
12 # define DRD_CONFIG_MASK (0x3 << 0)
13 # define DRD_CONFIG_DYNAMIC (0x0 << 0)
14 # define DRD_CONFIG_HOST (0x1 << 0)
15 # define DRD_CONFIG_DEVICE (0x2 << 0)
16 # define SW_VBUS_VALID_MASK (1 << 24)
17 # define SW_VBUS_DEASSERT_VALID (0 << 24)
18 # define SW_VBUS_ASSERT_VALID (1 << 24)
19 # define SW_IDPIN_EN_MASK (1 << 21)
20 # define SW_IDPIN_DIS (0 << 21)
21 # define SW_IDPIN_EN (1 << 21)
22 # define SW_IDPIN_MASK (1 << 20)
23 # define SW_IDPIN_HOST (0 << 20)
24 # define SW_IDPIN_DEVICE (1 << 20)
25 #define DUAL_ROLE_CFG1 0x80dc
26 # define DRD_MODE_MASK (1 << 29)
27 # define DRD_MODE_DEVICE (0 << 29)
28 # define DRD_MODE_HOST (1 << 29)
29 
30 static void configure_host_mode_port0(struct device *dev)
31 {
32  uint32_t *cfg0;
33  uint32_t *cfg1;
34  const struct resource *res;
35  uint32_t reg;
36  struct stopwatch sw;
37 
38  /*
39  * Only default to host mode if the xdci device is present and
40  * enabled. If it's disabled assume the switch was already done
41  * in FSP.
42  */
43  if (!dev->enabled)
44  return;
45 
46  printk(BIOS_INFO, "Putting port 0 into host mode.\n");
47 
49 
50  cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0);
51  cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1);
52 
53  reg = read32(cfg0);
55  reg &= ~(SW_VBUS_VALID_MASK);
58  write32(cfg0, reg);
59 
61 
62  /* Wait for the host mode status bit. */
63  while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) {
64  if (stopwatch_expired(&sw)) {
65  printk(BIOS_INFO, "Timed out waiting for host mode.\n");
66  break;
67  }
68  }
69 
70  printk(BIOS_INFO, "XDCI port 0 host switch over took %lu ms\n",
72 }
73 
74 void soc_xdci_init(struct device *dev)
75 {
77 }
#define SW_VBUS_VALID_MASK
Definition: xdci.c:16
#define DUAL_ROLE_CFG1
Definition: xdci.c:25
#define SW_IDPIN_EN
Definition: xdci.c:21
static void configure_host_mode_port0(struct device *dev)
Definition: xdci.c:30
#define SW_IDPIN_HOST
Definition: xdci.c:23
#define SW_IDPIN_EN_MASK
Definition: xdci.c:19
void soc_xdci_init(struct device *dev)
Definition: xdci.c:74
#define SW_IDPIN_MASK
Definition: xdci.c:22
#define SW_VBUS_DEASSERT_VALID
Definition: xdci.c:17
#define DRD_MODE_HOST
Definition: xdci.c:28
#define DRD_CONFIG_DYNAMIC
Definition: xdci.c:13
#define DUAL_ROLE_CFG0
Definition: xdci.c:11
#define DRD_CONFIG_MASK
Definition: xdci.c:12
#define DRD_MODE_MASK
Definition: xdci.c:26
static void write32(void *addr, uint32_t val)
Definition: mmio.h:40
static uint32_t read32(const void *addr)
Definition: mmio.h:22
#define printk(level,...)
Definition: stdlib.h:16
struct resource * find_resource(const struct device *dev, unsigned int index)
Return an existing resource structure for a given index.
Definition: device_util.c:394
static int stopwatch_expired(struct stopwatch *sw)
Definition: timer.h:152
static long stopwatch_duration_msecs(struct stopwatch *sw)
Definition: timer.h:182
static void stopwatch_init_msecs_expire(struct stopwatch *sw, long ms)
Definition: timer.h:133
#define BIOS_INFO
BIOS_INFO - Expected events.
Definition: loglevel.h:113
#define PCI_BASE_ADDRESS_0
Definition: pci_def.h:63
unsigned int uint32_t
Definition: stdint.h:14
unsigned long uintptr_t
Definition: stdint.h:21
Definition: device.h:107
unsigned int enabled
Definition: device.h:122
resource_t base
Definition: resource.h:45