coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ramstage.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/ramstage.h>
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#include "include/gpio.h"
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void
mainboard_silicon_init_params
(
FSP_SIL_UPD
*
params
)
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{
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/* Configure pads prior to SiliconInit() in case there's any
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* dependencies during hardware initialization. */
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gpio_configure_pads
(
gpio_table
,
ARRAY_SIZE
(
gpio_table
));
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params
->CdClock = 3;
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}
params
static struct sdram_info params
Definition:
sdram_configs.c:83
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
mainboard_silicon_init_params
__weak void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
Definition:
ramstage.c:162
gpio_table
static const struct pad_config gpio_table[]
Definition:
gpio.h:24
gpio_configure_pads
void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
program a particular set of GPIO
Definition:
gpio.c:307
FSP_SIL_UPD
#define FSP_SIL_UPD
Definition:
ramstage.h:12
src
mainboard
asrock
h110m
ramstage.c
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