5 #include <soc/addressmap.h>
377 for (i = 0; i < num; i++, t++)
static void write32(void *addr, uint32_t val)
static uint32_t read32(const void *addr)
#define printk(level,...)
#define wait_us(timeout_us, condition)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
#define USB3_PCS_PHYSTATUS
static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout
static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], int num)
void ss_qmp_phy_init(void)
struct ss_usb_phy_reg qmp_v3_usb_phy
static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[]
static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[]
static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[]
check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010)
static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[]
static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout
static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout
static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout
#define QMP_PHY_QSERDES_RX_REG_BASE
#define QMP_PHY_PCS_REG_BASE
#define QMP_PHY_QSERDES_COM_REG_BASE
#define QMP_PHY_QSERDES_TX_REG_BASE
struct usb3_phy_pcs_reg_layout * qmp_pcs_reg
const struct qmp_phy_init_tbl * rx_tbl
const struct qmp_phy_init_tbl * serdes_tbl
const struct qmp_phy_init_tbl * tx_tbl
const struct qmp_phy_init_tbl * pcs_tbl
u32 pcs_rxeqtraining_wait_time
u32 pcs_lock_detect_config3
u32 pcs_lfps_ecstart_eqtlock
u32 pcs_txdeemph_m3p5db_v3
u32 pcs_autonomous_mode_ctrl
u32 pcs_refgen_req_config2
u32 pcs_lock_detect_config1
u32 pcs_txdeemph_m3p5db_ls
u32 pcs_pwrup_reset_dly_time_auxclk
u32 pcs_rcvr_dtct_dly_u3_l
u32 pcs_rcvr_dtct_dly_p1u2_h
u32 pcs_txdeemph_m3p5db_v0
u32 pcs_refgen_req_config1
u32 pcs_rcvr_dtct_dly_u3_h
u32 pcs_txdeemph_m3p5db_v2
u32 pcs_txdeemph_m3p5db_v4
u32 pcs_txdeemph_m3p5db_v1
u32 pcs_power_down_control
u32 pcs_lock_detect_config2
u32 pcs_fll_cnt_val_h_tol
u32 pcs_rcvr_dtct_dly_p1u2_l
u32 pcs_rxeqtraining_run_time
u32 pcs_power_state_config2
u32 com_integloop_gain1_mode0
u32 com_bias_en_clkbuflr_en
u32 com_sysclk_buf_enable
u32 com_div_frac_start1_mode0
u32 com_coreclk_div_mode0
u32 com_div_frac_start3_mode0
u32 com_integloop_gain0_mode0
u32 com_div_frac_start2_mode0
u32 com_cmn_rate_override
u32 rx_sigdet_deglitch_ctrl
u32 rx_ucdr_so_saturtn_and_en
u32 rx_rx_eq_offset_adap_ctrl1
u32 rx_rx_offset_adap_ctrl2
u32 rx_ucdr_fastlock_fo_gain
u32 tx_res_code_lane_offset_tx
u32 tx_res_code_lane_offset_rx