coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
spi.h File Reference
#include <spi-generic.h>
#include <stddef.h>
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Functions

void spi_enable (const size_t bus)
 Enable the SPI controller. More...
 
void spi_disable (const size_t bus)
 Disable the SPI controller. More...
 
void spi_set_cs (const size_t bus, const size_t chip_select, const size_t assert_is_low)
 Set SPI Chip select line and level if asserted. More...
 
void spi_set_clock (const size_t bus, const size_t speed_hz, const size_t idle_low, const size_t idle_cycles)
 Set SPI clock frequency. More...
 
uint64_t spi_get_clock (const size_t bus)
 Get current SPI clock frequency in Hz. More...
 
void spi_set_lsbmsb (const size_t bus, const size_t lsb_first)
 Set SPI LSB/MSB first. More...
 
void spi_init_custom (const size_t bus, const size_t speed_hz, const size_t idle_low, const size_t idle_cycles, const size_t lsb_first, const size_t chip_select, const size_t assert_is_low)
 Init SPI with custom parameters and enable SPI controller. More...
 

Function Documentation

◆ spi_disable()

void spi_disable ( const size_t  bus)

Disable the SPI controller.

Pins are tristated.

Parameters
busThe SPI bus to operate on

Definition at line 127 of file spi.c.

References ARRAY_SIZE, assert, cavium_spi_slaves, cavium_spi::cfg, cavium_spi_cfg::csena, cavium_spi_cfg::enable, read64(), cavium_spi_slave::regs, cavium_spi_cfg::s, cavium_spi_cfg::u, and write64().

Referenced by spi_init(), and spi_init_custom().

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◆ spi_enable()

void spi_enable ( const size_t  bus)

Enable the SPI controller.

Pins are driven.

Parameters
busThe SPI bus to operate on

Definition at line 106 of file spi.c.

References ARRAY_SIZE, assert, cavium_spi_slaves, cavium_spi::cfg, cavium_spi_cfg::csena, cavium_spi_cfg::enable, read64(), cavium_spi_slave::regs, cavium_spi_cfg::s, cavium_spi_cfg::u, and write64().

Referenced by spi_init(), and spi_init_custom().

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◆ spi_get_clock()

uint64_t spi_get_clock ( const size_t  bus)

Get current SPI clock frequency in Hz.

Parameters
busThe SPI bus to operate on

Definition at line 211 of file spi.c.

References ARRAY_SIZE, assert, cavium_spi_slaves, cavium_spi::cfg, cavium_spi_cfg::clkdiv, read64(), cavium_spi_slave::regs, cavium_spi_cfg::s, thunderx_get_io_clock(), and cavium_spi_cfg::u.

Referenced by mainboard_print_info().

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◆ spi_init_custom()

void spi_init_custom ( const size_t  bus,
const size_t  speed_hz,
const size_t  idle_low,
const size_t  idle_cycles,
const size_t  lsb_first,
const size_t  chip_select,
const size_t  assert_is_low 
)

Init SPI with custom parameters and enable SPI controller.

Parameters
busThe SPI bus to operate on
speed_hzThe SPI frequency in Hz
idle_lowThe SPI clock idles low
idle_cyclesNumber of CLK cycles between two commands (0 - 3)
lsb_firstThe SPI operates LSB first
chip_selectThe chip select pin to use (0 - 3)
assert_is_lowCS pin state is low when asserted

Definition at line 261 of file spi.c.

References spi_disable(), spi_enable(), spi_set_clock(), spi_set_cs(), and spi_set_lsbmsb().

Referenced by configure_spi_flash().

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◆ spi_set_clock()

void spi_set_clock ( const size_t  bus,
const size_t  speed_hz,
const size_t  idle_low,
const size_t  idle_cycles 
)

Set SPI clock frequency.

Parameters
busThe SPI bus to operate on
speed_hzThe SPI frequency in Hz
idle_lowThe SPI clock idles low
idle_cyclesNumber of CLK cycles between two commands (0 - 3)

Definition at line 180 of file spi.c.

References ARRAY_SIZE, assert, BIOS_DEBUG, cavium_spi_slaves, cavium_spi::cfg, cavium_spi_cfg::clk_cont, cavium_spi_cfg::clkdiv, cavium_spi_cfg::csena, cavium_spi_cfg::idleclks, cavium_spi_cfg::idlelow, MIN, printk, read64(), cavium_spi_slave::regs, cavium_spi_cfg::s, thunderx_get_io_clock(), cavium_spi_cfg::u, and write64().

Referenced by spi_init(), and spi_init_custom().

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◆ spi_set_cs()

void spi_set_cs ( const size_t  bus,
const size_t  chip_select,
const size_t  assert_is_low 
)

Set SPI Chip select line and level if asserted.

Parameters
busThe SPI bus to operate on
chip_selectThe chip select pin to use (0 - 3)
assert_is_lowCS pin state is low when asserted

Definition at line 150 of file spi.c.

References ARRAY_SIZE, assert, cavium_spi_slaves, cavium_spi::cfg, cavium_spi_slave::cs, cavium_spi_cfg::csena, cavium_spi_cfg::cshi, read64(), cavium_spi_slave::regs, cavium_spi_cfg::s, cavium_spi_cfg::u, and write64().

Referenced by spi_init(), and spi_init_custom().

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◆ spi_set_lsbmsb()

void spi_set_lsbmsb ( const size_t  bus,
const size_t  lsb_first 
)

Set SPI LSB/MSB first.

Parameters
busThe SPI bus to operate on
lsb_firstThe SPI operates LSB first

Definition at line 234 of file spi.c.

References ARRAY_SIZE, assert, cavium_spi_slaves, cavium_spi::cfg, cavium_spi_cfg::csena, cavium_spi_cfg::lsbfirst, read64(), cavium_spi_slave::regs, cavium_spi_cfg::s, cavium_spi_cfg::u, and write64().

Referenced by spi_init(), and spi_init_custom().

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