coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
bootblock.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <bootblock_common.h>
4 #include <soc/soc.h>
5 #include <soc/spi.h>
6 #include <soc/uart.h>
7 
9 {
10  if (CONFIG(BOOTBLOCK_CONSOLE)) {
11  if (!uart_is_enabled(CONFIG_UART_FOR_CONSOLE))
12  uart_setup(CONFIG_UART_FOR_CONSOLE, CONFIG_TTYS0_BAUD);
13  }
14 }
15 
16 static void configure_spi_flash(void)
17 {
18  /* FIXME: Only tested on EM100 Pro */
19  spi_init_custom(0, // bus
20  25000000, // speed Hz
21  0, // idle low disabled
22  0, // zero idle cycles between transfers
23  0, // MSB first
24  0, // Chip select 0
25  1); // assert is high
26 }
27 
29 {
31 }
@ CONFIG
Definition: dsi_common.h:201
__weak void bootblock_mainboard_init(void)
Definition: bootblock.c:19
__weak void bootblock_mainboard_early_init(void)
Definition: bootblock.c:16
static void configure_spi_flash(void)
Definition: bootblock.c:16
void spi_init_custom(const size_t bus, const size_t speed_hz, const size_t idle_low, const size_t idle_cycles, const size_t lsb_first, const size_t chip_select, const size_t assert_is_low)
Init SPI with custom parameters and enable SPI controller.
Definition: spi.c:261
int uart_setup(const size_t bus, int baudrate)
Setup UART with desired BAUD rate in 8N1, no parity mode.
Definition: uart.c:141
int uart_is_enabled(const size_t bus)
Returns the UART state.
Definition: uart.c:120