coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
devtree.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <chip.h>
4 #include <cpu/intel/turbo.h>
5 #include <device/device.h>
6 #include <device/pci_def.h>
7 #include <option.h>
8 #include <types.h>
9 #include <variants.h>
10 
11 void devtree_update(void)
12 {
13  config_t *cfg = config_of_soc();
14 
15  struct soc_power_limits_config *soc_conf_2core =
16  &cfg->power_limits_config[POWER_LIMITS_U_2_CORE];
17 
18  struct soc_power_limits_config *soc_conf_4core =
19  &cfg->power_limits_config[POWER_LIMITS_U_4_CORE];
20 
21  struct device *nic_dev = pcidev_on_root(0x14, 3);
22  struct device *tbt_pci_dev = pcidev_on_root(0x07, 0);
23  struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2);
24 
25 
26  /* Update PL1 & PL2 based on CMOS settings */
28  case PP_POWER_SAVER:
29  disable_turbo();
30  soc_conf_2core->tdp_pl1_override = 15;
31  soc_conf_4core->tdp_pl1_override = 15;
32  soc_conf_2core->tdp_pl2_override = 15;
33  soc_conf_4core->tdp_pl2_override = 15;
34  break;
35  case PP_BALANCED:
36  soc_conf_2core->tdp_pl1_override = 15;
37  soc_conf_4core->tdp_pl1_override = 15;
38  soc_conf_2core->tdp_pl2_override = 25;
39  soc_conf_4core->tdp_pl2_override = 25;
40  break;
41  case PP_PERFORMANCE:
42  soc_conf_2core->tdp_pl1_override = 28;
43  soc_conf_4core->tdp_pl1_override = 28;
44  soc_conf_2core->tdp_pl2_override = 40;
45  soc_conf_4core->tdp_pl2_override = 40;
46  break;
47  }
48 
49  /* Enable/Disable Wireless based on CMOS settings */
50  if (get_uint_option("wireless", 1) == 0)
51  nic_dev->enabled = 0;
52 
53  /* Enable/Disable Webcam based on CMOS settings */
54  if (get_uint_option("webcam", 1) == 0)
55  cfg->usb2_ports[3].enable = 0;
56 
57  /* Enable/Disable Thunderbolt based on CMOS settings */
58  if (get_uint_option("thunderbolt", 1) == 0) {
59  cfg->UsbTcPortEn = 0;
60  cfg->TcssXhciEn = 0;
61  cfg->TcssD3ColdDisable = 0;
62  tbt_pci_dev->enabled = 0;
63  tbt_dma_dev->enabled = 0;
64  }
65 }
DEVTREE_CONST struct device * pcidev_on_root(uint8_t dev, uint8_t fn)
Definition: device_const.c:260
#define config_of_soc()
Definition: device.h:394
void devtree_update(void)
Definition: devtree.c:11
enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback)
Definition: devtree.c:11
unsigned int get_uint_option(const char *name, const unsigned int fallback)
Definition: option.c:116
@ POWER_LIMITS_U_2_CORE
Definition: chip.h:30
@ POWER_LIMITS_U_4_CORE
Definition: chip.h:31
@ PP_PERFORMANCE
Definition: variants.h:11
@ PP_POWER_SAVER
Definition: variants.h:9
@ PP_BALANCED
Definition: variants.h:10
Definition: device.h:107
unsigned int enabled
Definition: device.h:122
void disable_turbo(void)
Definition: turbo.c:108