coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio_early.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <mainboard/gpio.h>
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#include <soc/gpio.h>
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static
const
struct
pad_config
early_gpio_table
[] = {
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/* Early LPC configuration in romstage */
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PAD_CFG_NF
(
GPP_A1
,
NONE
, DEEP, NF1),
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PAD_CFG_NF
(
GPP_A2
,
NONE
, DEEP, NF1),
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PAD_CFG_NF
(
GPP_A3
,
NONE
, DEEP, NF1),
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PAD_CFG_NF
(
GPP_A4
,
NONE
, DEEP, NF1),
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PAD_CFG_NF
(
GPP_A5
,
NONE
, DEEP, NF1),
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PAD_CFG_NF
(
GPP_A6
,
NONE
, DEEP, NF1),
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PAD_CFG_NF
(
GPP_A8
,
NONE
, DEEP, NF1),
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PAD_CFG_NF
(
GPP_A9
,
NONE
, DEEP, NF1),
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PAD_CFG_NF
(
GPP_A10
,
NONE
, DEEP, NF1),
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};
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void
mainboard_configure_early_gpios
(
void
)
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{
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gpio_configure_pads
(
early_gpio_table
,
ARRAY_SIZE
(
early_gpio_table
));
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}
GPP_A4
#define GPP_A4
Definition:
gpio_soc_defs.h:123
GPP_A5
#define GPP_A5
Definition:
gpio_soc_defs.h:124
GPP_A2
#define GPP_A2
Definition:
gpio_soc_defs.h:121
GPP_A6
#define GPP_A6
Definition:
gpio_soc_defs.h:125
GPP_A3
#define GPP_A3
Definition:
gpio_soc_defs.h:122
GPP_A10
#define GPP_A10
Definition:
gpio_soc_defs.h:129
GPP_A8
#define GPP_A8
Definition:
gpio_soc_defs.h:127
GPP_A1
#define GPP_A1
Definition:
gpio_soc_defs.h:120
GPP_A9
#define GPP_A9
Definition:
gpio_soc_defs.h:128
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
NONE
@ NONE
Definition:
qup_se_handlers_common.h:196
gpio_configure_pads
void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
program a particular set of GPIO
Definition:
gpio.c:307
PAD_CFG_NF
#define PAD_CFG_NF(pad, pull, rst, func)
Definition:
gpio_defs.h:197
pad_config
Definition:
gpio.h:75
mainboard_configure_early_gpios
void mainboard_configure_early_gpios(void)
Definition:
gpio_early.c:19
early_gpio_table
static const struct pad_config early_gpio_table[]
Definition:
gpio_early.c:6
src
mainboard
supermicro
x11-lga1151-series
variants
x11ssh-f
gpio_early.c
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