coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
|
#include <southbridge/intel/i82801gx/i82801gx.h>
#include "hostbridge_regs.h"
#include <northbridge/intel/common/fixed_bars.h>
#include "mchbar_regs.h"
Go to the source code of this file.
Macros | |
#define | DEFAULT_PMIOBAR 0x00000400 |
#define | BOOT_PATH_NORMAL 0 |
#define | BOOT_PATH_RESET 1 |
#define | BOOT_PATH_RESUME 2 |
#define | HOST_BRIDGE PCI_DEV(0, 0, 0) |
#define | PEGSTS 0x214 /* 32 bits */ |
#define | GMCH_IGD PCI_DEV(0, 2, 0) |
#define | GMADR 0x18 |
#define | GTTADR 0x1c |
#define | BSM 0x5c |
Functions | |
void | pineview_early_init (void) |
u32 | decode_igd_memory_size (const u32 gms) |
Decodes used Graphics Mode Select (GMS) to kilobytes. More... | |
u32 | decode_igd_gtt_size (const u32 gsm) |
Decodes used Graphics Stolen Memory (GSM) to kilobytes. More... | |
void | get_mb_spd_addrmap (u8 *spd_addr_map) |
void | mb_pirq_setup (void) |
#define BOOT_PATH_NORMAL 0 |
Definition at line 10 of file pineview.h.
#define BOOT_PATH_RESET 1 |
Definition at line 11 of file pineview.h.
#define BOOT_PATH_RESUME 2 |
Definition at line 12 of file pineview.h.
#define BSM 0x5c |
Definition at line 28 of file pineview.h.
#define DEFAULT_PMIOBAR 0x00000400 |
Definition at line 8 of file pineview.h.
#define GMADR 0x18 |
Definition at line 26 of file pineview.h.
#define GMCH_IGD PCI_DEV(0, 2, 0) |
Definition at line 24 of file pineview.h.
#define GTTADR 0x1c |
Definition at line 27 of file pineview.h.
#define HOST_BRIDGE PCI_DEV(0, 0, 0) |
Definition at line 15 of file pineview.h.
#define PEGSTS 0x214 /* 32 bits */ |
Definition at line 21 of file pineview.h.
Definition at line 16 of file early_init.c.
Definition at line 155 of file early_init.c.
References BIOS_DEBUG, early_misc_setup(), GCS, pineview_setup_bars(), printk, and RCBA32.
Referenced by mainboard_romstage_entry().