coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.h
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _SOC_QUALCOMM_SC7180_GPIO_H_
4 #define _SOC_QUALCOMM_SC7180_GPIO_H_
5 
6 #include <types.h>
7 #include <soc/addressmap.h>
8 #include <soc/gpio_common.h>
9 
10 #define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \
11 GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + (index * TLMM_GPIO_OFF_DELTA), \
12 GPIO##index##_FUNC_##func1 = 1, \
13 GPIO##index##_FUNC_##func2 = 2, \
14 GPIO##index##_FUNC_##func3 = 3, \
15 GPIO##index##_FUNC_##func4 = 4, \
16 GPIO##index##_FUNC_##func5 = 5, \
17 GPIO##index##_FUNC_##func6 = 6, \
18 GPIO##index##_FUNC_##func7 = 7
19 
20 enum {
21  PIN(0, SOUTH, QUP0_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
22  PIN(1, SOUTH, QUP0_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
23  PIN(2, SOUTH, QUP0_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
24  PIN(3, SOUTH, QUP0_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
25  PIN(4, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
26  PIN(5, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
27  PIN(6, NORTH, QUP1_L0, QUP1_L2, RES_3, RES_4, RES_5, RES_6, RES_7),
28  PIN(7, NORTH, QUP1_L1, QUP1_L3, RES_3, RES_4, RES_5, RES_6, RES_7),
29  PIN(8, NORTH, GP_PDM_MIRB, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
30  PIN(9, NORTH, RES1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
31  PIN(10, NORTH, MDP_VSYNC_P_MIRA, RES_2, RES_3, RES_4, RES_5, RES_6,
32  RES_7),
33  PIN(11, NORTH, MDP_VSYNC_S_MIRA, RES_2, RES_3, RES_4, RES_5, RES_6,
34  RES_7),
35  PIN(12, SOUTH, MDP_VSYNC_E, RES_2, QUP0_L4, RES_4, RES_5, RES_6, RES_7),
36  PIN(13, SOUTH, CAM_MCLK0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
37  PIN(14, SOUTH, CAM_MCLK1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
38  PIN(15, SOUTH, CAM_MCLK2, QUP0_L0, QUP0_L2, RES_4, RES_5, RES_6, RES_7),
39  PIN(16, SOUTH, CAM_MCLK3, QUP0_L1, QUP0_L3, RES_4, RES_5, RES_6, RES_7),
40  PIN(17, SOUTH, CCI_I2C_SDA0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
41  PIN(18, SOUTH, CCI_I2C_SCL0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
42  PIN(19, SOUTH, CCI_I2C_SDA1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
43  PIN(20, SOUTH, CCI_I2C_SCL1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
44  PIN(21, NORTH, CCI_TIMER0, GCC_GP2_CLK_MIRB, RES_3, RES_4, RES_5, RES_6,
45  RES_7),
46  PIN(22, NORTH, CCI_TIMER1, GCC_GP3_CLK_MIRB, RES_3, RES_4, RES_5, RES_6,
47  RES_7),
48  PIN(23, SOUTH, CCI_TIMER2, CAM_MCLK4, RES_3, RES_4, RES_5, RES_6,
49  RES_7),
50  PIN(24, SOUTH, CCI_TIMER3, CCI_ASYNC_IN1, RES_3, RES_4, RES_5, RES_6,
51  RES_7),
52  PIN(25, SOUTH, CCI_TIMER4, CCI_ASYNC_IN2, QUP0_L0, RES_4, RES_5, RES_6,
53  RES_7),
54  PIN(26, SOUTH, CCI_ASYNC_IN0, QUP0_L1, RES_3, RES_4, RES_5, RES_6,
55  RES_7),
56  PIN(27, SOUTH, CCI_I2C_SDA2, QUP0_L2, RES_3, RES_4, RES_5, RES_6,
57  RES_7),
58  PIN(28, SOUTH, CCI_I2C_SCL2, QUP0_L3, RES_3, RES_4, RES_5, RES_6,
59  RES_7),
60  PIN(29, NORTH, GP_MN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
61  PIN(30, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
62  PIN(31, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
63  PIN(32, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
64  PIN(33, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
65  PIN(34, SOUTH, QUP0_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
66  PIN(35, SOUTH, QUP0_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
67  PIN(36, SOUTH, QUP0_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
68  PIN(37, SOUTH, QUP0_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
69  PIN(38, SOUTH, QUP0_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
70  PIN(39, SOUTH, QUP0_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
71  PIN(40, SOUTH, QUP0_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
72  PIN(41, SOUTH, QUP0_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
73  PIN(42, NORTH, QUP1_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
74  PIN(43, NORTH, QUP1_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
75  PIN(44, NORTH, QUP1_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
76  PIN(45, NORTH, QUP1_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
77  PIN(46, NORTH, QUP1_L0, QUP1_L2, RES_3, RES_4, RES_5, RES_6, RES_7),
78  PIN(47, NORTH, QUP1_L1, QUP1_L3, RES_3, RES_4, RES_5, RES_6, RES_7),
79  PIN(48, NORTH, GCC_GP1_CLK_MIRA, RES_2, RES_3, RES_4, RES_5, RES_6,
80  RES_7),
81  PIN(49, WEST, MI2S_1_SCK, BTFM_SLIMBUS_CLK, RES_3, RES_4, RES_5, RES_6,
82  RES_7),
83  PIN(50, WEST, MI2S_1_WS, BTFM_SLIMBUS_DATA0, RES_3, RES_4, RES_5, RES_6,
84  RES_7),
85  PIN(51, WEST, MI2S_1_DATA0, BTFM_SLIMBUS_DATA1, RES_3, RES_4, RES_5,
86  RES_6, RES_7),
87  PIN(52, WEST, MI2S_1_DATA1, BTFM_SLIMBUS_DATA2, RES_3, RES_4, RES_5,
88  RES_6, RES_7),
89  PIN(53, WEST, MI2S_0_SCK, QUP1_L0, RES_3, RES_4, RES_5, RES_6, RES_7),
90  PIN(54, WEST, MI2S_0_WS, QUP1_L1, RES_3, RES_4, RES_5, RES_6, RES_7),
91  PIN(55, WEST, MI2S_0_DATA0, QUP1_L2, RES_3, RES_4, RES_5, RES_6, RES_7),
92  PIN(56, WEST, MI2S_0_DATA1, QUP1_L3, RES_3, RES_4, RES_5, RES_6, RES_7),
93  PIN(57, WEST, LPASS_EXT_MCLK0, RES_2, RES_3, RES_4, RES_5, RES_6,
94  RES_7),
95  PIN(58, WEST, LPASS_EXT_MCLK1, RES_2, RES_3, RES_4, RES_5, RES_6,
96  RES_7),
97  PIN(59, NORTH, QUP1_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
98  PIN(60, NORTH, QUP1_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
99  PIN(61, NORTH, QUP1_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
100  PIN(62, NORTH, QUP1_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
101  PIN(63, NORTH, QSPI_CLK, MDP_VSYNC0_OUT, MI2S_2_SCK, MDP_VSYNC1_OUT,
102  MDP_VSYNC2_OUT, MDP_VSYNC3_OUT, RES_7),
103  PIN(64, NORTH, QSPI_DATA_0, MI2S_2_WS, RES_3, RES_4, RES_5, RES_6,
104  RES_7),
105  PIN(65, NORTH, QSPI_DATA_1, MI2S_2_DATA0, RES_3, RES_4, RES_5,
106  RES_6, RES_7),
107  PIN(66, NORTH, QSPI_DATA_2, MI2S_2_DATA1, RES_3, RES_4, RES_5,
108  RES_6, RES_7),
109  PIN(67, NORTH, QSPI_DATA_3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
110  PIN(68, NORTH, QSPI_CS_N_0, QUP1_L4, RES_3, RES_4, RES_5, RES_6, RES_7),
111  PIN(69, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
112  PIN(70, NORTH, RES_1, RES_2, MDP_VSYNC_P_MIRB, LDO_EN, RES_5, RES_6,
113  RES_7),
114  PIN(71, NORTH, RES_1, MDP_VSYNC_S_MIRB, LDO_UPDATE, RES_4, RES_5, RES_6,
115  RES_7),
116  PIN(72, NORTH, QSPI_CS_N_1, QUP1_L5, RES_3, RES_4, RES_5, RES_6, RES_7),
117  PIN(73, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
118  PIN(74, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
119  PIN(75, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
120  PIN(76, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
121  PIN(77, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
122  PIN(78, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
123  PIN(79, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
124  PIN(80, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
125  PIN(81, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
126  PIN(82, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
127  PIN(83, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
128  PIN(84, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
129  PIN(85, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
130  PIN(86, NORTH, QUP1_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
131  PIN(87, NORTH, QUP1_L1, ADSP_EXT_VFR_IRQ, RES_3, RES_4, RES_5,
132  RES_6, RES_7),
133  PIN(88, NORTH, QUP1_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
134  PIN(89, NORTH, QUP1_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
135  PIN(90, NORTH, QUP1_L4, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
136  PIN(91, NORTH, QUP1_L5, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
137  PIN(92, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
138  PIN(93, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
139  PIN(94, SOUTH, QUP0_L5, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
140  PIN(95, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
141  PIN(96, WEST, QLINK_REQUEST, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
142  PIN(97, WEST, QLINK_ENABLE, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
143  PIN(98, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
144  PIN(99, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
145  PIN(100, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
146  PIN(101, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
147  PIN(102, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
148  PIN(103, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
149  PIN(104, WEST, USB_PHY_PS, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
150  PIN(105, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
151  PIN(106, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
152  PIN(107, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
153  PIN(108, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
154  PIN(109, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
155  PIN(110, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
156  PIN(111, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
157  PIN(112, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
158  PIN(113, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
159  PIN(114, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
160  PIN(115, WEST, QUP0_L0, QUP0_L2, RES_3, RES_4, RES_5, RES_6, RES_7),
161  PIN(116, WEST, QUP0_L1, QUP0_L3, RES_3, RES_4, RES_5, RES_6, RES_7),
162  PIN(117, WEST, DP_HOT_PLUG_DETECT_MIRB, RES_2, RES_3, RES_4, RES_5,
163  RES_6, RES_7),
164  PIN(118, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
165 };
166 #endif /* _SOC_QUALCOMM_SC7180_GPIO_H_ */
LDO_EN
#define LDO_EN
Definition: rk808.c:19
QSPI_DATA_1
#define QSPI_DATA_1
Definition: addressmap.h:52
QSPI_DATA_0
#define QSPI_DATA_0
Definition: addressmap.h:51
QSPI_CLK
#define QSPI_CLK
Definition: addressmap.h:50
PIN
#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7)
Definition: gpio.h:10