coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <gpio.h>
6 #include <soc/gpio.h>
8 
9 enum {
10  SKU_37_DROID = 37, /* LTE */
11  SKU_38_DROID = 38, /* LTE + Touch */
12  SKU_39_DROID = 39, /* LTE + KB backlight*/
13  SKU_40_DROID = 40, /* LTE + Touch + KB backlight*/
14 };
15 
16 static const struct pad_config default_override_table[] = {
17  PAD_NC(GPIO_104, UP_20K),
18 
19  /* GPIO_137 -- HP_INT_ODL and would be amend by SSFC. */
20  PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1,
21  DISPUPD),
22 
23  /* EN_PP3300_TOUCHSCREEN */
24  PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0,
25  DISPUPD),
26 
27  PAD_NC(GPIO_213, DN_20K),
28 };
29 
30 static const struct pad_config lte_override_table[] = {
31  /* Default override table. */
32  PAD_NC(GPIO_104, UP_20K),
33 
34  /* GPIO_137 -- HP_INT_ODL and would be amend by SSFC. */
35  PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1,
36  DISPUPD),
37 
38  /* EN_PP3300_TOUCHSCREEN */
39  PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0,
40  DISPUPD),
41 
42  PAD_NC(GPIO_213, DN_20K),
43 
44  /* Be specific to LTE SKU */
45  /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */
46  PAD_CFG_GPO(GPIO_67, 1, PWROK),
47 
48  /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */
49  PAD_CFG_GPO(GPIO_117, 1, PWROK),
50 
51  /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */
52  PAD_CFG_GPO(GPIO_161, 1, DEEP),
53 };
54 
55 const struct pad_config *variant_override_gpio_table(size_t *num)
56 {
59 
60  switch (sku_id) {
61  case SKU_37_DROID:
62  case SKU_38_DROID:
63  case SKU_39_DROID:
64  case SKU_40_DROID:
66  return lte_override_table;
67  default:
70  }
71 }
72 
73 static const struct pad_config lte_early_override_table[] = {
74  /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */
75  PAD_CFG_GPO(GPIO_67, 1, PWROK),
76 
77  /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */
78  PAD_CFG_GPO(GPIO_117, 1, PWROK),
79 
80  /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */
81  PAD_CFG_GPO(GPIO_161, 0, DEEP),
82 };
83 
85 {
87 
89 }
uint32_t sku_id(void)
#define ARRAY_SIZE(a)
Definition: helpers.h:12
uint32_t google_chromeec_get_board_sku(void)
Definition: ec_skuid.c:6
#define GPIO_161
Definition: gpio_apl.h:282
#define GPIO_213
Definition: gpio_apl.h:171
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
Definition: gpio.c:450
const struct soc_amd_gpio *__weak variant_early_override_gpio_table(size_t *size)
Definition: gpio.c:317
static const struct pad_config lte_override_table[]
Definition: gpio.c:30
@ SKU_39_DROID
Definition: gpio.c:12
@ SKU_37_DROID
Definition: gpio.c:10
@ SKU_38_DROID
Definition: gpio.c:11
@ SKU_40_DROID
Definition: gpio.c:13
static const struct pad_config default_override_table[]
Definition: gpio.c:16
static const struct pad_config lte_early_override_table[]
Definition: gpio.c:73
#define GPIO_104
Definition: gpio.h:69
#define GPIO_67
Definition: gpio.h:53
#define GPIO_146
Definition: gpio.h:93
#define PAD_NC(pin)
Definition: gpio_defs.h:263
#define GPIO_137
Definition: gpio.h:92
#define GPIO_117
Definition: gpio.h:84
#define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm)
Definition: gpio_defs.h:391
#define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm)
Definition: gpio_defs.h:277
#define PAD_CFG_GPO(pad, val, rst)
Definition: gpio_defs.h:247
unsigned int uint32_t
Definition: stdint.h:14