coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <variants.h>
4 
5 /*
6  * All definitions are taken from a comparison of the output of "inteltool -a"
7  * using the stock BIOS and with coreboot.
8  */
9 
10 /* Early pad configuration in bootblock */
11 const struct pad_config early_gpio_table[] = {
12  /* C20: UART2_RXD_R */
13  PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
14  /* C21: UART2_TXD_R */
15  PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
16 };
17 
18 const struct pad_config *variant_early_gpio_table(size_t *num)
19 {
21  return early_gpio_table;
22 }
23 
24 /* Pad configuration in ramstage. */
25 const struct pad_config gpio_table[] = {
26  /* REFERENCE: EP PER SCHEMATIC */
27 
28  /* GPD0: PCH_BATLOW# */
29  PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
30  /* GPD1: AC_PRESENT */
31  PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
32  /* GPD2: LAN_WAKE# */
33  PAD_NC(GPD2, NONE),
34  /* GPD3: SIO_PWRBTN# */
35  PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
36  /* GPD4: SIO_SLP_S3# */
37  PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
38  /* GPD5: SIO_SLP_S4# */
39  PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
40  /* GPD6: SIO_SLP_A# */
41  PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
42  /* GPD7: PCH_TBT_PERST# */
43  PAD_CFG_GPO(GPD7, 0, PLTRST),
44  /* GPD8: SUSCLK */
45  PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
46  /* GPD9: SIO_SLP_WLAN# */
47  PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
48  /* GPD10: SIO_SLP_S5# */
49  PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
50  /* GPD11: PM_LANPHY_EN */
51  PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
52 
53  /* A0: ESPI_IO_0 */
54  /* A1: ESPI_IO_1 */
55  /* A2: ESPI_IO_2 */
56  /* A3: ESPI_IO_3 */
57  /* A4: ESPI_CS_L */
58  /* A5: ESPI_CLK */
59  /* A6: Not Connected(TP764) */
60  /* A7: WLAN_PCM_CLK */
61  PAD_NC(GPP_A7, NONE),
62  /* A8: WLAN_PCM_RST */
63  PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2),
64  /* A9: WLAN_PCM_CLKREQ0 */
65  PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2),
66  /* A10: WLAN_PCM_IN */
68  /* A11: M2_CPU_SSD_RST_N */
69  PAD_CFG_GPO(GPP_A11, 1, PLTRST),
70  /* A12: SATAGP_1 */
71  PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
72  /* A13: Not Connected */
74  /* A14: Not Connected */
76  /* A15 Not Connected */
78  /* A16: USB2_OCB_3 */
79  PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
80  /* A17: Not Connected */
82  /* A18: DDIB_HPD */
83  PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
84  /* A19 Not Connected */
86  /* A20: Not Connected */
88  /* A21 Not Connected */
90  /* A22: Not Connected */
92  /* A23: TC_RETIMER_FORCE_PWR */
93  PAD_CFG_GPO(GPP_A23, 0, PLTRST),
94 
95  /* B0: CORE_VID_0 */
96  PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
97  /* B1: CORE_VID_1 */
98  PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
99  /* B2: VRALERT_N */
100  PAD_NC(GPP_B2, NONE),
101  /* B3: Not Connected */
102  PAD_NC(GPP_B3, NONE),
103  /* B4: Not Connected */
104  PAD_NC(GPP_B4, NONE),
105  /* B5: Not Connected */
106  PAD_NC(GPP_B5, NONE),
107  /* B6: Not Connected */
108  PAD_NC(GPP_B6, NONE),
109  /* B7: Not Connected */
110  PAD_NC(GPP_B7, NONE),
111  /* B8: Not Connected */
112  PAD_NC(GPP_B8, NONE),
113  /* B9: PWR_MON_I2C_SDA_R */
114  PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
115  /* B10: PWR_MON_I2C_SCL_R */
116  PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
117  /* B11: I2C_PMC_PD_INT_N */
118  PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
119  /* B12: PM_SLP_S0_N */
120  PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
121  /* B13: PLT_RST_N */
122  PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
123  /* B14: FPS_RST_N */
124  PAD_CFG_GPO(GPP_B14, 1, PLTRST),
125  /* B15: Not Connected */
126  PAD_NC(GPP_B15, NONE),
127  /* B16: M2_PCH_SSD_PWREN */
128  PAD_NC(GPP_B16, NONE),
129  /* B17: Not Connected */
130  PAD_NC(GPP_B17, NONE),
131  /* B18: UF_CAM_STROBE */
132  PAD_CFG_GPO(GPP_B18, 0, DEEP),
133  /* B19: GSPI1_CS0_FPS_N */
134  PAD_NC(GPP_B19, NONE),
135  /* B20: GSPI1_CLK_FPS */
136  PAD_NC(GPP_B20, NONE),
137  /* B21: GSPI1_MISO_FPS */
138  PAD_NC(GPP_B21, NONE),
139  /* B22: GSPI1_MOSI_FPS */
140  PAD_CFG_GPO(GPP_B22, 0, DEEP),
141  /* B23: CPU_CLKFREQ */
142  PAD_CFG_GPO(GPP_B23, 0, DEEP),
143 
144  /* C0: SMBCLK */
145  PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
146  /* C1: SMBDATA */
147  PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
148  /* C2: SMBALERT_N */
149  PAD_CFG_GPO(GPP_C2, 0, DEEP),
150  /* C3: SML0_CLK */
151  PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
152  /* C4: SML0_DATA */
153  PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
154  /* C5: SML0ALERT_IN */
155  PAD_CFG_GPO(GPP_C5, 0, DEEP),
156  /* C6: SML1_CLK */
157  PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),
158  /* C7: SML1_DATA */
159  PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),
160  /* C8: CLICK_PAD_INT_N */
161  PAD_CFG_GPI_APIC_LOW(GPP_C8, NONE, PLTRST),
162  /* C9: Not Connected */
163  PAD_NC(GPP_C9, NONE),
164  /* C10: Not Connected */
165  PAD_NC(GPP_C10, NONE),
166  /* C11: Not Connected */
167  PAD_NC(GPP_C11, NONE),
168  /* C12: Not Connected */
169  PAD_NC(GPP_C12, NONE),
170  /* C13: Not Connected */
171  PAD_NC(GPP_C13, NONE),
172  /* C14: TPM_IRQ */
173  PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
174  /* C15: TPM_RST */
175  PAD_NC(GPP_C15, NONE),
176  /* C16: I2C0_SDA */
177  PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
178  /* C17: I2C0_SCL */
179  PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
180  /* C18: TOUCH_I2C_SDA */
181  PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
182  /* C19: TOUCH_I2C_CLK */
183  PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
184  /* C22: Not Connected */
185  PAD_NC(GPP_C22, NONE),
186  /* C23: WLAN_WAKE_N */
187  PAD_NC(GPP_C23, NONE),
188 
189  /* D0: ACCEL1_INT */
190  PAD_NC(GPP_D0, NONE),
191  /* D1: ACCEL2_INT */
192  PAD_NC(GPP_D1, NONE),
193  /* D2: Not Connected */
194  PAD_NC(GPP_D2, NONE),
195  /* D3: Not Connected */
196  PAD_NC(GPP_D3, NONE),
197  /* D4: Not Connected */
198  PAD_NC(GPP_D4, NONE),
199  /* D5: CLKREQ0_M2_SSD_N */
200  PAD_NC(GPP_D5, NONE),
201  /* D6: CLKREQ1_WLAN_N */
202  PAD_NC(GPP_D6, NONE),
203  /* D7: LAN_CLKREQ# */
204  PAD_NC(GPP_D7, NONE),
205  /* D8: Not Connected */
206  PAD_NC(GPP_D8, NONE),
207  /* D9: Not Connected */
208  PAD_NC(GPP_D9, NONE),
209  /* D10: Not Connected */
210  PAD_NC(GPP_D10, NONE),
211  /* D11: Not Connected */
212  PAD_NC(GPP_D11, NONE),
213  /* D12: Not Connected */
214  PAD_NC(GPP_D12, NONE),
215  /* D13: Not Connected */
216  PAD_NC(GPP_D13, NONE),
217  /* D14: Not Connected */
218  PAD_NC(GPP_D14, NONE),
219  /* D15: Not Connected */
220  PAD_NC(GPP_D15, NONE),
221  /* D16: CPU_SSD_PWREN */
222  PAD_CFG_GPO(GPP_D16, 1, PLTRST),
223  /* D17: Not Connected */
224  PAD_NC(GPP_D17, NONE),
225  /* D18: Not Connected */
226  PAD_NC(GPP_D18, NONE),
227  /* D19: GPPC_D_19_WFCAM_PD_N */
228  PAD_CFG_TERM_GPO(GPP_D19, 1, UP_20K, DEEP),
229 
230  /* E0: SATAXPCIE_0_SATAGP_0 */
231  PAD_NC(GPP_E0, NONE),
232  /* E1: Not Connected */
233  PAD_NC(GPP_E1, NONE),
234  /* E2: Not Connected */
235  PAD_NC(GPP_E2, NONE),
236  /* E3: FPS_INT */
237  PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1),
238  /* E4: Not Connected */
239  PAD_NC(GPP_E4, NONE),
240  /* E5: Not Connected */
241  PAD_NC(GPP_E5, NONE),
242  /* E6: THC0_SPI1_RST_N_TCH_PNL */
243  PAD_NC(GPP_E6, NONE),
244  /* E7: EC_SMI_LP_N */
245  PAD_NC(GPP_E7, NONE),
246  /* E8: EC_SLP_S0IX_N */
247  PAD_NC(GPP_E8, NONE),
248  /* E9: USB2_TCP01_OC_N */
249  PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
250  /* E10: SPI1_TCH_PNL_CS_N */
251  PAD_NC(GPP_E10, NONE),
252  /* E11: SPI1_CLK */
253  PAD_NC(GPP_E11, NONE),
254  /* E12: Not Connected */
255  PAD_NC(GPP_E12, NONE),
256  /* E13: Not Connected */
257  PAD_NC(GPP_E13, NONE),
258  /* E14: EDP_HPD */
259  PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
260  /* E15: Not Connected */
261  PAD_NC(GPP_E15, NONE),
262  /* E16: Not Connected */
263  PAD_NC(GPP_E16, NONE),
264  /* E17: Not Connected */
265  PAD_NC(GPP_E17, NONE),
266  /* E18: TBT_LSX0_TXD */
267  PAD_NC(GPP_E18, NATIVE),
268  /* E19: TBT_LSX0_RXD */
269  PAD_NC(GPP_E19, NATIVE),
270  /* E20: Not Connected */
271  PAD_NC(GPP_E20, NONE),
272  /* E21: TBT_LSX1_RXD */
273  PAD_NC(GPP_E21, NATIVE),
274  /* E22: Not Connected */
275  PAD_NC(GPP_E22, NONE),
276  /* E23: Not Connected */
277  PAD_NC(GPP_E23, NONE),
278 
279  /* F0: CNV_BRI_DT_BT_UART0_RTS_R */
280  PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
281  /* F1: CNV_BRI_RSP_BT_UART0_RX_R */
282  PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
283  /* F2: CNV_RGI_DT_BT_UART0_TX_R */
284  PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
285  /* F3: CNV_RGI_RSP_BT_UART0_CTS */
286  PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
287  /* F4: Not Connected */
288  PAD_NC(GPP_F4, NONE),
289  /* F5: GPPC_F5_MODEM_CLKREQ */
290  PAD_NC(GPP_F5, NONE),
291  /* F6: Not Connected */
292  PAD_NC(GPP_F6, NONE),
293  /* F7: BIOS_REC */
294  PAD_CFG_GPO(GPP_F7, 1, PLTRST),
295  /* F8: Not Connected */
296  PAD_NC(GPP_F8, NONE),
297  /* F9: Not Connected */
298  PAD_NC(GPP_F9, NONE),
299  /* F10: GPPC_F_10 */
300  PAD_CFG_GPO(GPP_F10, 0, DEEP),
301  /* F11: Not Connected */
302  PAD_NC(GPP_F11, NONE),
303  /* F12: Not Connected */
304  PAD_NC(GPP_F12, NONE),
305  /* F13: Not Connected */
306  PAD_NC(GPP_F13, NONE),
307  /* F14: Not Connected */
308  PAD_NC(GPP_F14, NONE),
309  /* F15: Not Connected */
310  PAD_NC(GPP_F15, NONE),
311  /* F16: Not Connected */
312  PAD_NC(GPP_F16, NONE),
313  /* F17: TOUCH_PANEL_RESET_N */
314  PAD_NC(GPP_F17, NONE),
315  /* F18: TOUCH_PANEL_INT_N */
316  PAD_NC(GPP_F18, NONE),
317  /* F19: Not Connected */
318  PAD_NC(GPP_F19, NONE),
319  /* F20: Not Connected */
320  PAD_NC(GPP_F20, NONE),
321  /* F21: Not Connected */
322  PAD_NC(GPP_F21, NONE),
323  /* F22: Not Connected */
324  PAD_NC(GPP_F22, NONE),
325  /* F23: Not Connected */
326  PAD_NC(GPP_F23, NONE),
327 
328  /* H0: GPPC_H0_M2_SSD_RST_N */
329  PAD_CFG_GPO(GPP_H0, 0, DEEP),
330  /* H1: GPPC_H_1 */
331  PAD_CFG_GPO(GPP_H1, 0, DEEP),
332  /* H2: GPPC_H_2 */
333  PAD_CFG_GPO(GPP_H2, 0, DEEP),
334  /* H3: Not Connected */
335  PAD_NC(GPP_H3, NONE),
336  /* H4: GSENSOR_I2C_SDA */
337  PAD_NC(GPP_H4, NONE),
338  /* H5: GSENSOR_I2C_SCL */
339  PAD_NC(GPP_H5, NONE),
340  /* H6: Not Connected */
341  PAD_NC(GPP_H6, NONE),
342  /* H7: Not Connected */
343  PAD_NC(GPP_H7, NONE),
344  /* H8: Not Connected */
345  PAD_NC(GPP_H8, NONE),
346  /* H9: Not Connected */
347  PAD_NC(GPP_H9, NONE),
348  /* H10: Not Connected */
349  PAD_NC(GPP_H10, NONE),
350  /* H11: Not Connected */
351  PAD_NC(GPP_H11, NONE),
352  /* H12: Not Connected */
353  PAD_NC(GPP_H12, NONE),
354  /* H13: Not Connected */
355  PAD_NC(GPP_H13, NONE),
356  /* H14: Not Connected */
357  PAD_NC(GPP_H14, NONE),
358  /* H15: Not Connected */
359  PAD_NC(GPP_H15, NONE),
360  /* H16: DDIB_DDC_SCL */
361  PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
362  /* H17: DDIB_DDC_SDA */
363  PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
364  /* H18: CPU_C10_GATE_N */
365  PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
366  /* H19: UART_BT_WAKE_N */
367  PAD_NC(GPP_H19, NONE),
368  /* H20: Not Connected */
369  PAD_NC(GPP_H20, NONE),
370  /* H21: Not Connected */
371  PAD_NC(GPP_H21, NONE),
372  /* H22: Not Connected */
373  PAD_NC(GPP_H22, NONE),
374  /* H23: Not Connected */
375  PAD_NC(GPP_H23, NONE),
376 
377  /* R0: HDA_BCLK */
378  PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
379  /* R1: HDA_SYNC */
380  PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
381  /* R2: HDA_SDO */
382  PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
383  /* R3: HDA_SDI_0_SSP0_RXD */
384  PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
385  /* R4: Not Connected */
386  PAD_NC(GPP_R4, NONE),
387  /* R5: Not Connected */
388  PAD_NC(GPP_R5, NONE),
389  /* R6: Not Connected */
390  PAD_NC(GPP_R6, NONE),
391  /* R7: Not Connected */
392  PAD_NC(GPP_R7, NONE),
393 
394  /* S0: Not Connected */
395  PAD_NC(GPP_S0, NONE),
396  /* S1: Not Connected */
397  PAD_NC(GPP_S1, NONE),
398  /* S2: Not Connected */
399  PAD_NC(GPP_S2, NONE),
400  /* S3: Not Connected */
401  PAD_NC(GPP_S3, NONE),
402  /* S4: Not Connected */
403  PAD_NC(GPP_S4, NONE),
404  /* S5: Not Connected */
405  PAD_NC(GPP_S5, NONE),
406  /* S6: Not Connected */
407  PAD_NC(GPP_S6, NONE),
408  /* S7: Not Connected */
409  PAD_NC(GPP_S7, NONE),
410 
411  /* T2: Not Connected */
412  PAD_NC(GPP_T2, NONE),
413  /* T3: Not Connected */
414  PAD_NC(GPP_T3, NONE),
415 
416  /* U4: Not Connected */
417  PAD_NC(GPP_U4, NONE),
418  /* U5: Not Connected */
419  PAD_NC(GPP_U5, NONE),
420 };
421 
422 const struct pad_config *variant_gpio_table(size_t *num)
423 {
424  *num = ARRAY_SIZE(gpio_table);
425  return gpio_table;
426 }
#define GPD11
#define GPP_H22
#define GPP_C15
#define GPP_T3
Definition: gpio_soc_defs.h:94
#define GPD3
#define GPP_H20
#define GPP_B6
Definition: gpio_soc_defs.h:59
#define GPP_H19
#define GPP_D1
#define GPD9
#define GPP_C2
#define GPP_D10
#define GPP_D8
#define GPP_D17
#define GPP_E3
#define GPP_A18
#define GPP_F21
#define GPP_C12
#define GPP_F12
#define GPP_F16
#define GPP_S4
#define GPP_H15
#define GPP_H16
#define GPP_R4
#define GPP_E0
#define GPP_R7
#define GPP_F6
#define GPP_H18
#define GPP_D14
#define GPP_B1
Definition: gpio_soc_defs.h:54
#define GPP_F20
#define GPP_S0
#define GPP_F23
#define GPP_C5
#define GPP_H11
#define GPP_A14
#define GPP_B12
Definition: gpio_soc_defs.h:65
#define GPP_H17
#define GPP_D12
#define GPP_S5
#define GPP_B16
Definition: gpio_soc_defs.h:69
#define GPP_B2
Definition: gpio_soc_defs.h:55
#define GPP_D7
#define GPP_R3
#define GPP_B13
Definition: gpio_soc_defs.h:66
#define GPP_E6
#define GPP_F0
#define GPP_D6
#define GPP_A19
#define GPP_D2
#define GPP_H12
#define GPP_H6
#define GPP_C9
#define GPP_H2
#define GPP_C22
#define GPP_R6
#define GPP_H9
#define GPD0
#define GPP_D9
#define GPP_R0
#define GPP_F5
#define GPP_B15
Definition: gpio_soc_defs.h:68
#define GPP_E13
#define GPP_H21
#define GPP_C23
#define GPP_H13
#define GPP_C8
#define GPP_S7
#define GPP_D11
#define GPP_H7
#define GPP_H1
#define GPP_C11
#define GPP_H14
#define GPP_D5
#define GPP_B22
Definition: gpio_soc_defs.h:75
#define GPP_A23
#define GPP_C18
#define GPP_F9
#define GPP_S3
#define GPP_C13
#define GPP_E14
#define GPP_E23
#define GPP_E9
#define GPP_C17
#define GPP_E8
#define GPP_A7
#define GPP_E5
#define GPD7
#define GPP_B8
Definition: gpio_soc_defs.h:61
#define GPP_S1
#define GPP_C20
#define GPP_B20
Definition: gpio_soc_defs.h:73
#define GPP_A20
#define GPP_A16
#define GPP_F1
#define GPP_F17
#define GPP_A12
#define GPP_F15
#define GPP_D4
#define GPP_C10
#define GPP_C6
#define GPD2
#define GPP_F10
#define GPP_E7
#define GPP_C16
#define GPP_F7
#define GPD1
#define GPP_F13
#define GPP_C4
#define GPP_D18
#define GPP_S6
#define GPP_B19
Definition: gpio_soc_defs.h:72
#define GPP_E17
#define GPP_E2
#define GPP_E19
#define GPP_H0
#define GPP_H5
#define GPP_C21
#define GPP_R2
#define GPP_B9
Definition: gpio_soc_defs.h:62
#define GPD10
#define GPP_E18
#define GPP_F14
#define GPP_H3
#define GPP_F4
#define GPP_A10
#define GPP_A8
#define GPP_D0
#define GPP_B14
Definition: gpio_soc_defs.h:67
#define GPP_B11
Definition: gpio_soc_defs.h:64
#define GPP_D13
#define GPP_B18
Definition: gpio_soc_defs.h:71
#define GPP_B5
Definition: gpio_soc_defs.h:58
#define GPP_B0
Definition: gpio_soc_defs.h:53
#define GPP_A11
#define GPP_R5
#define GPP_C14
#define GPP_E20
#define GPP_A15
#define GPP_A9
#define GPP_E10
#define GPP_F8
#define GPP_C19
#define GPD8
#define GPP_A13
#define GPP_S2
#define GPP_A21
#define GPP_B23
Definition: gpio_soc_defs.h:76
#define GPP_E15
#define GPP_B10
Definition: gpio_soc_defs.h:63
#define GPP_E16
#define GPP_D19
#define GPP_T2
Definition: gpio_soc_defs.h:93
#define GPP_C1
#define GPP_F2
#define GPP_E11
#define GPD6
#define GPP_F18
#define GPP_B3
Definition: gpio_soc_defs.h:56
#define GPP_A22
#define GPP_F22
#define GPP_D15
#define GPP_F11
#define GPP_B21
Definition: gpio_soc_defs.h:74
#define GPD4
#define GPP_B4
Definition: gpio_soc_defs.h:57
#define GPP_D16
#define GPP_F3
#define GPP_E22
#define GPP_H10
#define GPP_E21
#define GPP_C3
#define GPP_E12
#define GPP_A17
#define GPP_B17
Definition: gpio_soc_defs.h:70
#define GPP_E4
#define GPP_C0
#define GPD5
#define GPP_E1
#define GPP_H8
#define GPP_F19
#define GPP_H4
#define GPP_H23
#define GPP_B7
Definition: gpio_soc_defs.h:60
#define GPP_C7
#define GPP_D3
#define GPP_R1
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define GPP_U5
#define GPP_U4
const struct pad_config * variant_early_gpio_table(size_t *num)
Definition: gpio.c:204
const struct pad_config *__weak variant_gpio_table(size_t *num)
Definition: gpio.c:406
const struct pad_config early_gpio_table[]
Definition: gpio.c:373
const struct pad_config gpio_table[]
Definition: gpio.c:33
#define PAD_NC(pin)
Definition: gpio_defs.h:263
#define PAD_CFG_TERM_GPO(pad, val, pull, rst)
Definition: gpio_defs.h:262
#define PAD_CFG_NF(pad, pull, rst, func)
Definition: gpio_defs.h:197
#define PAD_CFG_GPO(pad, val, rst)
Definition: gpio_defs.h:247
#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst)
Definition: gpio_defs.h:402