|
| enum | {
OSC_FREQ_12 = 8
, OSC_FREQ_13 = 0
, OSC_FREQ_16P8 = 1
, OSC_FREQ_19P2 = 4
,
OSC_FREQ_26 = 12
, OSC_FREQ_38P4 = 5
, OSC_FREQ_48 = 9
} |
| |
| enum | {
SCLK_SYS_STATE_STDBY
, SCLK_SYS_STATE_IDLE
, SCLK_SYS_STATE_RUN
, SCLK_SYS_STATE_IRQ = 4U
,
SCLK_SYS_STATE_FIQ = 8U
} |
| |
| enum | {
SCLK_SOURCE_CLKM
, SCLK_SOURCE_PLLC_OUT1
, SCLK_SOURCE_PLLP_OUT4
, SCLK_SOURCE_PLLP_OUT3
,
SCLK_SOURCE_PLLP_OUT2
, SCLK_SOURCE_PLLC_OUT0
, SCLK_SOURCE_CLKS
, SCLK_SOURCE_PLLM_OUT1
} |
| |
| enum | { CRC_CCLK_BRST_POL_PLLX_OUT0 = 0x8
, CRC_CCLK_BRST_POL_CPU_STATE_RUN = 0x2
} |
| |
| enum | { CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB = 1 << 31
} |
| |
| enum | { CRC_CLK_CLR_CPU0_STP = 0x1 << 8
, CRC_CLK_CLR_CPU1_STP = 0x1 << 9
, CRC_CLK_CLR_CPU2_STP = 0x1 << 10
, CRC_CLK_CLR_CPU3_STP = 0x1 << 11
} |
| |
| enum | {
CRC_RST_CPUG_CLR_CPU0 = 0x1 << 0
, CRC_RST_CPUG_CLR_CPU1 = 0x1 << 1
, CRC_RST_CPUG_CLR_CPU2 = 0x1 << 2
, CRC_RST_CPUG_CLR_CPU3 = 0x1 << 3
,
CRC_RST_CPUG_CLR_DBG0 = 0x1 << 12
, CRC_RST_CPUG_CLR_DBG1 = 0x1 << 13
, CRC_RST_CPUG_CLR_DBG2 = 0x1 << 14
, CRC_RST_CPUG_CLR_DBG3 = 0x1 << 15
,
CRC_RST_CPUG_CLR_CORE0 = 0x1 << 16
, CRC_RST_CPUG_CLR_CORE1 = 0x1 << 17
, CRC_RST_CPUG_CLR_CORE2 = 0x1 << 18
, CRC_RST_CPUG_CLR_CORE3 = 0x1 << 19
,
CRC_RST_CPUG_CLR_CX0 = 0x1 << 20
, CRC_RST_CPUG_CLR_CX1 = 0x1 << 21
, CRC_RST_CPUG_CLR_CX2 = 0x1 << 22
, CRC_RST_CPUG_CLR_CX3 = 0x1 << 23
,
CRC_RST_CPUG_CLR_L2 = 0x1 << 24
, CRC_RST_CPUG_CLR_NONCPU = 0x1 << 29
, CRC_RST_CPUG_CLR_PDBG = 0x1 << 30
} |
| |
| enum | {
CRC_RST_CPULP_CLR_CPU0 = 0x1 << 0
, CRC_RST_CPULP_CLR_DBG0 = 0x1 << 12
, CRC_RST_CPULP_CLR_CORE0 = 0x1 << 16
, CRC_RST_CPULP_CLR_CX0 = 0x1 << 20
,
CRC_RST_CPULP_CLR_L2 = 0x1 << 24
, CRC_RST_CPULP_CLR_NONCPU = 0x1 << 29
, CRC_RST_CPULP_CLR_PDBG = 0x1 << 30
} |
| |
1.9.1