coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c File Reference
#include <gpio.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include <string.h>
Include dependency graph for romstage.c:

Go to the source code of this file.

Functions

void mainboard_memory_init_params (FSPM_UPD *memupd)
 
void mainboard_save_dimm_info (void)
 

Variables

static const struct lpddr4_sku skus []
 
static const struct lpddr4_cfg lp4cfg
 
static const uint8_t ch0_bit_swizzling []
 
static const uint8_t ch1_bit_swizzling []
 
static const uint8_t ch2_bit_swizzling []
 
static const uint8_t ch3_bit_swizzling []
 

Function Documentation

◆ mainboard_memory_init_params()

void mainboard_memory_init_params ( FSPM_UPD *  memupd)

Definition at line 52 of file romstage.c.

References ch0_bit_swizzling, ch1_bit_swizzling, ch2_bit_swizzling, ch3_bit_swizzling, config, FSP_M_CONFIG, and memcpy().

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◆ mainboard_save_dimm_info()

void mainboard_save_dimm_info ( void  )

Definition at line 126 of file romstage.c.

References lp4cfg, and save_lpddr4_dimm_info().

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Variable Documentation

◆ ch0_bit_swizzling

const uint8_t ch0_bit_swizzling[]
static
Initial value:
= {
0x0f, 0x0b, 0x0d, 0x0e, 0x09, 0x0c, 0x0a, 0x08,
0x06, 0x04, 0x05, 0x07, 0x03, 0x02, 0x01, 0x00,
0x1e, 0x19, 0x18, 0x1c, 0x1d, 0x1b, 0x1f, 0x1a,
0x14, 0x15, 0x17, 0x10, 0x16, 0x12, 0x11, 0x13
}

Definition at line 24 of file romstage.c.

Referenced by mainboard_memory_init_params().

◆ ch1_bit_swizzling

const uint8_t ch1_bit_swizzling[]
static
Initial value:
= {
0x03, 0x05, 0x06, 0x07, 0x01, 0x04, 0x02, 0x00,
0x0c, 0x0d, 0x0e, 0x0b, 0x0a, 0x08, 0x09, 0x0f,
0x10, 0x16, 0x15, 0x13, 0x14, 0x17, 0x12, 0x11,
0x1f, 0x1e, 0x1b, 0x19, 0x18, 0x1d, 0x1c, 0x1a
}

Definition at line 31 of file romstage.c.

Referenced by mainboard_memory_init_params().

◆ ch2_bit_swizzling

const uint8_t ch2_bit_swizzling[]
static
Initial value:
= {
0x08, 0x0d, 0x0b, 0x0e, 0x09, 0x0f, 0x0c, 0x0a,
0x04, 0x00, 0x02, 0x06, 0x05, 0x07, 0x03, 0x01,
0x1b, 0x1c, 0x1f, 0x1d, 0x1a, 0x18, 0x19, 0x1e,
0x17, 0x12, 0x15, 0x16, 0x13, 0x10, 0x14, 0x11
}

Definition at line 38 of file romstage.c.

Referenced by mainboard_memory_init_params().

◆ ch3_bit_swizzling

const uint8_t ch3_bit_swizzling[]
static
Initial value:
= {
0x03, 0x07, 0x06, 0x05, 0x01, 0x04, 0x02, 0x00,
0x0c, 0x0f, 0x0d, 0x0e, 0x0a, 0x08, 0x09, 0x0b,
0x10, 0x11, 0x12, 0x13, 0x16, 0x14, 0x17, 0x15,
0x1c, 0x1e, 0x1d, 0x19, 0x1f, 0x18, 0x1b, 0x1a
}

Definition at line 45 of file romstage.c.

Referenced by mainboard_memory_init_params().

◆ lp4cfg

const struct lpddr4_cfg lp4cfg
static
Initial value:
= {
.skus = skus,
.num_skus = ARRAY_SIZE(skus),
}
#define ARRAY_SIZE(a)
Definition: helpers.h:12
static const struct lpddr4_sku skus[]
Definition: romstage.c:8

Definition at line 1 of file romstage.c.

Referenced by mainboard_save_dimm_info().

◆ skus

const struct lpddr4_sku skus[]
static
Initial value:
= {
[0] = {
.speed = LP4_SPEED_2133,
.ch0_rank_density = LP4_8Gb_DENSITY,
.ch1_rank_density = LP4_8Gb_DENSITY,
.ch0_dual_rank = 1,
.ch1_dual_rank = 1,
.part_num = "D9SKJ",
},
}
@ LP4_SPEED_2133
Definition: meminit.h:48
@ LP4_8Gb_DENSITY
Definition: meminit.h:56

Definition at line 1 of file romstage.c.