coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
3
#include <baseboard/gpio.h>
4
#include <baseboard/variants.h>
5
#include <
commonlib/helpers.h
>
6
7
/* Pad configuration in ramstage */
8
static
const
struct
pad_config
override_gpio_table
[] = {
9
/* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
10
PAD_CFG_GPO
(
GPP_A7
, 1, DEEP),
11
/* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
12
PAD_CFG_GPO
(
GPP_A8
, 0, DEEP),
13
/* A10 : I2S2_RXD ==> EN_SPKR_PA */
14
PAD_CFG_GPO
(
GPP_A10
, 1, DEEP),
15
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
16
PAD_CFG_GPO
(
GPP_A13
, 1, DEEP),
17
/* A16 : USB_OC3# ==> USB_C0_OC_ODL */
18
PAD_CFG_NF
(
GPP_A16
,
NONE
, DEEP, NF1),
19
/* A18 : DDSP_HPDB ==> HDMI_HPD */
20
PAD_CFG_NF
(
GPP_A18
,
NONE
, DEEP, NF1),
21
/* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */
22
PAD_NC
(
GPP_A19
,
NONE
),
23
/* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */
24
PAD_NC
(
GPP_A20
,
NONE
),
25
/* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
26
PAD_CFG_GPO
(
GPP_A22
, 1, DEEP),
27
/* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
28
PAD_CFG_NF
(
GPP_A23
,
NONE
, DEEP, NF1),
29
30
/* B2 : VRALERT# ==> EN_PP3300_SSD */
31
PAD_CFG_GPO
(
GPP_B2
, 1, PLTRST),
32
/* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
33
PAD_CFG_NF
(
GPP_B9
,
NONE
, DEEP, NF1),
34
/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
35
PAD_CFG_NF
(
GPP_B10
,
NONE
, DEEP, NF1),
36
/* B22 : GSPI1_MOSI ==> NC */
37
PAD_NC
(
GPP_B22
,
NONE
),
38
39
/* C0 : SMBCLK ==> EN_PP3300_WLAN */
40
PAD_CFG_GPO
(
GPP_C0
, 1, DEEP),
41
/* C10 : UART0_RTS# ==> USI_RST_L */
42
PAD_CFG_GPO
(
GPP_C10
, 0, DEEP),
43
/* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
44
PAD_CFG_NF
(
GPP_C16
,
NONE
, DEEP, NF1),
45
/* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
46
PAD_CFG_NF
(
GPP_C17
,
NONE
, DEEP, NF1),
47
/* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
48
PAD_CFG_NF
(
GPP_C18
,
NONE
, DEEP, NF1),
49
/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
50
PAD_CFG_NF
(
GPP_C19
,
NONE
, DEEP, NF1),
51
52
/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
53
PAD_CFG_NF
(
GPP_D8
,
NONE
, DEEP, NF1),
54
/* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */
55
PAD_CFG_NF
(
GPP_D13
,
NONE
, DEEP, NF1),
56
/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
57
PAD_CFG_NF
(
GPP_D14
,
NONE
, DEEP, NF1),
58
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
59
PAD_CFG_GPO
(
GPP_D16
, 1, DEEP),
60
/* D17 : ISH_GP4 ==> EN_FCAM_PWR */
61
PAD_CFG_GPO
(
GPP_D17
, 1, DEEP),
62
63
/* E3 : CPU_GP0 ==> USI_REPORT_EN */
64
PAD_CFG_GPO
(
GPP_E3
, 1, DEEP),
65
/* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
66
PAD_CFG_GPI
(
GPP_E4
,
NONE
, DEEP),
67
/* E7 : CPU_GP1 ==> USI_INT */
68
PAD_CFG_GPI_APIC
(
GPP_E7
,
NONE
, PLTRST, LEVEL,
NONE
),
69
/* E8 : SPI1_CS1# ==> SLP_S0IX */
70
PAD_CFG_GPO
(
GPP_E8
, 0, DEEP),
71
/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
72
PAD_CFG_GPI
(
GPP_E11
,
NONE
, DEEP),
73
/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
74
PAD_CFG_GPI_IRQ_WAKE(
GPP_E15
,
NONE
, DEEP, LEVEL, INVERT),
75
/* E18 : DDP1_CTRLCLK ==> NC */
76
PAD_NC
(
GPP_E18
,
NONE
),
77
/* E20 : DDP2_CTRLCLK ==> NC */
78
PAD_NC
(
GPP_E20
,
NONE
),
79
80
/* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */
81
PAD_CFG_GPI_INT
(
GPP_F8
,
NONE
, PLTRST, EDGE_BOTH),
82
/* F11 : GPPF11_THC1_SPI2_CLK ==> NC */
83
PAD_NC
(
GPP_F12
,
NONE
),
84
/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
85
PAD_CFG_GPO
(
GPP_F13
, 1, DEEP),
86
87
/* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
88
PAD_CFG_GPO
(
GPP_H3
, 1, DEEP),
89
/* H8 : I2C4_SDA ==> PCB_ID0 */
90
PAD_CFG_GPI
(
GPP_H8
,
NONE
, DEEP),
91
/* H9 : I2C4_SCL ==> PCB_ID1 */
92
PAD_CFG_GPI
(
GPP_H9
,
NONE
, DEEP),
93
/* H10 : SRCCLKREQ4# ==> NC */
94
PAD_NC
(
GPP_H10
,
NONE
),
95
/* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */
96
PAD_CFG_GPI
(
GPP_H13
,
NONE
, DEEP),
97
/* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */
98
PAD_CFG_NF
(
GPP_H16
,
NONE
, DEEP, NF1),
99
/* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */
100
PAD_CFG_NF
(
GPP_H17
,
NONE
, DEEP, NF1),
101
102
/* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
103
PAD_CFG_NF
(
GPP_R0
,
NONE
, DEEP, NF2),
104
/* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
105
PAD_CFG_NF
(
GPP_R1
,
NONE
, DEEP, NF2),
106
/* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX */
107
PAD_CFG_NF
(
GPP_R2
, DN_20K, DEEP, NF2),
108
/* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
109
PAD_CFG_NF
(
GPP_R3
,
NONE
, DEEP, NF2),
110
/* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */
111
PAD_CFG_NF
(
GPP_R5
,
NONE
, DEEP, NF2),
112
/* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */
113
PAD_CFG_NF
(
GPP_R6
,
NONE
, DEEP, NF2),
114
/* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */
115
PAD_CFG_NF
(
GPP_R7
,
NONE
, DEEP, NF2),
116
117
/* S6 : SNDW3_CLK ==> DMIC_CLK0 */
118
PAD_CFG_NF
(
GPP_S6
,
NONE
, DEEP, NF2),
119
/* S7 : SNDW3_DATA ==> DMIC_DATA0 */
120
PAD_CFG_NF
(
GPP_S7
,
NONE
, DEEP, NF2),
121
122
/* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
123
PAD_CFG_NF
(
GPD9
,
NONE
, DEEP, NF1),
124
};
125
126
/* Early pad configuration in bootblock */
127
static
const
struct
pad_config
early_gpio_table
[] = {
128
/* C8 : UART0 RX */
129
PAD_CFG_NF
(
GPP_C8
,
NONE
, DEEP, NF1),
130
/* C9 : UART0 TX */
131
PAD_CFG_NF
(
GPP_C9
,
NONE
, DEEP, NF1),
132
133
/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
134
PAD_CFG_NF
(
GPP_A12
,
NONE
, DEEP, NF1),
135
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
136
/* assert reset on reboot */
137
PAD_CFG_GPO
(
GPP_A13
, 0, DEEP),
138
/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
139
PAD_CFG_GPI
(
GPP_A17
,
NONE
, DEEP),
140
141
/* B2 : VRALERT# ==> EN_PP3300_SSD */
142
PAD_CFG_GPO
(
GPP_B2
, 1, PLTRST),
143
/* B11 : PMCALERT# ==> PCH_WP_OD */
144
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_B11
,
NONE
, DEEP),
145
/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
146
PAD_CFG_NF
(
GPP_B15
,
NONE
, DEEP, NF1),
147
/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
148
PAD_CFG_NF
(
GPP_B16
,
NONE
, DEEP, NF1),
149
/* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
150
PAD_CFG_NF
(
GPP_B17
,
NONE
, DEEP, NF1),
151
/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
152
PAD_CFG_NF
(
GPP_B18
,
NONE
, DEEP, NF1),
153
154
/* C0 : SMBCLK ==> EN_PP3300_WLAN */
155
PAD_CFG_GPO
(
GPP_C0
, 1, DEEP),
156
/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
157
PAD_CFG_GPI_APIC
(
GPP_C21
,
NONE
, PLTRST, LEVEL, INVERT),
158
159
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
160
PAD_CFG_GPO
(
GPP_D16
, 1, DEEP),
161
};
162
163
const
struct
pad_config
*
variant_override_gpio_table
(
size_t
*num)
164
{
165
*num =
ARRAY_SIZE
(
override_gpio_table
);
166
return
override_gpio_table
;
167
}
168
169
const
struct
pad_config
*
variant_early_gpio_table
(
size_t
*num)
170
{
171
*num =
ARRAY_SIZE
(
early_gpio_table
);
172
return
early_gpio_table
;
173
}
GPD9
#define GPD9
Definition:
gpio_soc_defs.h:390
GPP_D8
#define GPP_D8
Definition:
gpio_soc_defs.h:260
GPP_D17
#define GPP_D17
Definition:
gpio_soc_defs.h:269
GPP_E3
#define GPP_E3
Definition:
gpio_soc_defs.h:631
GPP_A18
#define GPP_A18
Definition:
gpio_soc_defs.h:137
GPP_F12
#define GPP_F12
Definition:
gpio_soc_defs.h:585
GPP_H16
#define GPP_H16
Definition:
gpio_soc_defs.h:232
GPP_R7
#define GPP_R7
Definition:
gpio_soc_defs.h:676
GPP_D14
#define GPP_D14
Definition:
gpio_soc_defs.h:266
GPP_H17
#define GPP_H17
Definition:
gpio_soc_defs.h:233
GPP_B16
#define GPP_B16
Definition:
gpio_soc_defs.h:69
GPP_B2
#define GPP_B2
Definition:
gpio_soc_defs.h:55
GPP_R3
#define GPP_R3
Definition:
gpio_soc_defs.h:672
GPP_A19
#define GPP_A19
Definition:
gpio_soc_defs.h:138
GPP_C9
#define GPP_C9
Definition:
gpio_soc_defs.h:546
GPP_R6
#define GPP_R6
Definition:
gpio_soc_defs.h:675
GPP_H9
#define GPP_H9
Definition:
gpio_soc_defs.h:225
GPP_R0
#define GPP_R0
Definition:
gpio_soc_defs.h:669
GPP_B15
#define GPP_B15
Definition:
gpio_soc_defs.h:68
GPP_H13
#define GPP_H13
Definition:
gpio_soc_defs.h:229
GPP_C8
#define GPP_C8
Definition:
gpio_soc_defs.h:545
GPP_S7
#define GPP_S7
Definition:
gpio_soc_defs.h:167
GPP_B22
#define GPP_B22
Definition:
gpio_soc_defs.h:75
GPP_A23
#define GPP_A23
Definition:
gpio_soc_defs.h:142
GPP_C18
#define GPP_C18
Definition:
gpio_soc_defs.h:555
GPP_C17
#define GPP_C17
Definition:
gpio_soc_defs.h:554
GPP_E8
#define GPP_E8
Definition:
gpio_soc_defs.h:636
GPP_A7
#define GPP_A7
Definition:
gpio_soc_defs.h:126
GPP_A20
#define GPP_A20
Definition:
gpio_soc_defs.h:139
GPP_A16
#define GPP_A16
Definition:
gpio_soc_defs.h:135
GPP_A12
#define GPP_A12
Definition:
gpio_soc_defs.h:131
GPP_C10
#define GPP_C10
Definition:
gpio_soc_defs.h:547
GPP_E7
#define GPP_E7
Definition:
gpio_soc_defs.h:635
GPP_C16
#define GPP_C16
Definition:
gpio_soc_defs.h:553
GPP_F13
#define GPP_F13
Definition:
gpio_soc_defs.h:586
GPP_S6
#define GPP_S6
Definition:
gpio_soc_defs.h:166
GPP_C21
#define GPP_C21
Definition:
gpio_soc_defs.h:558
GPP_R2
#define GPP_R2
Definition:
gpio_soc_defs.h:671
GPP_B9
#define GPP_B9
Definition:
gpio_soc_defs.h:62
GPP_E18
#define GPP_E18
Definition:
gpio_soc_defs.h:646
GPP_H3
#define GPP_H3
Definition:
gpio_soc_defs.h:219
GPP_A10
#define GPP_A10
Definition:
gpio_soc_defs.h:129
GPP_A8
#define GPP_A8
Definition:
gpio_soc_defs.h:127
GPP_B11
#define GPP_B11
Definition:
gpio_soc_defs.h:64
GPP_D13
#define GPP_D13
Definition:
gpio_soc_defs.h:265
GPP_B18
#define GPP_B18
Definition:
gpio_soc_defs.h:71
GPP_R5
#define GPP_R5
Definition:
gpio_soc_defs.h:674
GPP_E20
#define GPP_E20
Definition:
gpio_soc_defs.h:648
GPP_F8
#define GPP_F8
Definition:
gpio_soc_defs.h:581
GPP_C19
#define GPP_C19
Definition:
gpio_soc_defs.h:556
GPP_A13
#define GPP_A13
Definition:
gpio_soc_defs.h:132
GPP_E15
#define GPP_E15
Definition:
gpio_soc_defs.h:643
GPP_B10
#define GPP_B10
Definition:
gpio_soc_defs.h:63
GPP_E11
#define GPP_E11
Definition:
gpio_soc_defs.h:639
GPP_A22
#define GPP_A22
Definition:
gpio_soc_defs.h:141
GPP_D16
#define GPP_D16
Definition:
gpio_soc_defs.h:268
GPP_H10
#define GPP_H10
Definition:
gpio_soc_defs.h:226
GPP_A17
#define GPP_A17
Definition:
gpio_soc_defs.h:136
GPP_B17
#define GPP_B17
Definition:
gpio_soc_defs.h:70
GPP_E4
#define GPP_E4
Definition:
gpio_soc_defs.h:632
GPP_C0
#define GPP_C0
Definition:
gpio_soc_defs.h:537
GPP_H8
#define GPP_H8
Definition:
gpio_soc_defs.h:224
GPP_R1
#define GPP_R1
Definition:
gpio_soc_defs.h:670
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
helpers.h
variant_early_gpio_table
const struct pad_config * variant_early_gpio_table(size_t *num)
Definition:
gpio.c:204
variant_override_gpio_table
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
Definition:
gpio.c:450
override_gpio_table
static const struct pad_config override_gpio_table[]
Definition:
gpio.c:8
early_gpio_table
static const struct pad_config early_gpio_table[]
Definition:
gpio.c:127
NONE
@ NONE
Definition:
qup_se_handlers_common.h:196
PAD_NC
#define PAD_NC(pin)
Definition:
gpio_defs.h:263
PAD_CFG_GPI
#define PAD_CFG_GPI(pad, pull, rst)
Definition:
gpio_defs.h:284
PAD_CFG_NF
#define PAD_CFG_NF(pad, pull, rst, func)
Definition:
gpio_defs.h:197
PAD_CFG_GPI_INT
#define PAD_CFG_GPI_INT(pad, pull, rst, trig)
Definition:
gpio_defs.h:348
PAD_CFG_GPI_APIC
#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:376
PAD_CFG_GPO
#define PAD_CFG_GPO(pad, val, rst)
Definition:
gpio_defs.h:247
PAD_CFG_GPI_GPIO_DRIVER
#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst)
Definition:
gpio_defs.h:323
pad_config
Definition:
gpio.h:75
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gpio.c
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