coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Public Types | Data Fields
soc_intel_tigerlake_config Struct Reference

#include <chip.h>

Collaboration diagram for soc_intel_tigerlake_config:
Collaboration graph

Public Types

enum  {
  SaGv_Disabled , SaGv_FixedPoint0 , SaGv_FixedPoint1 , SaGv_FixedPoint2 ,
  SaGv_FixedPoint3 , SaGv_Enabled
}
 
enum  {
  DEBUG_INTERFACE_RAM = (1 << 0) , DEBUG_INTERFACE_UART_8250IO = (1 << 1) , DEBUG_INTERFACE_USB3 = (1 << 3) , DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4) ,
  DEBUG_INTERFACE_TRACEHUB = (1 << 5)
}
 

Data Fields

struct soc_intel_common_config common_soc_config
 
struct soc_power_limits_config power_limits_config [POWER_LIMITS_MAX]
 
uint8_t ConfigTdpLevel
 
uint8_t pmc_gpe0_dw0
 
uint8_t pmc_gpe0_dw1
 
uint8_t pmc_gpe0_dw2
 
uint32_t lpc_ioe
 
uint32_t gen1_dec
 
uint32_t gen2_dec
 
uint32_t gen3_dec
 
uint32_t gen4_dec
 
int s0ix_enable
 
enum lpm_state_mask LpmStateDisableMask
 
uint8_t TcssD3HotDisable
 
uint8_t TcssD3ColdDisable
 
int dptf_enable
 
int deep_s3_enable_ac
 
int deep_s3_enable_dc
 
int deep_s5_enable_ac
 
int deep_s5_enable_dc
 
uint32_t deep_sx_config
 
uint32_t tcc_offset
 
enum soc_intel_tigerlake_config:: { ... }  SaGv
 
uint8_t RMT
 
uint32_t CmdMirror
 
struct usb2_port_config usb2_ports [16]
 
struct usb3_port_config usb3_ports [10]
 
uint16_t usb2_wake_enable_bitmap
 
uint16_t usb3_wake_enable_bitmap
 
uint8_t usb2_phy_sus_pg_disable
 
struct tcss_port_config tcss_ports [MAX_TYPE_C_PORTS]
 
uint8_t AcousticNoiseMitigation
 
uint8_t FastPkgCRampDisable
 
uint8_t SlowSlewRate
 
uint8_t SataMode
 
uint8_t SataSalpSupport
 
uint8_t SataPortsEnable [8]
 
uint8_t SataPortsDevSlp [8]
 
uint8_t SataPwrOptimizeDisable
 
uint8_t SataPortsEnableDitoConfig [8]
 
uint8_t SataPortsDmVal [8]
 
uint16_t SataPortsDitoVal [8]
 
uint8_t PchHdaDspEnable
 
uint8_t PchHdaAudioLinkHdaEnable
 
uint8_t PchHdaAudioLinkDmicEnable [MAX_HD_AUDIO_DMIC_LINKS]
 
uint8_t PchHdaAudioLinkSspEnable [MAX_HD_AUDIO_SSP_LINKS]
 
uint8_t PchHdaAudioLinkSndwEnable [MAX_HD_AUDIO_SNDW_LINKS]
 
uint8_t PchHdaIDispCodecDisconnect
 
uint8_t PcieRpEnable [CONFIG_MAX_ROOT_PORTS]
 
uint8_t PcieRpHotPlug [CONFIG_MAX_ROOT_PORTS]
 
uint8_t PcieRpSlotImplemented [CONFIG_MAX_ROOT_PORTS]
 
uint8_t PcieClkSrcUsage [CONFIG_MAX_PCIE_CLOCK_SRC]
 
uint8_t PcieClkSrcClkReq [CONFIG_MAX_PCIE_CLOCK_SRC]
 
uint8_t PcieRpClkReqDetect [CONFIG_MAX_ROOT_PORTS]
 
uint8_t PciePtm [CONFIG_MAX_ROOT_PORTS]
 
enum L1_substates_control PcieRpL1Substates [CONFIG_MAX_ROOT_PORTS]
 
uint8_t PcieRpLtrEnable [CONFIG_MAX_ROOT_PORTS]
 
uint8_t PcieRpAdvancedErrorReporting [CONFIG_MAX_ROOT_PORTS]
 
uint8_t SkipExtGfxScan
 
uint8_t eist_enable
 
uint8_t enable_c6dram
 
uint8_t SerialIoI2cMode [CONFIG_SOC_INTEL_I2C_DEV_MAX]
 
uint8_t SerialIoGSpiMode [CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]
 
uint8_t SerialIoUartMode [CONFIG_SOC_INTEL_UART_DEV_MAX]
 
uint8_t SerialIoGSpiCsMode [CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]
 
uint8_t SerialIoGSpiCsState [CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]
 
uint8_t TraceHubMode
 
enum soc_intel_tigerlake_config:: { ... }  debug_interface_flag
 
bool CnviBtCore
 
bool CnviBtAudioOffload
 
uint8_t TcssXhciEn
 
uint8_t TcssXdciEn
 
uint8_t UsbTcPortEn
 
struct typec_aux_bias_pads typec_aux_bias_pads [MAX_TYPE_C_PORTS]
 
uint16_t TcssAuxOri
 
uint16_t ITbtConnectTopologyTimeoutInMs
 
uint8_t gpio_override_pm
 
uint8_t gpio_pm [TOTAL_GPIO_COMM]
 
uint8_t DdiPortAConfig
 
uint8_t DdiPortBConfig
 
uint8_t DdiPortAHpd
 
uint8_t DdiPortBHpd
 
uint8_t DdiPortCHpd
 
uint8_t DdiPort1Hpd
 
uint8_t DdiPort2Hpd
 
uint8_t DdiPort3Hpd
 
uint8_t DdiPort4Hpd
 
uint8_t DdiPortADdc
 
uint8_t DdiPortBDdc
 
uint8_t DdiPortCDdc
 
uint8_t DdiPort1Ddc
 
uint8_t DdiPort2Ddc
 
uint8_t DdiPort3Ddc
 
uint8_t DdiPort4Ddc
 
uint8_t HybridStorageMode
 
uint8_t cpu_ratio_override
 
uint8_t HyperThreadingDisable
 
uint8_t DmiPwrOptimizeDisable
 
struct {
   bool   configure_ext_fivr
 
   enum fivr_enable_states   v1p05_enable_bitmap
 
   enum fivr_enable_states   vnn_enable_bitmap
 
   enum fivr_voltage_supported   v1p05_supported_voltage_bitmap
 
   enum fivr_voltage_supported   vnn_supported_voltage_bitmap
 
   int   v1p05_icc_max_ma
 
   int   vnn_sx_voltage_mv
 
} ext_fivr_settings
 
uint8_t CpuReplacementCheck
 
uint8_t PchPmSlpS3MinAssert
 
uint8_t PchPmSlpS4MinAssert
 
uint8_t PchPmSlpSusMinAssert
 
uint8_t PchPmSlpAMinAssert
 
uint8_t PchPmPwrCycDur
 
bool external_clk_gated
 
bool external_phy_gated
 
bool external_bypass
 
struct i915_gpu_controller_info gfx
 

Detailed Description

Definition at line 95 of file chip.h.

Member Enumeration Documentation

◆ anonymous enum

anonymous enum
Enumerator
SaGv_Disabled 
SaGv_FixedPoint0 
SaGv_FixedPoint1 
SaGv_FixedPoint2 
SaGv_FixedPoint3 
SaGv_Enabled 

Definition at line 153 of file chip.h.

◆ anonymous enum

anonymous enum
Enumerator
DEBUG_INTERFACE_RAM 
DEBUG_INTERFACE_UART_8250IO 
DEBUG_INTERFACE_USB3 
DEBUG_INTERFACE_LPSS_SERIAL_IO 
DEBUG_INTERFACE_TRACEHUB 

Definition at line 304 of file chip.h.

Field Documentation

◆ AcousticNoiseMitigation

uint8_t soc_intel_tigerlake_config::AcousticNoiseMitigation

Definition at line 185 of file chip.h.

◆ CmdMirror

uint32_t soc_intel_tigerlake_config::CmdMirror

Definition at line 166 of file chip.h.

◆ CnviBtAudioOffload

bool soc_intel_tigerlake_config::CnviBtAudioOffload

Definition at line 316 of file chip.h.

◆ CnviBtCore

bool soc_intel_tigerlake_config::CnviBtCore

Definition at line 313 of file chip.h.

◆ common_soc_config

struct soc_intel_common_config soc_intel_tigerlake_config::common_soc_config

Definition at line 1 of file chip.h.

◆ ConfigTdpLevel

uint8_t soc_intel_tigerlake_config::ConfigTdpLevel

Definition at line 104 of file chip.h.

◆ configure_ext_fivr

bool soc_intel_tigerlake_config::configure_ext_fivr

Definition at line 423 of file chip.h.

◆ cpu_ratio_override

uint8_t soc_intel_tigerlake_config::cpu_ratio_override

Definition at line 410 of file chip.h.

◆ CpuReplacementCheck

uint8_t soc_intel_tigerlake_config::CpuReplacementCheck

Definition at line 438 of file chip.h.

◆ DdiPort1Ddc

uint8_t soc_intel_tigerlake_config::DdiPort1Ddc

Definition at line 391 of file chip.h.

◆ DdiPort1Hpd

uint8_t soc_intel_tigerlake_config::DdiPort1Hpd

Definition at line 382 of file chip.h.

◆ DdiPort2Ddc

uint8_t soc_intel_tigerlake_config::DdiPort2Ddc

Definition at line 392 of file chip.h.

◆ DdiPort2Hpd

uint8_t soc_intel_tigerlake_config::DdiPort2Hpd

Definition at line 383 of file chip.h.

◆ DdiPort3Ddc

uint8_t soc_intel_tigerlake_config::DdiPort3Ddc

Definition at line 393 of file chip.h.

◆ DdiPort3Hpd

uint8_t soc_intel_tigerlake_config::DdiPort3Hpd

Definition at line 384 of file chip.h.

◆ DdiPort4Ddc

uint8_t soc_intel_tigerlake_config::DdiPort4Ddc

Definition at line 394 of file chip.h.

◆ DdiPort4Hpd

uint8_t soc_intel_tigerlake_config::DdiPort4Hpd

Definition at line 385 of file chip.h.

◆ DdiPortAConfig

uint8_t soc_intel_tigerlake_config::DdiPortAConfig

Definition at line 375 of file chip.h.

◆ DdiPortADdc

uint8_t soc_intel_tigerlake_config::DdiPortADdc

Definition at line 388 of file chip.h.

◆ DdiPortAHpd

uint8_t soc_intel_tigerlake_config::DdiPortAHpd

Definition at line 379 of file chip.h.

◆ DdiPortBConfig

uint8_t soc_intel_tigerlake_config::DdiPortBConfig

Definition at line 376 of file chip.h.

◆ DdiPortBDdc

uint8_t soc_intel_tigerlake_config::DdiPortBDdc

Definition at line 389 of file chip.h.

◆ DdiPortBHpd

uint8_t soc_intel_tigerlake_config::DdiPortBHpd

Definition at line 380 of file chip.h.

◆ DdiPortCDdc

uint8_t soc_intel_tigerlake_config::DdiPortCDdc

Definition at line 390 of file chip.h.

◆ DdiPortCHpd

uint8_t soc_intel_tigerlake_config::DdiPortCHpd

Definition at line 381 of file chip.h.

◆ 

enum { ... } soc_intel_tigerlake_config::debug_interface_flag

◆ deep_s3_enable_ac

int soc_intel_tigerlake_config::deep_s3_enable_ac

Definition at line 135 of file chip.h.

◆ deep_s3_enable_dc

int soc_intel_tigerlake_config::deep_s3_enable_dc

Definition at line 136 of file chip.h.

◆ deep_s5_enable_ac

int soc_intel_tigerlake_config::deep_s5_enable_ac

Definition at line 137 of file chip.h.

◆ deep_s5_enable_dc

int soc_intel_tigerlake_config::deep_s5_enable_dc

Definition at line 138 of file chip.h.

◆ deep_sx_config

uint32_t soc_intel_tigerlake_config::deep_sx_config

Definition at line 144 of file chip.h.

◆ DmiPwrOptimizeDisable

uint8_t soc_intel_tigerlake_config::DmiPwrOptimizeDisable

Definition at line 419 of file chip.h.

◆ dptf_enable

int soc_intel_tigerlake_config::dptf_enable

Definition at line 132 of file chip.h.

◆ eist_enable

uint8_t soc_intel_tigerlake_config::eist_enable

Definition at line 268 of file chip.h.

◆ enable_c6dram

uint8_t soc_intel_tigerlake_config::enable_c6dram

Definition at line 271 of file chip.h.

◆ 

struct { ... } soc_intel_tigerlake_config::ext_fivr_settings

◆ external_bypass

bool soc_intel_tigerlake_config::external_bypass

Definition at line 515 of file chip.h.

◆ external_clk_gated

bool soc_intel_tigerlake_config::external_clk_gated

Definition at line 499 of file chip.h.

◆ external_phy_gated

bool soc_intel_tigerlake_config::external_phy_gated

Definition at line 507 of file chip.h.

◆ FastPkgCRampDisable

uint8_t soc_intel_tigerlake_config::FastPkgCRampDisable

Definition at line 195 of file chip.h.

◆ gen1_dec

uint32_t soc_intel_tigerlake_config::gen1_dec

Definition at line 116 of file chip.h.

◆ gen2_dec

uint32_t soc_intel_tigerlake_config::gen2_dec

Definition at line 117 of file chip.h.

◆ gen3_dec

uint32_t soc_intel_tigerlake_config::gen3_dec

Definition at line 118 of file chip.h.

◆ gen4_dec

uint32_t soc_intel_tigerlake_config::gen4_dec

Definition at line 119 of file chip.h.

◆ gfx

struct i915_gpu_controller_info soc_intel_tigerlake_config::gfx

Definition at line 515 of file chip.h.

◆ gpio_override_pm

uint8_t soc_intel_tigerlake_config::gpio_override_pm

Definition at line 356 of file chip.h.

Referenced by mainboard_update_soc_chip_config().

◆ gpio_pm

uint8_t soc_intel_tigerlake_config::gpio_pm[TOTAL_GPIO_COMM]

Definition at line 368 of file chip.h.

Referenced by mainboard_update_soc_chip_config().

◆ HybridStorageMode

uint8_t soc_intel_tigerlake_config::HybridStorageMode

Definition at line 399 of file chip.h.

◆ HyperThreadingDisable

uint8_t soc_intel_tigerlake_config::HyperThreadingDisable

Definition at line 413 of file chip.h.

◆ ITbtConnectTopologyTimeoutInMs

uint16_t soc_intel_tigerlake_config::ITbtConnectTopologyTimeoutInMs

Definition at line 349 of file chip.h.

◆ lpc_ioe

uint32_t soc_intel_tigerlake_config::lpc_ioe

Definition at line 113 of file chip.h.

◆ LpmStateDisableMask

enum lpm_state_mask soc_intel_tigerlake_config::LpmStateDisableMask

Definition at line 122 of file chip.h.

Referenced by mainboard_update_soc_chip_config().

◆ PchHdaAudioLinkDmicEnable

uint8_t soc_intel_tigerlake_config::PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]

Definition at line 231 of file chip.h.

◆ PchHdaAudioLinkHdaEnable

uint8_t soc_intel_tigerlake_config::PchHdaAudioLinkHdaEnable

Definition at line 230 of file chip.h.

◆ PchHdaAudioLinkSndwEnable

uint8_t soc_intel_tigerlake_config::PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]

Definition at line 233 of file chip.h.

◆ PchHdaAudioLinkSspEnable

uint8_t soc_intel_tigerlake_config::PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]

Definition at line 232 of file chip.h.

◆ PchHdaDspEnable

uint8_t soc_intel_tigerlake_config::PchHdaDspEnable

Definition at line 229 of file chip.h.

◆ PchHdaIDispCodecDisconnect

uint8_t soc_intel_tigerlake_config::PchHdaIDispCodecDisconnect

Definition at line 234 of file chip.h.

◆ PchPmPwrCycDur

uint8_t soc_intel_tigerlake_config::PchPmPwrCycDur

Definition at line 491 of file chip.h.

◆ PchPmSlpAMinAssert

uint8_t soc_intel_tigerlake_config::PchPmSlpAMinAssert

Definition at line 474 of file chip.h.

◆ PchPmSlpS3MinAssert

uint8_t soc_intel_tigerlake_config::PchPmSlpS3MinAssert

Definition at line 447 of file chip.h.

◆ PchPmSlpS4MinAssert

uint8_t soc_intel_tigerlake_config::PchPmSlpS4MinAssert

Definition at line 456 of file chip.h.

◆ PchPmSlpSusMinAssert

uint8_t soc_intel_tigerlake_config::PchPmSlpSusMinAssert

Definition at line 465 of file chip.h.

◆ PcieClkSrcClkReq

uint8_t soc_intel_tigerlake_config::PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC]

Definition at line 247 of file chip.h.

◆ PcieClkSrcUsage

uint8_t soc_intel_tigerlake_config::PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]

Definition at line 244 of file chip.h.

◆ PciePtm

uint8_t soc_intel_tigerlake_config::PciePtm[CONFIG_MAX_ROOT_PORTS]

Definition at line 253 of file chip.h.

◆ PcieRpAdvancedErrorReporting

uint8_t soc_intel_tigerlake_config::PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]

Definition at line 262 of file chip.h.

◆ PcieRpClkReqDetect

uint8_t soc_intel_tigerlake_config::PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]

Definition at line 250 of file chip.h.

◆ PcieRpEnable

uint8_t soc_intel_tigerlake_config::PcieRpEnable[CONFIG_MAX_ROOT_PORTS]

Definition at line 237 of file chip.h.

◆ PcieRpHotPlug

uint8_t soc_intel_tigerlake_config::PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]

Definition at line 238 of file chip.h.

◆ PcieRpL1Substates

enum L1_substates_control soc_intel_tigerlake_config::PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]

Definition at line 253 of file chip.h.

◆ PcieRpLtrEnable

uint8_t soc_intel_tigerlake_config::PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]

Definition at line 259 of file chip.h.

◆ PcieRpSlotImplemented

uint8_t soc_intel_tigerlake_config::PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS]

Definition at line 240 of file chip.h.

◆ pmc_gpe0_dw0

uint8_t soc_intel_tigerlake_config::pmc_gpe0_dw0

Definition at line 108 of file chip.h.

◆ pmc_gpe0_dw1

uint8_t soc_intel_tigerlake_config::pmc_gpe0_dw1

Definition at line 109 of file chip.h.

◆ pmc_gpe0_dw2

uint8_t soc_intel_tigerlake_config::pmc_gpe0_dw2

Definition at line 110 of file chip.h.

◆ power_limits_config

struct soc_power_limits_config soc_intel_tigerlake_config::power_limits_config[POWER_LIMITS_MAX]

Definition at line 1 of file chip.h.

◆ RMT

uint8_t soc_intel_tigerlake_config::RMT

Definition at line 163 of file chip.h.

◆ s0ix_enable

int soc_intel_tigerlake_config::s0ix_enable

Definition at line 122 of file chip.h.

◆ 

enum { ... } soc_intel_tigerlake_config::SaGv

◆ SataMode

uint8_t soc_intel_tigerlake_config::SataMode

Definition at line 206 of file chip.h.

◆ SataPortsDevSlp

uint8_t soc_intel_tigerlake_config::SataPortsDevSlp[8]

Definition at line 209 of file chip.h.

◆ SataPortsDitoVal

uint16_t soc_intel_tigerlake_config::SataPortsDitoVal[8]

Definition at line 226 of file chip.h.

◆ SataPortsDmVal

uint8_t soc_intel_tigerlake_config::SataPortsDmVal[8]

Definition at line 224 of file chip.h.

◆ SataPortsEnable

uint8_t soc_intel_tigerlake_config::SataPortsEnable[8]

Definition at line 208 of file chip.h.

◆ SataPortsEnableDitoConfig

uint8_t soc_intel_tigerlake_config::SataPortsEnableDitoConfig[8]

Definition at line 221 of file chip.h.

◆ SataPwrOptimizeDisable

uint8_t soc_intel_tigerlake_config::SataPwrOptimizeDisable

Definition at line 215 of file chip.h.

◆ SataSalpSupport

uint8_t soc_intel_tigerlake_config::SataSalpSupport

Definition at line 207 of file chip.h.

◆ SerialIoGSpiCsMode

uint8_t soc_intel_tigerlake_config::SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]

Definition at line 289 of file chip.h.

◆ SerialIoGSpiCsState

uint8_t soc_intel_tigerlake_config::SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]

Definition at line 295 of file chip.h.

◆ SerialIoGSpiMode

uint8_t soc_intel_tigerlake_config::SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]

Definition at line 282 of file chip.h.

◆ SerialIoI2cMode

uint8_t soc_intel_tigerlake_config::SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]

Definition at line 281 of file chip.h.

◆ SerialIoUartMode

uint8_t soc_intel_tigerlake_config::SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]

Definition at line 283 of file chip.h.

◆ SkipExtGfxScan

uint8_t soc_intel_tigerlake_config::SkipExtGfxScan

Definition at line 265 of file chip.h.

◆ SlowSlewRate

uint8_t soc_intel_tigerlake_config::SlowSlewRate

Definition at line 203 of file chip.h.

◆ tcc_offset

uint32_t soc_intel_tigerlake_config::tcc_offset

Definition at line 147 of file chip.h.

◆ tcss_ports

struct tcss_port_config soc_intel_tigerlake_config::tcss_ports[MAX_TYPE_C_PORTS]

Definition at line 176 of file chip.h.

◆ TcssAuxOri

uint16_t soc_intel_tigerlake_config::TcssAuxOri

Definition at line 346 of file chip.h.

◆ TcssD3ColdDisable

uint8_t soc_intel_tigerlake_config::TcssD3ColdDisable

Definition at line 129 of file chip.h.

◆ TcssD3HotDisable

uint8_t soc_intel_tigerlake_config::TcssD3HotDisable

Definition at line 127 of file chip.h.

◆ TcssXdciEn

uint8_t soc_intel_tigerlake_config::TcssXdciEn

Definition at line 320 of file chip.h.

◆ TcssXhciEn

uint8_t soc_intel_tigerlake_config::TcssXhciEn

Definition at line 319 of file chip.h.

◆ TraceHubMode

uint8_t soc_intel_tigerlake_config::TraceHubMode

Definition at line 301 of file chip.h.

◆ typec_aux_bias_pads

struct typec_aux_bias_pads soc_intel_tigerlake_config::typec_aux_bias_pads[MAX_TYPE_C_PORTS]

Definition at line 327 of file chip.h.

◆ usb2_phy_sus_pg_disable

uint8_t soc_intel_tigerlake_config::usb2_phy_sus_pg_disable

Definition at line 176 of file chip.h.

◆ usb2_ports

struct usb2_port_config soc_intel_tigerlake_config::usb2_ports[16]

Definition at line 166 of file chip.h.

◆ usb2_wake_enable_bitmap

uint16_t soc_intel_tigerlake_config::usb2_wake_enable_bitmap

Definition at line 172 of file chip.h.

◆ usb3_ports

struct usb3_port_config soc_intel_tigerlake_config::usb3_ports[10]

Definition at line 166 of file chip.h.

◆ usb3_wake_enable_bitmap

uint16_t soc_intel_tigerlake_config::usb3_wake_enable_bitmap

Definition at line 174 of file chip.h.

◆ UsbTcPortEn

uint8_t soc_intel_tigerlake_config::UsbTcPortEn

Definition at line 327 of file chip.h.

◆ v1p05_enable_bitmap

enum fivr_enable_states soc_intel_tigerlake_config::v1p05_enable_bitmap

Definition at line 423 of file chip.h.

◆ v1p05_icc_max_ma

int soc_intel_tigerlake_config::v1p05_icc_max_ma

Definition at line 429 of file chip.h.

◆ v1p05_supported_voltage_bitmap

enum fivr_voltage_supported soc_intel_tigerlake_config::v1p05_supported_voltage_bitmap

Definition at line 423 of file chip.h.

◆ vnn_enable_bitmap

enum fivr_enable_states soc_intel_tigerlake_config::vnn_enable_bitmap

Definition at line 423 of file chip.h.

◆ vnn_supported_voltage_bitmap

enum fivr_voltage_supported soc_intel_tigerlake_config::vnn_supported_voltage_bitmap

Definition at line 423 of file chip.h.

◆ vnn_sx_voltage_mv

int soc_intel_tigerlake_config::vnn_sx_voltage_mv

Definition at line 431 of file chip.h.

The documentation for this struct was generated from the following file: