chip.h File Reference

#include <drivers/i2c/designware/dw_i2c.h>
#include <device/pci_ids.h>
#include <intelblocks/cfg.h>
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
#include <intelblocks/power_limit.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/tcss.h>
#include <soc/gpe.h>
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <soc/serialio.h>
#include <soc/usb.h>
#include <soc/vr_config.h>
#include <stdint.h>

Include dependency graph for chip.h:

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures
struct	soc_intel_alderlake_config

Macros
#define	FIVR_ENABLE_ALL_SX

Typedefs
typedef struct soc_intel_alderlake_config	config_t

Enumerations
enum	soc_intel_alderlake_power_limits {   ADL_P_142_242_282_15W_CORE , ADL_P_282_482_28W_CORE , ADL_P_682_28W_CORE , ADL_P_442_482_45W_CORE ,   ADL_P_642_682_45W_CORE , ADL_M_282_12W_CORE , ADL_M_282_15W_CORE , ADL_M_242_CORE ,   ADL_P_442_45W_CORE , ADL_POWER_LIMITS_COUNT }
enum	soc_intel_alderlake_cpu_tdps {   TDP_9W = 9 , TDP_12W = 12 , TDP_15W = 15 , TDP_28W = 28 ,   TDP_45W = 45 }
enum	ddi_ports {   DDI_PORT_A , DDI_PORT_B , DDI_PORT_C , DDI_PORT_1 ,   DDI_PORT_2 , DDI_PORT_3 , DDI_PORT_4 , DDI_PORT_COUNT }
enum	ddi_port_flags { DDI_ENABLE_DDC = 1 << 0 , DDI_ENABLE_HPD = 1 << 1 }
enum	fivr_enable_states {   FIVR_ENABLE_S0i1_S0i2 = BIT(0) , FIVR_ENABLE_S0i3 = BIT(1) , FIVR_ENABLE_S3 = BIT(2) , FIVR_ENABLE_S4 = BIT(3) ,   FIVR_ENABLE_S5 = BIT(4) , FIVR_ENABLE_S0i1_S0i2 = BIT(0) , FIVR_ENABLE_S0i3 = BIT(1) , FIVR_ENABLE_S3 = BIT(2) ,   FIVR_ENABLE_S4 = BIT(3) , FIVR_ENABLE_S5 = BIT(4) }
enum	fivr_voltage_supported {   FIVR_RET_ACTIVE_SWITCH_SUPPORT = BIT(0) , FIVR_VOLTAGE_NORMAL = BIT(1) , FIVR_VOLTAGE_MIN_ACTIVE = BIT(2) , FIVR_VOLTAGE_MIN_RETENTION = BIT(3) ,   FIVR_VOLTAGE_NORMAL = BIT(1) , FIVR_VOLTAGE_MIN_ACTIVE = BIT(2) , FIVR_VOLTAGE_MIN_RETENTION = BIT(3) }
enum	pkgcstate_limit {   LIMIT_C0_C1 = 0 , LIMIT_C2 = 1 , LIMIT_C3 = 2 , LIMIT_C6 = 3 ,   LIMIT_C7 = 4 , LIMIT_C7S = 5 , LIMIT_C8 = 6 , LIMIT_C9 = 7 ,   LIMIT_C10 = 8 , LIMIT_CPUDEFAULT = 254 , LIMIT_AUTO = 255 }
enum	lpm_state_mask {   LPM_S0i2_0 = BIT(0) , LPM_S0i2_1 = BIT(1) , LPM_S0i2_2 = BIT(2) , LPM_S0i3_0 = BIT(3) ,   LPM_S0i3_1 = BIT(4) , LPM_S0i3_2 = BIT(5) , LPM_S0i3_3 = BIT(6) , LPM_S0i3_4 = BIT(7) ,   LPM_S0iX_ALL , LPM_S0i2_0 = BIT(0) , LPM_S0i2_1 = BIT(1) , LPM_S0i2_2 = BIT(2) ,   LPM_S0i3_0 = BIT(3) , LPM_S0i3_1 = BIT(4) , LPM_S0i3_2 = BIT(5) , LPM_S0i3_3 = BIT(6) ,   LPM_S0i3_4 = BIT(7) , LPM_S0iX_ALL }
enum	fivr_spread_spectrum_ratio {   FIVR_SS_0_5 = 0 , FIVR_SS_1 = 3 , FIVR_SS_1_5 = 8 , FIVR_SS_2 = 18 ,   FIVR_SS_3 = 28 , FIVR_SS_4 = 34 , FIVR_SS_5 = 39 , FIVR_SS_6 = 44 }
enum	slew_rate {   SLEW_FAST_2 , SLEW_FAST_4 , SLEW_FAST_8 , SLEW_FAST_16 ,   SLEW_FAST_2 , SLEW_FAST_4 , SLEW_FAST_8 , SLEW_FAST_16 }

Variables
struct {
unsigned int   cpu_id
enum soc_intel_alderlake_power_limits   limits
enum soc_intel_alderlake_cpu_tdps   cpu_tdp
}	cpuid_to_adl []

Macro Definition Documentation

FIVR_ENABLE_ALL_SX

#define FIVR_ENABLE_ALL_SX

Value:

                            (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 | \
                            FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5)

Definition at line 109 of file chip.h.

Typedef Documentation

config_t

typedef struct soc_intel_alderlake_config config_t

Definition at line 1 of file chip.h.

Enumeration Type Documentation

ddi_port_flags

enum ddi_port_flags

Enumerator
DDI_ENABLE_DDC
DDI_ENABLE_HPD

Definition at line 78 of file chip.h.

ddi_ports

enum ddi_ports

Enumerator
DDI_PORT_A
DDI_PORT_B
DDI_PORT_C
DDI_PORT_1
DDI_PORT_2
DDI_PORT_3
DDI_PORT_4
DDI_PORT_COUNT

Definition at line 67 of file chip.h.

fivr_enable_states

enum fivr_enable_states

Enumerator
FIVR_ENABLE_S0i1_S0i2
FIVR_ENABLE_S0i3
FIVR_ENABLE_S3
FIVR_ENABLE_S4
FIVR_ENABLE_S5
FIVR_ENABLE_S0i1_S0i2
FIVR_ENABLE_S0i3
FIVR_ENABLE_S3
FIVR_ENABLE_S4
FIVR_ENABLE_S5

Definition at line 87 of file chip.h.

fivr_spread_spectrum_ratio

enum fivr_spread_spectrum_ratio

Enumerator
FIVR_SS_0_5
FIVR_SS_1
FIVR_SS_1_5
FIVR_SS_2
FIVR_SS_3
FIVR_SS_4
FIVR_SS_5
FIVR_SS_6

Definition at line 149 of file chip.h.

fivr_voltage_supported

enum fivr_voltage_supported

Enumerator
FIVR_RET_ACTIVE_SWITCH_SUPPORT
FIVR_VOLTAGE_NORMAL
FIVR_VOLTAGE_MIN_ACTIVE
FIVR_VOLTAGE_MIN_RETENTION
FIVR_VOLTAGE_NORMAL
FIVR_VOLTAGE_MIN_ACTIVE
FIVR_VOLTAGE_MIN_RETENTION

Definition at line 102 of file chip.h.

lpm_state_mask

enum lpm_state_mask

Enumerator
LPM_S0i2_0
LPM_S0i2_1
LPM_S0i2_2
LPM_S0i3_0
LPM_S0i3_1
LPM_S0i3_2
LPM_S0i3_3
LPM_S0i3_4
LPM_S0iX_ALL
LPM_S0i2_0
LPM_S0i2_1
LPM_S0i2_2
LPM_S0i3_0
LPM_S0i3_1
LPM_S0i3_2
LPM_S0i3_3
LPM_S0i3_4
LPM_S0iX_ALL

Definition at line 131 of file chip.h.

pkgcstate_limit

enum pkgcstate_limit

Enumerator
LIMIT_C0_C1
LIMIT_C2
LIMIT_C3
LIMIT_C6
LIMIT_C7
LIMIT_C7S
LIMIT_C8
LIMIT_C9
LIMIT_C10
LIMIT_CPUDEFAULT
LIMIT_AUTO

Definition at line 116 of file chip.h.

slew_rate

enum slew_rate

Enumerator
SLEW_FAST_2
SLEW_FAST_4
SLEW_FAST_8
SLEW_FAST_16
SLEW_FAST_2
SLEW_FAST_4
SLEW_FAST_8
SLEW_FAST_16

Definition at line 168 of file chip.h.

soc_intel_alderlake_cpu_tdps

enum soc_intel_alderlake_cpu_tdps

Enumerator
TDP_9W
TDP_12W
TDP_15W
TDP_28W
TDP_45W

Definition at line 37 of file chip.h.

soc_intel_alderlake_power_limits

enum soc_intel_alderlake_power_limits

Enumerator
ADL_P_142_242_282_15W_CORE
ADL_P_282_482_28W_CORE
ADL_P_682_28W_CORE
ADL_P_442_482_45W_CORE
ADL_P_642_682_45W_CORE
ADL_M_282_12W_CORE
ADL_M_282_15W_CORE
ADL_M_242_CORE
ADL_P_442_45W_CORE
ADL_POWER_LIMITS_COUNT

Definition at line 23 of file chip.h.

Variable Documentation

cpu_id

unsigned int cpu_id

Definition at line 47 of file chip.h.

Referenced by camera_fill_cio2(), core_start_execution(), generate_cpu_entries(), get_sku_index(), model_206ax_report(), platform_fsp_silicon_init_params_cb(), platform_is_up3(), report_cpu_info(), soc_memory_init_params(), soc_systemagent_init(), speedstep_get_limits(), and wilco_ec_set_cpuid().

cpu_tdp

enum soc_intel_alderlake_cpu_tdps cpu_tdp

Definition at line 47 of file chip.h.

Referenced by get_cpu_tdp(), get_sku_index(), soc_systemagent_init(), and variant_update_power_limits().

const { ... } cpuid_to_adl[]

Initial value:

= {
        { PCI_DID_INTEL_ADL_P_ID_10, ADL_P_142_242_282_15W_CORE, TDP_15W },
        { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_142_242_282_15W_CORE, TDP_15W },
        { PCI_DID_INTEL_ADL_P_ID_6, ADL_P_142_242_282_15W_CORE, TDP_15W },
        { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_282_482_28W_CORE, TDP_28W },
        { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_282_482_28W_CORE, TDP_28W },
        { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W },
        { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_442_482_45W_CORE, TDP_45W },
        { PCI_DID_INTEL_ADL_P_ID_4, ADL_P_642_682_45W_CORE, TDP_45W },
        { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_642_682_45W_CORE, TDP_45W },
        { PCI_DID_INTEL_ADL_P_ID_1, ADL_P_442_482_45W_CORE, TDP_45W },
        { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W },
        { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W },
        { PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W },
}

Referenced by get_sku_index(), and soc_systemagent_init().

limits

enum soc_intel_alderlake_power_limits limits

Definition at line 47 of file chip.h.