coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ec.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <acpi/acpi.h>
4 #include <arch/io.h>
5 #include <console/console.h>
6 #include <ec/ec.h>
8 #include <intelblocks/lpc_lib.h>
9 #include <variant/ec.h>
10 
11 static void ramstage_ec_init(void)
12 {
13  const struct google_chromeec_event_info info = {
14  .log_events = MAINBOARD_EC_LOG_EVENTS,
15  .sci_events = MAINBOARD_EC_SCI_EVENTS,
16  .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
17  .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
18  .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
19  };
20 
21  printk(BIOS_ERR, "mainboard: EC init\n");
22 
24 }
25 
26 static void bootblock_ec_init(void)
27 {
28  uint16_t ec_ioport_base;
29  size_t ec_ioport_size;
30 
31  /*
32  * Set up LPC decoding for the ChromeEC I/O port ranges:
33  * - Ports 62/66, 60/64, and 200->208
34  * - ChromeEC specific communication I/O ports.
35  */
37  | LPC_IOE_LGE_200);
38  google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
39  lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
40 }
41 
43 {
44  if (CONFIG(EC_GOOGLE_CHROMEEC)) {
45  if (ENV_RAMSTAGE)
47  else if (ENV_BOOTBLOCK)
49  } else if (ENV_BOOTBLOCK) {
50  /*
51  * Set up LPC decoding for the ChromeEC I/O port ranges:
52  * - Ports 62/66, 60/64, and 200->208
53  * - ChromeEC specific communication I/O ports.
54  */
56  | LPC_IOE_LGE_200);
57  }
58 
59  if (CONFIG(GLK_INTEL_EC)) {
60  printk(BIOS_ERR, "S3 Hack Enable ACPI mode: outb(0xaa,0x66)\n");
61  outb(0xaa, 0x66);
62  printk(BIOS_INFO, "Hack to turn on the CPU fan\n");
63  outb(0x81, 0x66);
64  outb(0x44, 0x62);
65  outb(0x32, 0x62);
66  /* Need delay here, hence second outb */
67  outb(0x32, 0x62);
68  outb(0x1a, 0x66);
69  }
70 }
static int acpi_is_wakeup_s3(void)
Definition: acpi.h:9
#define printk(level,...)
Definition: stdlib.h:16
void outb(u8 val, u16 port)
static struct smmstore_params_info info
Definition: ramstage.c:12
@ CONFIG
Definition: dsi_common.h:201
void google_chromeec_events_init(const struct google_chromeec_event_info *info, bool is_s3_wakeup)
Definition: ec.c:410
void google_chromeec_ioport_range(uint16_t *base, size_t *size)
Definition: ec_lpc.c:364
#define BIOS_INFO
BIOS_INFO - Expected events.
Definition: loglevel.h:113
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
Definition: loglevel.h:72
#define LPC_IOE_EC_62_66
Definition: lpc_lib.h:18
#define LPC_IOE_LGE_200
Definition: lpc_lib.h:21
#define LPC_IOE_KBC_60_64
Definition: lpc_lib.h:19
uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables)
Definition: lpc_lib.c:21
void lpc_open_pmio_window(uint16_t base, uint16_t size)
Definition: lpc_lib.c:71
void mainboard_ec_init(void)
Definition: ec.c:8
#define MAINBOARD_EC_S5_WAKE_EVENTS
Definition: ec.h:32
#define MAINBOARD_EC_SCI_EVENTS
Definition: ec.h:12
#define MAINBOARD_EC_LOG_EVENTS
Definition: ec.h:42
#define MAINBOARD_EC_S3_WAKE_EVENTS
Definition: ec.h:37
#define MAINBOARD_EC_S0IX_WAKE_EVENTS
Definition: ec.h:25
static void ramstage_ec_init(void)
Definition: ec.c:11
static void bootblock_ec_init(void)
Definition: ec.c:26
#define ENV_BOOTBLOCK
Definition: rules.h:148
#define ENV_RAMSTAGE
Definition: rules.h:150
unsigned short uint16_t
Definition: stdint.h:11