coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_southbridge.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <bootblock_common.h>
4 #include <stdint.h>
5 #include <cf9_reset.h>
8 
9 #include "superio.h"
10 #include "thermal.h"
11 
12 static const u16 hwm_initvals[] = {
13  HWM_BANK(0),
14  HWM_INITVAL(0xae, 0x01), /* Enable PECI Agent0 */
15 
16  HWM_BANK(7), /* PECI */
17  HWM_INITVAL(0x01, 0x95), /* Enable PECI */
18  HWM_INITVAL(0x03, 0x10), /* Enable Agent 0 */
19  /*
20  * PECI temperatures are negative, going up to 0.
21  * 0 represents the maximum allowable junction temperature, Tjmax.
22  * There is also Tcontrol, which is the temperature at which the
23  * system cooling should run at full speed.
24  * Since the NCT5577D fan control only supports positive values,
25  * Tbase0 is used as an offset.
26  */
27  HWM_INITVAL(0x09, CRITICAL_TEMPERATURE), /* Tbase0 */
28 
29  HWM_BANK(2), /* CPUFAN control */
30  HWM_INITVAL(0x00, 0x0c), /* PECI Agent 0 as CPUFAN monitoring source */
31  HWM_INITVAL(0x01, 50), /* Target temperature */
32  HWM_INITVAL(0x02, 0x40), /* Enable Smart Fan IV mode */
33  HWM_INITVAL(0x03, 0x01), /* Step-up time */
34  HWM_INITVAL(0x04, 0x01), /* Step-down time */
35  HWM_INITVAL(0x05, 0x10), /* Stop PWM value */
36  HWM_INITVAL(0x06, 0x20), /* Start PWM value */
37  HWM_INITVAL(0x21, 45), /* Smart Fan IV Temp1 */
38  HWM_INITVAL(0x22, 46), /* Smart Fan IV Temp2 */
39  HWM_INITVAL(0x23, 47), /* Smart Fan IV Temp3 */
40  HWM_INITVAL(0x24, PASSIVE_TEMPERATURE), /* Smart Fan IV Temp4 */
41  HWM_INITVAL(0x27, 0x01), /* Smart Fan IV PWM1 */
42  HWM_INITVAL(0x28, 0x02), /* Smart Fan IV PWM2 */
43  HWM_INITVAL(0x29, 0x03), /* Smart Fan IV PWM3 */
44  HWM_INITVAL(0x2a, 0xff), /* Smart Fan IV PWM4 */
45  /* Smart Fan IV Critical temp */
47  HWM_INITVAL(0x38, 3), /* Smart Fan IV Critical temp tolerance */
48  HWM_INITVAL(0x39, 0x81), /* Enable SYSTIN weight value */
49  HWM_INITVAL(0x3a, 1), /* SYSTIN temperature step */
50  HWM_INITVAL(0x3b, 2), /* SYSTIN step tolerance */
51  HWM_INITVAL(0x3c, 1), /* SYSTIN weight step */
52  HWM_INITVAL(0x3d, 40), /* SYSTIN temperature base */
53  HWM_INITVAL(0x3e, 0x00), /* SYSTIN fan duty base */
54 
55  HWM_BANK(0),
56 };
57 
58 static void hwm_init(void)
59 {
60  /* Set up fan control */
61  for (int i = 0; i < ARRAY_SIZE(hwm_initvals); i++)
63 }
64 
65 static const u16 superio_initvals[] = {
66  /* Global config registers */
67  SUPERIO_INITVAL(0x1a, 0x02),
68  SUPERIO_INITVAL(0x1b, 0x6a),
69  SUPERIO_INITVAL(0x27, 0x80),
70 #if CONFIG(DISABLE_UART_ON_TESTPADS)
71  SUPERIO_INITVAL(0x2a, 0x80),
72 #else
73  SUPERIO_INITVAL(0x2a, 0x00),
74 #endif
75  SUPERIO_INITVAL(0x2c, 0x00),
76 
77  SUPERIO_BANK(2), /* UART A */
78  SUPERIO_INITVAL(0x30, 0x01),
79  SUPERIO_INITVAL(0x60, 0x03),
80  SUPERIO_INITVAL(0x61, 0xf8),
81  SUPERIO_INITVAL(0x70, 0x04),
82 
83  SUPERIO_BANK(7), /* GPIO config */
84  SUPERIO_INITVAL(0x30, 0x01),
85  SUPERIO_INITVAL(0xe0, 0xcf),
86  SUPERIO_INITVAL(0xe1, 0x0f),
87  SUPERIO_INITVAL(0xe4, 0xed),
88  SUPERIO_INITVAL(0xe5, 0x4d),
89  SUPERIO_INITVAL(0xec, 0x30),
90  SUPERIO_INITVAL(0xee, 0xff),
91 
92  SUPERIO_BANK(8),
93  SUPERIO_INITVAL(0x30, 0x0a),
94  SUPERIO_INITVAL(0x60, GPIO_PORT >> 8),
95  SUPERIO_INITVAL(0x61, GPIO_PORT & 0xff),
96 
97  SUPERIO_BANK(9),
98  SUPERIO_INITVAL(0x30, 0x8c),
99  SUPERIO_INITVAL(0xe1, 0x90),
100 
101  SUPERIO_BANK(0xa),
102  SUPERIO_INITVAL(0xe4, 0x20),
103  SUPERIO_INITVAL(0xe6, 0x4c),
104 
105  SUPERIO_BANK(0xb), /* HWM & LED */
106  SUPERIO_INITVAL(0x30, 0x01),
107  SUPERIO_INITVAL(0x60, HWM_PORT >> 8),
108  SUPERIO_INITVAL(0x61, HWM_PORT & 0xff),
109  SUPERIO_INITVAL(0xf7, 0x67),
110  SUPERIO_INITVAL(0xf8, 0x60),
111 
112  SUPERIO_BANK(0x16),
113  SUPERIO_INITVAL(0x30, 0x00),
114 };
115 
116 static void superio_init(void)
117 {
119  for (int i = 0; i < ARRAY_SIZE(superio_initvals); i++)
121  SUPERIO_LOCK;
122 }
123 
125 {
126  superio_init();
127  hwm_init();
128 }
129 
130 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
131 {
132  read_spd(&spd[0], 0x50, id_only);
133  read_spd(&spd[2], 0x51, id_only);
134 }
135 
136 const struct southbridge_usb_port mainboard_usb_ports[] = {
137 #define USB_CONFIG(enabled, current, ocpin) { enabled, current, ocpin }
138 #include "usb.h"
139 };
#define ARRAY_SIZE(a)
Definition: helpers.h:12
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
void bootblock_mainboard_early_init(void)
static void superio_init(void)
static const u16 hwm_initvals[]
static const u16 superio_initvals[]
const struct southbridge_usb_port mainboard_usb_ports[]
static void hwm_init(void)
u8 spd_raw_data[256]
Definition: ddr3.h:156
#define PASSIVE_TEMPERATURE
Definition: thermal.h:10
#define CRITICAL_TEMPERATURE
Definition: thermal.h:7
void read_spd(spd_raw_data *spd, u8 addr, bool id_only)
Definition: raminit.c:138
uint16_t u16
Definition: stdint.h:48
#define HWM_INITVAL
Definition: superio.h:16
#define SUPERIO_WRITE_INITVAL(val)
Definition: superio.h:32
#define HWM_BANK(x)
Definition: superio.h:15
#define HWM_PORT
Definition: superio.h:10
#define HWM_WRITE_INITVAL(val)
Definition: superio.h:34
#define SUPERIO_INITVAL(reg, data)
Definition: superio.h:14
#define SUPERIO_UNLOCK
Definition: superio.h:18
#define SUPERIO_BANK(x)
Definition: superio.h:13
#define GPIO_PORT
Definition: superio.h:11
#define SUPERIO_LOCK
Definition: superio.h:23