coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_southbridge.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
bootblock_common.h
>
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#include <
stdint.h
>
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#include <
cf9_reset.h
>
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#include <
northbridge/intel/sandybridge/raminit_native.h
>
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#include <
southbridge/intel/bd82x6x/pch.h
>
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#include "
superio.h
"
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#include "
thermal.h
"
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static
const
u16
hwm_initvals
[] = {
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HWM_BANK
(0),
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HWM_INITVAL
(0xae, 0x01),
/* Enable PECI Agent0 */
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HWM_BANK
(7),
/* PECI */
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HWM_INITVAL
(0x01, 0x95),
/* Enable PECI */
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HWM_INITVAL
(0x03, 0x10),
/* Enable Agent 0 */
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/*
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* PECI temperatures are negative, going up to 0.
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* 0 represents the maximum allowable junction temperature, Tjmax.
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* There is also Tcontrol, which is the temperature at which the
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* system cooling should run at full speed.
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* Since the NCT5577D fan control only supports positive values,
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* Tbase0 is used as an offset.
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*/
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HWM_INITVAL
(0x09,
CRITICAL_TEMPERATURE
),
/* Tbase0 */
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HWM_BANK
(2),
/* CPUFAN control */
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HWM_INITVAL
(0x00, 0x0c),
/* PECI Agent 0 as CPUFAN monitoring source */
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HWM_INITVAL
(0x01, 50),
/* Target temperature */
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HWM_INITVAL
(0x02, 0x40),
/* Enable Smart Fan IV mode */
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HWM_INITVAL
(0x03, 0x01),
/* Step-up time */
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HWM_INITVAL
(0x04, 0x01),
/* Step-down time */
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HWM_INITVAL
(0x05, 0x10),
/* Stop PWM value */
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HWM_INITVAL
(0x06, 0x20),
/* Start PWM value */
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HWM_INITVAL
(0x21, 45),
/* Smart Fan IV Temp1 */
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HWM_INITVAL
(0x22, 46),
/* Smart Fan IV Temp2 */
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HWM_INITVAL
(0x23, 47),
/* Smart Fan IV Temp3 */
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HWM_INITVAL
(0x24,
PASSIVE_TEMPERATURE
),
/* Smart Fan IV Temp4 */
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HWM_INITVAL
(0x27, 0x01),
/* Smart Fan IV PWM1 */
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HWM_INITVAL
(0x28, 0x02),
/* Smart Fan IV PWM2 */
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HWM_INITVAL
(0x29, 0x03),
/* Smart Fan IV PWM3 */
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HWM_INITVAL
(0x2a, 0xff),
/* Smart Fan IV PWM4 */
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/* Smart Fan IV Critical temp */
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HWM_INITVAL
(0x35,
CRITICAL_TEMPERATURE
),
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HWM_INITVAL
(0x38, 3),
/* Smart Fan IV Critical temp tolerance */
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HWM_INITVAL
(0x39, 0x81),
/* Enable SYSTIN weight value */
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HWM_INITVAL
(0x3a, 1),
/* SYSTIN temperature step */
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HWM_INITVAL
(0x3b, 2),
/* SYSTIN step tolerance */
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HWM_INITVAL
(0x3c, 1),
/* SYSTIN weight step */
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HWM_INITVAL
(0x3d, 40),
/* SYSTIN temperature base */
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HWM_INITVAL
(0x3e, 0x00),
/* SYSTIN fan duty base */
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HWM_BANK
(0),
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};
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static
void
hwm_init
(
void
)
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{
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/* Set up fan control */
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for
(
int
i = 0; i <
ARRAY_SIZE
(
hwm_initvals
); i++)
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HWM_WRITE_INITVAL
(
hwm_initvals
[i]);
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}
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static
const
u16
superio_initvals
[] = {
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/* Global config registers */
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SUPERIO_INITVAL
(0x1a, 0x02),
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SUPERIO_INITVAL
(0x1b, 0x6a),
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SUPERIO_INITVAL
(0x27, 0x80),
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#if CONFIG(DISABLE_UART_ON_TESTPADS)
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SUPERIO_INITVAL
(0x2a, 0x80),
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#else
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SUPERIO_INITVAL
(0x2a, 0x00),
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#endif
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SUPERIO_INITVAL
(0x2c, 0x00),
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SUPERIO_BANK
(2),
/* UART A */
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SUPERIO_INITVAL
(0x30, 0x01),
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SUPERIO_INITVAL
(0x60, 0x03),
80
SUPERIO_INITVAL
(0x61, 0xf8),
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SUPERIO_INITVAL
(0x70, 0x04),
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SUPERIO_BANK
(7),
/* GPIO config */
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SUPERIO_INITVAL
(0x30, 0x01),
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SUPERIO_INITVAL
(0xe0, 0xcf),
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SUPERIO_INITVAL
(0xe1, 0x0f),
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SUPERIO_INITVAL
(0xe4, 0xed),
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SUPERIO_INITVAL
(0xe5, 0x4d),
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SUPERIO_INITVAL
(0xec, 0x30),
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SUPERIO_INITVAL
(0xee, 0xff),
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SUPERIO_BANK
(8),
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SUPERIO_INITVAL
(0x30, 0x0a),
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SUPERIO_INITVAL
(0x60,
GPIO_PORT
>> 8),
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SUPERIO_INITVAL
(0x61,
GPIO_PORT
& 0xff),
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SUPERIO_BANK
(9),
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SUPERIO_INITVAL
(0x30, 0x8c),
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SUPERIO_INITVAL
(0xe1, 0x90),
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SUPERIO_BANK
(0xa),
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SUPERIO_INITVAL
(0xe4, 0x20),
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SUPERIO_INITVAL
(0xe6, 0x4c),
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SUPERIO_BANK
(0xb),
/* HWM & LED */
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SUPERIO_INITVAL
(0x30, 0x01),
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SUPERIO_INITVAL
(0x60,
HWM_PORT
>> 8),
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SUPERIO_INITVAL
(0x61,
HWM_PORT
& 0xff),
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SUPERIO_INITVAL
(0xf7, 0x67),
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SUPERIO_INITVAL
(0xf8, 0x60),
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SUPERIO_BANK
(0x16),
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SUPERIO_INITVAL
(0x30, 0x00),
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};
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static
void
superio_init
(
void
)
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{
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SUPERIO_UNLOCK
;
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for
(
int
i = 0; i <
ARRAY_SIZE
(
superio_initvals
); i++)
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SUPERIO_WRITE_INITVAL
(
superio_initvals
[i]);
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SUPERIO_LOCK
;
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}
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void
bootblock_mainboard_early_init
(
void
)
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{
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superio_init
();
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hwm_init
();
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}
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void
mainboard_get_spd
(
spd_raw_data
*spd,
bool
id_only)
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{
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read_spd
(&spd[0], 0x50, id_only);
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read_spd
(&spd[2], 0x51, id_only);
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}
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const
struct
southbridge_usb_port
mainboard_usb_ports
[] = {
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#define USB_CONFIG(enabled, current, ocpin) { enabled, current, ocpin }
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#include "
usb.h
"
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};
bootblock_common.h
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
cf9_reset.h
mainboard_get_spd
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
Definition:
early_southbridge.c:130
bootblock_mainboard_early_init
void bootblock_mainboard_early_init(void)
Definition:
early_southbridge.c:124
superio_init
static void superio_init(void)
Definition:
early_southbridge.c:116
hwm_initvals
static const u16 hwm_initvals[]
Definition:
early_southbridge.c:12
superio_initvals
static const u16 superio_initvals[]
Definition:
early_southbridge.c:65
mainboard_usb_ports
const struct southbridge_usb_port mainboard_usb_ports[]
Definition:
early_southbridge.c:136
hwm_init
static void hwm_init(void)
Definition:
early_southbridge.c:58
spd_raw_data
u8 spd_raw_data[256]
Definition:
ddr3.h:156
PASSIVE_TEMPERATURE
#define PASSIVE_TEMPERATURE
Definition:
thermal.h:10
CRITICAL_TEMPERATURE
#define CRITICAL_TEMPERATURE
Definition:
thermal.h:7
read_spd
void read_spd(spd_raw_data *spd, u8 addr, bool id_only)
Definition:
raminit.c:138
raminit_native.h
thermal.h
usb.h
pch.h
stdint.h
u16
uint16_t u16
Definition:
stdint.h:48
southbridge_usb_port
Definition:
pch.h:56
superio.h
HWM_INITVAL
#define HWM_INITVAL
Definition:
superio.h:16
SUPERIO_WRITE_INITVAL
#define SUPERIO_WRITE_INITVAL(val)
Definition:
superio.h:32
HWM_BANK
#define HWM_BANK(x)
Definition:
superio.h:15
HWM_PORT
#define HWM_PORT
Definition:
superio.h:10
HWM_WRITE_INITVAL
#define HWM_WRITE_INITVAL(val)
Definition:
superio.h:34
SUPERIO_INITVAL
#define SUPERIO_INITVAL(reg, data)
Definition:
superio.h:14
SUPERIO_UNLOCK
#define SUPERIO_UNLOCK
Definition:
superio.h:18
SUPERIO_BANK
#define SUPERIO_BANK(x)
Definition:
superio.h:13
GPIO_PORT
#define GPIO_PORT
Definition:
superio.h:11
SUPERIO_LOCK
#define SUPERIO_LOCK
Definition:
superio.h:23
src
mainboard
intel
dcp847ske
early_southbridge.c
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