coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio_early.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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static
const
struct
pad_config
early_gpio_table
[] = {
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PAD_CFG_GPO
(
GPP_C14
, 1, RSMRST),
// M.2_PLT_RST_CNTRL1#
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PAD_CFG_GPO
(
GPP_C15
, 1, RSMRST),
// M.2_PLT_RST_CNTRL2#
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PAD_CFG_GPO
(
GPP_F0
, 1, RSMRST),
// TBT_PERST_N
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PAD_CFG_GPO
(
GPP_F22
, 0, DEEP),
// DGPU_RST#_PCH
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PAD_CFG_GPO
(
GPP_F23
, 0, DEEP),
// DGPU_PWR_EN
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PAD_CFG_GPO
(
GPP_H16
, 1, RSMRST),
// TBT_RTD3_PWR_EN_R
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PAD_CFG_GPO
(
GPP_K8
, 1, RSMRST),
// SATA_M2_PWR_EN1
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PAD_CFG_GPO
(
GPP_K9
, 1, RSMRST),
// SATA_M2_PWR_EN2
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PAD_CFG_GPO
(
GPP_K11
, 1, RSMRST),
// GPIO_LANRTD3
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};
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void
variant_configure_early_gpios
(
void
)
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{
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gpio_configure_pads
(
early_gpio_table
,
ARRAY_SIZE
(
early_gpio_table
));
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}
GPP_C15
#define GPP_C15
Definition:
gpio_soc_defs.h:552
GPP_H16
#define GPP_H16
Definition:
gpio_soc_defs.h:232
GPP_F23
#define GPP_F23
Definition:
gpio_soc_defs.h:596
GPP_F0
#define GPP_F0
Definition:
gpio_soc_defs.h:573
GPP_C14
#define GPP_C14
Definition:
gpio_soc_defs.h:551
GPP_F22
#define GPP_F22
Definition:
gpio_soc_defs.h:595
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
variant_configure_early_gpios
void variant_configure_early_gpios(void)
Definition:
gpio_early.c:14
GPP_K9
#define GPP_K9
Definition:
gpio_soc_defs_cnp_h.h:214
GPP_K11
#define GPP_K11
Definition:
gpio_soc_defs_cnp_h.h:216
GPP_K8
#define GPP_K8
Definition:
gpio_soc_defs_cnp_h.h:213
gpio_configure_pads
void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
program a particular set of GPIO
Definition:
gpio.c:307
PAD_CFG_GPO
#define PAD_CFG_GPO(pad, val, rst)
Definition:
gpio_defs.h:247
pad_config
Definition:
gpio.h:75
early_gpio_table
static const struct pad_config early_gpio_table[]
Definition:
gpio_early.c:6
src
mainboard
system76
oryp6
variants
oryp7
gpio_early.c
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