coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <mainboard/gpio.h>
4 #include <soc/gpio.h>
5 
6 static const struct pad_config gpio_table[] = {
7  /* ------- GPIO Group GPD ------- */
8  PAD_NC(GPD0, NONE), // PM_BATLOW#
9  PAD_CFG_NF(GPD1, NONE, DEEP, NF1), // AC_PRESENT
10  _PAD_CFG_STRUCT(GPD2, 0x880500, 0x0), // LAN_WAKEUP#
11  PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
12  PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
13  PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
14  PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A#
15  PAD_NC(GPD7, NONE),
16  PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUSCLK
17  PAD_CFG_NF(GPD9, NONE, DEEP, NF1), // PCH_SLP_WLAN#
18  PAD_NC(GPD10, NONE), // SLP_S5#
19  PAD_NC(GPD11, NONE), // PCH_GPD11
20 
21  /* ------- GPIO Group A ------- */
22  PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
23  PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
24  PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
25  PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
26  PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
27  PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
28  PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
29  PAD_NC(GPP_A7, NONE), // G_INT1
30  PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
31  PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
32  PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // PCLK_TPM
33  PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), // LAN_WAKEUP#
34  PAD_NC(GPP_A12, NONE), // PCH_GPP_A12
35  PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
36  PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // S4_STATE#
37  PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), // SUSACK#
40  PAD_CFG_GPO(GPP_A18, 1, DEEP), // TBTA_ACE_GPIO3
41  PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN
42  PAD_CFG_GPO(GPP_A20, 0, DEEP), // TBTA_ACE_GPIO0
43  PAD_CFG_GPO(GPP_A21, 1, PLTRST), // TBT_FRC_PWR
44  PAD_CFG_GPO(GPP_A22, 0, PWROK), // PS8338B_SW
45  PAD_CFG_GPO(GPP_A23, 0, PWROK), // PS8338B_PCH
46 
47  /* ------- GPIO Group B ------- */
48  PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // CORE_VID0
49  PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // CORE_VID1
50  PAD_NC(GPP_B2, NONE), // VRALERT#
51  PAD_NC(GPP_B3, NONE),
52  PAD_NC(GPP_B4, NONE),
53  PAD_NC(GPP_B5, NONE), // PCIECLKRQ0#
54  PAD_NC(GPP_B6, NONE), // PCIECLKRQ1#
55  PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ#
56  PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // LAN_CLKREQ#
57  PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // TBT_CLKREQ#
58  PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD_CLKREQ#
60  PAD_NC(GPP_B12, NONE), // SLP_S0#
61  PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLTRST#
62  PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
63  PAD_NC(GPP_B15, NONE), // PCH_GPP_B15
64  PAD_NC(GPP_B16, NONE), // PCH_GPP_B16
65  PAD_NC(GPP_B17, NONE), // PCH_GPP_B17
66  PAD_NC(GPP_B18, NONE), // GSPI0_BBS0 - No Reboot strap
67  PAD_NC(GPP_B19, NONE), // PCH_GPP_B19
68  PAD_NC(GPP_B20, NONE), // PCH_GPP_B20
69  PAD_NC(GPP_B21, NONE), // PCH_GPP_B21
70  PAD_NC(GPP_B22, NONE), // PCH_GPP_B22 - Boot BIOS strap
71  PAD_NC(GPP_B23, NONE), // PCH_GPP_B23
72 
73  /* ------- GPIO Group C ------- */
74  PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
75  PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
76  PAD_NC(GPP_C2, NONE), // PCH_GPP_C2
77  PAD_NC(GPP_C3, NONE), // SML0CLK
78  PAD_NC(GPP_C4, NONE), // SML0DATA
79  PAD_NC(GPP_C5, NONE), // PCH_GPP_C5
80  PAD_NC(GPP_C6, NONE), // SML1CLK
81  PAD_NC(GPP_C7, NONE), // SML1DATA
82  PAD_NC(GPP_C8, NONE),
83  PAD_NC(GPP_C9, NONE),
86  PAD_NC(GPP_C12, NONE), // TBTA_ACE_GPIO2
87  _PAD_CFG_STRUCT(GPP_C13, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT
88  PAD_NC(GPP_C14, NONE), // TBTA_MRESET
89  PAD_NC(GPP_C15, NONE), // TBTA_ACE_GPIO7
90  PAD_NC(GPP_C16, NONE), // T_SDA
91  PAD_NC(GPP_C17, NONE), // T_SCL
93  _PAD_CFG_STRUCT(GPP_C19, 0x40880100, 0x0000), // SWI#
94  PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
95  PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
96  PAD_NC(GPP_C22, NONE), // UEART2_RTS_N
97  PAD_NC(GPP_C23, NONE), // UART2_CTS_N
98 
99  /* ------- GPIO Group D ------- */
100  PAD_NC(GPP_D0, NONE),
101  PAD_NC(GPP_D1, NONE),
102  PAD_NC(GPP_D2, NONE),
103  PAD_NC(GPP_D3, NONE),
104  PAD_NC(GPP_D4, NONE), // PCH_GPP_D4
105  PAD_NC(GPP_D5, NONE),
106  PAD_NC(GPP_D6, NONE),
107  PAD_NC(GPP_D7, NONE),
108  PAD_CFG_GPO(GPP_D8, 1, DEEP), // SB_BLON
109  PAD_NC(GPP_D9, NONE), // T_INT
110  PAD_NC(GPP_D10, NONE), // EDP_DET
111  PAD_NC(GPP_D11, NONE),
112  PAD_NC(GPP_D12, NONE),
113  PAD_NC(GPP_D13, NONE),
114  PAD_NC(GPP_D14, NONE),
115  PAD_NC(GPP_D15, NONE),
116  PAD_NC(GPP_D16, NONE),
117  PAD_NC(GPP_D17, NONE),
118  PAD_NC(GPP_D18, NONE),
119  PAD_NC(GPP_D19, NONE),
120  PAD_NC(GPP_D20, NONE),
121  PAD_CFG_GPI(GPP_D21, NONE, DEEP), // TPM_DET#
122  PAD_NC(GPP_D22, NONE),
123  PAD_NC(GPP_D23, NONE),
124 
125  /* ------- GPIO Group E ------- */
126  PAD_NC(GPP_E0, NONE), // PCH_GPP_E0
127  PAD_NC(GPP_E1, NONE), // SATA_ODD_PRSNT#
128  PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), // SATAGP2
129  PAD_NC(GPP_E3, NONE),
130  PAD_NC(GPP_E4, NONE), // DEVSLP0
131  PAD_NC(GPP_E5, NONE), // DEVSLP1
132  PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2
133  PAD_NC(GPP_E7, NONE),
134  PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATA_LED#
135  PAD_NC(GPP_E9, NONE), // USB_OC#12
136  PAD_NC(GPP_E10, NONE), // USB_OC#34
137  PAD_NC(GPP_E11, NONE), // USB_OC#56
138  PAD_NC(GPP_E12, NONE), // USB_OC#78
139  PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD
140  PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD
141  _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), // SMI#
142  PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, DEEP, LEVEL), // SCI#
143  PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD
144  PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK
145  PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), // MDP_CTRLDATA
146  PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK
147  PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), // HDMI_CTRLDATA
148  PAD_NC(GPP_E22, NONE),
149  PAD_NC(GPP_E23, NONE),
150 
151  /* ------- GPIO Group F ------- */
152  PAD_NC(GPP_F0, NONE),
153  PAD_NC(GPP_F1, NONE),
154  PAD_NC(GPP_F2, NONE),
155  PAD_NC(GPP_F3, NONE),
156  PAD_NC(GPP_F4, NONE),
157  PAD_NC(GPP_F5, NONE),
158  PAD_NC(GPP_F6, NONE),
159  PAD_NC(GPP_F7, NONE),
160  PAD_NC(GPP_F8, NONE),
161  PAD_NC(GPP_F9, NONE),
162  PAD_NC(GPP_F10, NONE),
163  PAD_NC(GPP_F11, NONE),
164  PAD_NC(GPP_F12, NONE),
165  PAD_NC(GPP_F13, NONE),
166  PAD_NC(GPP_F14, NONE),
167  PAD_NC(GPP_F15, NONE),
168  PAD_NC(GPP_F16, NONE),
169  PAD_NC(GPP_F17, NONE),
170  PAD_NC(GPP_F18, NONE),
171  PAD_NC(GPP_F19, NONE),
172  PAD_NC(GPP_F20, NONE),
173  PAD_NC(GPP_F21, NONE),
174  PAD_NC(GPP_F22, NONE),
175  PAD_NC(GPP_F23, NONE), // LIGHT_KB_DET#
176 
177  /* ------- GPIO Group G ------- */
178  PAD_NC(GPP_G0, NONE),
179  PAD_CFG_GPI(GPP_G1, NONE, DEEP), // TBT Detect
180  PAD_NC(GPP_G2, NONE),
181  PAD_NC(GPP_G3, NONE), // ASM1543_I_SEL0
182  PAD_NC(GPP_G4, NONE), // ASM1543_I_SEL1
183  PAD_NC(GPP_G5, NONE),
184  PAD_NC(GPP_G6, NONE),
185  PAD_NC(GPP_G7, NONE),
186 };
187 
189 {
191 }
#define GPD11
#define GPP_A4
#define GPP_C15
#define GPD3
#define GPP_B6
Definition: gpio_soc_defs.h:59
#define GPP_D1
#define GPD9
#define GPP_C2
#define GPP_D10
#define GPP_D8
#define GPP_D17
#define GPP_E3
#define GPP_A18
#define GPP_F21
#define GPP_C12
#define GPP_F12
#define GPP_F16
#define GPP_E0
#define GPP_F6
#define GPP_D14
#define GPP_B1
Definition: gpio_soc_defs.h:54
#define GPP_F20
#define GPP_F23
#define GPP_C5
#define GPP_A14
#define GPP_B12
Definition: gpio_soc_defs.h:65
#define GPP_D12
#define GPP_B16
Definition: gpio_soc_defs.h:69
#define GPP_A5
#define GPP_B2
Definition: gpio_soc_defs.h:55
#define GPP_D7
#define GPP_B13
Definition: gpio_soc_defs.h:66
#define GPP_E6
#define GPP_F0
#define GPP_D6
#define GPP_A19
#define GPP_D2
#define GPP_C9
#define GPP_C22
#define GPD0
#define GPP_D9
#define GPP_F5
#define GPP_B15
Definition: gpio_soc_defs.h:68
#define GPP_E13
#define GPP_A2
#define GPP_C23
#define GPP_C8
#define GPP_D11
#define GPP_A6
#define GPP_C11
#define GPP_D5
#define GPP_B22
Definition: gpio_soc_defs.h:75
#define GPP_A23
#define GPP_C18
#define GPP_F9
#define GPP_C13
#define GPP_E14
#define GPP_E23
#define GPP_E9
#define GPP_C17
#define GPP_E8
#define GPP_A7
#define GPP_E5
#define GPP_A0
#define GPD7
#define GPP_B8
Definition: gpio_soc_defs.h:61
#define GPP_C20
#define GPP_B20
Definition: gpio_soc_defs.h:73
#define GPP_A20
#define GPP_A16
#define GPP_F1
#define GPP_F17
#define GPP_A12
#define GPP_F15
#define GPP_D4
#define GPP_C10
#define GPP_C6
#define GPD2
#define GPP_F10
#define GPP_A3
#define GPP_E7
#define GPP_C16
#define GPP_F7
#define GPD1
#define GPP_F13
#define GPP_C4
#define GPP_D18
#define GPP_B19
Definition: gpio_soc_defs.h:72
#define GPP_E17
#define GPP_E2
#define GPP_E19
#define GPP_C21
#define GPP_B9
Definition: gpio_soc_defs.h:62
#define GPD10
#define GPP_E18
#define GPP_F14
#define GPP_F4
#define GPP_A10
#define GPP_A8
#define GPP_D0
#define GPP_A1
#define GPP_B14
Definition: gpio_soc_defs.h:67
#define GPP_B11
Definition: gpio_soc_defs.h:64
#define GPP_D13
#define GPP_B18
Definition: gpio_soc_defs.h:71
#define GPP_B5
Definition: gpio_soc_defs.h:58
#define GPP_B0
Definition: gpio_soc_defs.h:53
#define GPP_A11
#define GPP_C14
#define GPP_E20
#define GPP_A15
#define GPP_A9
#define GPP_E10
#define GPP_F8
#define GPP_C19
#define GPD8
#define GPP_A13
#define GPP_A21
#define GPP_B23
Definition: gpio_soc_defs.h:76
#define GPP_E15
#define GPP_B10
Definition: gpio_soc_defs.h:63
#define GPP_E16
#define GPP_D19
#define GPP_C1
#define GPP_F2
#define GPP_E11
#define GPD6
#define GPP_F18
#define GPP_B3
Definition: gpio_soc_defs.h:56
#define GPP_A22
#define GPP_F22
#define GPP_D15
#define GPP_F11
#define GPP_B21
Definition: gpio_soc_defs.h:74
#define GPD4
#define GPP_B4
Definition: gpio_soc_defs.h:57
#define GPP_D16
#define GPP_F3
#define GPP_E22
#define GPP_E21
#define GPP_C3
#define GPP_E12
#define GPP_A17
#define GPP_B17
Definition: gpio_soc_defs.h:70
#define GPP_E4
#define GPP_C0
#define GPD5
#define GPP_E1
#define GPP_F19
#define GPP_B7
Definition: gpio_soc_defs.h:60
#define GPP_C7
#define GPP_D3
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define GPP_D23
#define GPP_G1
Definition: gpio_soc_defs.h:89
#define GPP_G7
Definition: gpio_soc_defs.h:95
#define GPP_D22
#define GPP_G4
Definition: gpio_soc_defs.h:92
#define GPP_G2
Definition: gpio_soc_defs.h:90
#define GPP_D21
#define GPP_G6
Definition: gpio_soc_defs.h:94
#define GPP_G0
Definition: gpio_soc_defs.h:88
#define GPP_D20
#define GPP_G3
Definition: gpio_soc_defs.h:91
#define GPP_G5
Definition: gpio_soc_defs.h:93
void mainboard_configure_gpios(void)
Definition: gpio.c:223
const struct pad_config gpio_table[]
Definition: gpio.c:33
void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
program a particular set of GPIO
Definition: gpio.c:307
#define PAD_NC(pin)
Definition: gpio_defs.h:263
#define PAD_CFG_GPI(pad, pull, rst)
Definition: gpio_defs.h:284
#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig)
Definition: gpio_defs.h:452
#define _PAD_CFG_STRUCT(__pad, __config0, __config1)
Definition: gpio_defs.h:166
#define PAD_CFG_NF(pad, pull, rst, func)
Definition: gpio_defs.h:197
#define PAD_CFG_GPO(pad, val, rst)
Definition: gpio_defs.h:247