coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
xdci.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <device/pci_ids.h>
6 #include <intelblocks/xdci.h>
8 
9 __weak void soc_xdci_init(struct device *dev) { /* no-op */ }
10 
11 bool xdci_can_enable(unsigned int xdci_devfn)
12 {
13  /* Enable xDCI controller if enabled in devicetree and allowed */
14  if (!vboot_can_enable_udc()) {
15  devfn_disable(pci_root_bus(), xdci_devfn);
16  return false;
17  }
18  return is_devfn_enabled(xdci_devfn);
19 }
20 
21 static struct device_operations usb_xdci_ops = {
23  .set_resources = pci_dev_set_resources,
24  .enable_resources = pci_dev_enable_resources,
25  .init = soc_xdci_init,
26  .ops_pci = &pci_dev_ops_pci,
27 };
28 
29 static const unsigned short pci_device_ids[] = {
46  0
47 };
48 
49 static const struct pci_driver pch_usb_xdci __pci_driver = {
50  .ops = &usb_xdci_ops,
51  .vendor = PCI_VID_INTEL,
52  .devices = pci_device_ids,
53 };
void soc_xdci_init(struct device *dev)
Definition: xdci.c:74
bool xdci_can_enable(unsigned int xdci_devfn)
Definition: xdci.c:11
static struct device_operations usb_xdci_ops
Definition: xdci.c:21
static const struct pci_driver pch_usb_xdci __pci_driver
Definition: xdci.c:49
static const unsigned short pci_device_ids[]
Definition: xdci.c:29
void devfn_disable(const struct bus *bus, unsigned int devfn)
Definition: device.c:25
DEVTREE_CONST struct bus * pci_root_bus(void)
Definition: device_const.c:239
bool is_devfn_enabled(unsigned int devfn)
Definition: device_const.c:382
void pci_dev_enable_resources(struct device *dev)
Definition: pci_device.c:721
void pci_dev_read_resources(struct device *dev)
Definition: pci_device.c:534
struct pci_operations pci_dev_ops_pci
Default device operation for PCI devices.
Definition: pci_device.c:911
void pci_dev_set_resources(struct device *dev)
Definition: pci_device.c:691
#define PCI_DID_INTEL_JSP_XDCI
Definition: pci_ids.h:4281
#define PCI_DID_INTEL_APL_XDCI
Definition: pci_ids.h:4269
#define PCI_DID_INTEL_TGP_H_XDCI
Definition: pci_ids.h:4279
#define PCI_DID_INTEL_ADP_S_XDCI
Definition: pci_ids.h:4283
#define PCI_DID_INTEL_SPT_LP_XDCI
Definition: pci_ids.h:4271
#define PCI_DID_INTEL_CNP_H_XDCI
Definition: pci_ids.h:4273
#define PCI_DID_INTEL_TGP_LP_XDCI
Definition: pci_ids.h:4277
#define PCI_DID_INTEL_CNL_LP_XDCI
Definition: pci_ids.h:4272
#define PCI_DID_INTEL_CMP_LP_XDCI
Definition: pci_ids.h:4275
#define PCI_DID_INTEL_GLK_XDCI
Definition: pci_ids.h:4270
#define PCI_DID_INTEL_CMP_H_XDCI
Definition: pci_ids.h:4276
#define PCI_DID_INTEL_MTL_XDCI
Definition: pci_ids.h:4286
#define PCI_VID_INTEL
Definition: pci_ids.h:2157
#define PCI_DID_INTEL_ADP_P_XDCI
Definition: pci_ids.h:4282
#define PCI_DID_INTEL_MCC_XDCI
Definition: pci_ids.h:4280
#define PCI_DID_INTEL_ICP_LP_XDCI
Definition: pci_ids.h:4274
#define PCI_DID_INTEL_ADP_M_XDCI
Definition: pci_ids.h:4285
const struct smm_save_state_ops *legacy_ops __weak
Definition: save_state.c:8
void(* read_resources)(struct device *dev)
Definition: device.h:39
Definition: device.h:107
int vboot_can_enable_udc(void)
Definition: vboot_common.c:36