uart.h File Reference

#include <types.h>

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Functions
int	uart_is_enabled (const size_t bus)
	Returns the UART state. More...
int	uart_setup (const size_t bus, int baudrate)
	Setup UART with desired BAUD rate in 8N1, no parity mode. More...

Function Documentation

uart_is_enabled()

int uart_is_enabled

(

const size_t

bus

)

Returns the UART state.

Parameters

bus	The UART to operate on

Returns

Boolean: True if UART is enabled

Definition at line 120 of file uart.c.

References assert, cn81xx_uart_ctl::csclk_en, read64(), cn81xx_uart_ctl::s, cn81xx_uart_ctl::u, UAAx_PF_BAR0, and cn81xx_uart::uctl_ctl.

Referenced by bootblock_mainboard_early_init(), and dt_platform_fixup().

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uart_setup()

int uart_setup	(	const size_t	bus,
		int	baudrate
	)

Setup UART with desired BAUD rate in 8N1, no parity mode.

Parameters

bus	The UART to operate on
baudrate	baudrate to set up

Returns

Boolean: True on error

1. Assert all resets: a. UAA reset: UCTL_CTL[UAA_RST] = 1 b. UCTL reset: UCTL_CTL[UCTL_RST] = 1
2. Configure the HCLK: a. Reset the clock dividers: UCTL_CTL[H_CLKDIV_RST] = 1. b. Select the HCLK frequency i. UCTL_CTL[H_CLKDIV] = desired value, ii. UCTL_CTL[H_CLKDIV_EN] = 1 to enable the HCLK. iii. Readback UCTL_CTL to ensure the values take effect. c. Deassert the HCLK clock divider reset: UCTL_CTL[H_CLKDIV_RST] = 0.
3. Wait 20 HCLK cycles from step 3 for HCLK to start and async fifo to properly reset.
4. Deassert UCTL and UAHC resets: a. UCTL_CTL[UCTL_RST] = 0 b. Wait 10 HCLK cycles. c. UCTL_CTL[UAHC_RST] = 0 d. You will have to wait 10 HCLK cycles before accessing any HCLK-only registers.
5. Enable conditional SCLK of UCTL by writing UCTL_CTL[CSCLK_EN] = 1.

Exit here if the UART is not going to be used in coreboot. The previous initialization steps are sufficient to make the Linux kernel not panic.

1. Initialize the integer and fractional baud rate divider registers UARTIBRD and UARTFBRD as follows: a. Baud Rate Divisor = UARTCLK/(16xBaud Rate) = BRDI + BRDF b. The fractional register BRDF, m is calculated as integer(BRDF x 64 + 0.5) Example calculation: If the required baud rate is 230400 and hclk = 4MHz then: Baud Rate Divisor = (4x10^6)/(16x230400) = 1.085 This means BRDI = 1 and BRDF = 0.085. Therefore, fractional part, BRDF = integer((0.085x64)+0.5) = 5 Generated baud rate divider = 1+5/64 = 1.078
2. Program the line control register UAA(0..1)_LCR_H and the control register UAA(0..1)_CR

Definition at line 141 of file uart.c.

References assert, pl011_uart::cr, cn81xx_uart_ctl::csclk_en, pl011_uart::fbrd, cn81xx_uart_ctl::h_clk_byp_sel, cn81xx_uart_ctl::h_clk_en, cn81xx_uart_ctl::h_clkdiv_rst, cn81xx_uart_ctl::h_clkdiv_sel, pl011_uart::ibrd, pl011_uart::lcr_h, cn81xx_uart::pl011, PL011_UARTCR_RXE, PL011_UARTCR_TXE, PL011_UARTCR_UARTEN, PL011_UARTLCR_H_FEN, PL011_UARTLCR_H_WLEN_8, read64(), cn81xx_uart_ctl::s, thunderx_get_io_clock(), cn81xx_uart_ctl::u, cn81xx_uart_ctl::uaa_rst, UAAx_PF_BAR0, UART_FBRD_BAUD_DIVFRAC_MASK, UART_SCLK_DIV, uart_sclk_divisor(), uart_wait_hclk(), cn81xx_uart::uctl_ctl, cn81xx_uart_ctl::uctl_rst, write32(), and write64().

Referenced by bootblock_mainboard_early_init().

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