coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
bootblock.c
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-only */
2
3
#include <
bootblock_common.h
>
4
#include "
board.h
"
5
#include <
soc/qupv3_i2c_common.h
>
6
#include <soc/qcom_qup_se.h>
7
#include <
soc/qupv3_spi_common.h
>
8
9
void
bootblock_mainboard_init
(
void
)
10
{
11
setup_chromeos_gpios
();
12
13
if
(
CONFIG
(I2C_TPM))
14
i2c_init
(CONFIG_DRIVER_TPM_I2C_BUS,
I2C_SPEED_FAST
);
/* H1/TPM I2C */
15
16
if
(
CONFIG
(SPI_TPM))
17
qup_spi_init
(CONFIG_DRIVER_TPM_SPI_BUS, 1010 *
KHz
);
/* H1/TPM SPI */
18
19
if
(
CONFIG
(EC_GOOGLE_CHROMEEC))
20
qup_spi_init
(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 *
KHz
);
/* EC SPI */
21
}
bootblock_common.h
KHz
#define KHz
Definition:
helpers.h:79
CONFIG
@ CONFIG
Definition:
dsi_common.h:201
setup_chromeos_gpios
void setup_chromeos_gpios(void)
Definition:
chromeos.c:10
I2C_SPEED_FAST
@ I2C_SPEED_FAST
Definition:
i2c.h:45
bootblock_mainboard_init
__weak void bootblock_mainboard_init(void)
Definition:
bootblock.c:19
board.h
qupv3_i2c_common.h
qupv3_spi_common.h
qup_spi_init
void qup_spi_init(unsigned int bus, unsigned int speed_hz)
Definition:
qupv3_spi.c:157
i2c_init
void i2c_init(unsigned int bus)
Definition:
i2c.c:198
src
mainboard
google
herobrine
bootblock.c
Generated by
1.9.1