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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <spi-generic.h>
Go to the source code of this file.
Functions | |
int | qup_spi_claim_bus (const struct spi_slave *slave) |
int | qup_spi_xfer (const struct spi_slave *slave, const void *dout, size_t bytes_out, void *din, size_t bytes_in) |
void | qup_spi_release_bus (const struct spi_slave *slave) |
void | qup_spi_init (unsigned int bus, unsigned int speed_hz) |
int qup_spi_claim_bus | ( | const struct spi_slave * | slave | ) |
Definition at line 213 of file qupv3_spi.c.
References slave, and spi_qup_set_cs().
Definition at line 157 of file qupv3_spi.c.
References AHB_SEC_SLV_CLK_CGC_ON, assert, CLK_DIV_SHFT, clock_enable_qup(), clrbits32, DEFAULT_CGC_EN, DEFAULT_IO_OUTPUT_CTRL_MSK, DEFAULT_SE_CLK, DMA_AHB_SLV_CFG_ON, DMA_RX_CLK_CGC_ON, DMA_RX_IRQ_EN, DMA_TX_CLK_CGC_ON, DMA_TX_IRQ_EN, FIFO_DEPTH, FORCE_DEFAULT, GENI_DMA_MODE_EN, GENI_M_IRQ_EN, GENI_S_IRQ_EN, GPIO_6MA, gpio_configure(), GPIO_INPUT, GPIO_NO_PULL, GPIO_OUTPUT, KHz, M_CMD_DONE_EN, M_COMMON_GENI_M_IRQ_EN, M_RX_FIFO_LAST_EN, M_RX_FIFO_WATERMARK_EN, M_TX_FIFO_WATERMARK_EN, MIXED, qupv3_se_fw_load_and_init(), qup::regs, S_CMD_DONE_EN, S_COMMON_GENI_S_IRQ_EN, SE_PROTOCOL_SPI, SER_CLK_EN, and write32().
Referenced by bootblock_mainboard_init().
Definition at line 218 of file qupv3_spi.c.
References slave, and spi_qup_set_cs().
int qup_spi_xfer | ( | const struct spi_slave * | slave, |
const void * | dout, | ||
size_t | bytes_out, | ||
void * | din, | ||
size_t | bytes_in | ||
) |
Definition at line 78 of file qupv3_spi.c.
References assert, spi_slave::bus, M_CMD_FRAGMENTATION, MAX, MIN, NULL, qup_handle_transfer(), qup_setup_m_cmd(), qup_spi_xfer(), qup::regs, setup_fifo_params(), slave, SPI_FULL_DUPLEX, SPI_RX_ONLY, SPI_TX_ONLY, stopwatch_init_msecs_expire(), TRANS_LEN_MSK, TX_WATERMARK, and write32().
Referenced by qup_spi_xfer().