#include <device/mmio.h>
#include <soc/cdp.h>
#include <soc/blsp.h>

Include dependency graph for iomap.h:

Macros
#define	readl_i(a) read32((const void *)(a))

#define	writel_i(v, a) write32((void *)a, v)

#define	clrsetbits32_i(addr, clear, set) clrsetbits32(((void *)(addr)), (clear), (set))

#define	GCC_CLK_CTL_REG ((void *)0x01800000u)

#define	MSM_CLK_CTL_BASE GCC_CLK_CTL_REG

#define	GCC_CLK_BRANCH_ENA (GCC_CLK_CTL_REG + 0x6000)

#define	IMEM_AXI (1 << 17)

#define	SYS_NOC_APSS_AHB (1 << 16)

#define	BIMC_AXI_M0 (1 << 15)

#define	APSS_AHB (1 << 14)

#define	APSS_AXI (1 << 13)

#define	MPM_AHB (1 << 12)

#define	GMEM_SYS_NOC_AXI (1 << 11)

#define	BLSP1_AHB (1 << 10)

#define	BLSP1_SLEEP (1 << 9)

#define	PRNG_AHB (1 << 8)

#define	BOOT_ROM_AHB (1 << 7)

#define	MSG_RAM_AHB (1 << 6)

#define	TLMM_AHB (1 << 5)

#define	TLMM (1 << 4)

#define	SPMI_PCNOC_AHB (1 << 3)

#define	CRYPTO (1 << 2)

#define	CRYPTO_AXI (1 << 1)

#define	CRYPTO_AHB (1 << 0)

#define	GCC_BLSP1_QUP1_I2C_APPS_CBCR (MSM_CLK_CTL_BASE + 0x2008)

#define	GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR (MSM_CLK_CTL_BASE + 0x200c)

#define	GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR (MSM_CLK_CTL_BASE + 0x2010)

#define	GCC_BLSP1_QUP2_I2C_APPS_CBCR (MSM_CLK_CTL_BASE + 0x3010)

#define	GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR (MSM_CLK_CTL_BASE + 0x3000)

#define	GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR (MSM_CLK_CTL_BASE + 0x3004)

#define	GCNT_GLOBAL_CTRL_BASE ((void *)0x004a0000u)

#define	GCNT_CNTCR (GCNT_GLOBAL_CTRL_BASE + 0x1000)

#define	GCNT_GLB_CNTCV_LO (GCNT_GLOBAL_CTRL_BASE + 0x1008)

#define	GCNT_GLB_CNTCV_HI (GCNT_GLOBAL_CTRL_BASE + 0x100c)

#define	GCNT_CNTCV_LO (GCNT_GLOBAL_CTRL_BASE + 0x2000)

#define	GCNT_CNTCV_HI (GCNT_GLOBAL_CTRL_BASE + 0x2004)

#define	GCNT_PSHOLD ((void *)0x004AB000u)

#define	RPM_INT ((void *)0x63020)

#define	RPM_INT_ACK ((void *)0x63060)

#define	RPM_SIGNAL_COOKIE ((void *)0x47C20)

#define	RPM_SIGNAL_ENTRY ((void *)0x47C24)

#define	RPM_FW_MAGIC_NUM 0x4D505242

#define	TLMM_BASE_ADDR ((void *)0x01000000)

#define	GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 * (x))

#define	GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4)

#define	USB_HOST2_XHCI_BASE 0x10000000

#define	USB_HOST2_DWC3_BASE 0x1000C100

#define	USB_HOST2_PHY_BASE 0x100F8800

#define	USB_HOST1_XHCI_BASE 0x11000000

#define	USB_HOST1_DWC3_BASE 0x1100C100

#define	USB_HOST1_PHY_BASE 0x110F8800

#define	UART1_DM_BASE ((void *)0x078af000)

#define	UART2_DM_BASE ((void *)0x078b0000)

#define	GCC_BLSP1_UART_BCR_BASE (GCC_CLK_CTL_REG + 0x2038)

#define	GCC_BLSP1_UART_BCR(x) (GCC_BLSP1_UART_BCR_BASE + (x) * 0xff0)

#define	GCC_BLSP1_UART_APPS_CBCR(x) (GCC_BLSP1_UART_BCR(x) + 4)

#define	GCC_BLSP1_UART_APPS_CMD_RCGR(x) (GCC_BLSP1_UART_APPS_CBCR(x) + 8)

#define	GCC_BLSP1_UART_APPS_CFG_RCGR(x) (GCC_BLSP1_UART_APPS_CMD_RCGR(x) + 4)

#define	GCC_BLSP1_UART_APPS_M(x) (GCC_BLSP1_UART_APPS_CFG_RCGR(x) + 4)

#define	GCC_BLSP1_UART_APPS_N(x) (GCC_BLSP1_UART_APPS_M(x) + 4)

#define	GCC_BLSP1_UART_APPS_D(x) (GCC_BLSP1_UART_APPS_N(x) + 4)

#define	GCC_BLSP1_UART_MISC(x) (GCC_BLSP1_UART_APPS_D(x) + 4)

#define	BLSP1_QUP0_BASE ((void *)0x078B5000)

#define	BLSP1_QUP1_BASE ((void *)0x078B6000)

#define	BLSP1_QUP2_BASE ((void *)0x078B7000)

#define	BLSP1_QUP3_BASE ((void *)0x078B8000)

#define	TCSR_BOOT_MISC_DETECT ((void *)0x0193D100)

#define	TCSR_RESET_DEBUG_SW_ENTRY ((void *)0x01940000)

#define	BLSP_MINI_CORE_SHIFT 8

#define	BLSP_MINI_CORE_I2C (0x2u << BLSP_MINI_CORE_SHIFT)

#define	BLSP_MINI_CORE_MASK (0xfu << BLSP_MINI_CORE_SHIFT)

#define	ETIMEDOUT -10

#define	EINVAL -11

#define	EIO -12

Enumerations
enum	{ BLSP1_UART1 , BLSP1_UART2 }

Functions
static void *	blsp_qup_base (blsp_qup_id_t id)

Macro Definition Documentation

◆ APSS_AHB

#define APSS_AHB (1 << 14)

Definition at line 26 of file iomap.h.

◆ APSS_AXI

#define APSS_AXI (1 << 13)

Definition at line 27 of file iomap.h.

◆ BIMC_AXI_M0

#define BIMC_AXI_M0 (1 << 15)

Definition at line 25 of file iomap.h.

◆ BLSP1_AHB

#define BLSP1_AHB (1 << 10)

Definition at line 30 of file iomap.h.

◆ BLSP1_QUP0_BASE

#define BLSP1_QUP0_BASE ((void *)0x078B5000)

Definition at line 95 of file iomap.h.

◆ BLSP1_QUP1_BASE

#define BLSP1_QUP1_BASE ((void *)0x078B6000)

Definition at line 96 of file iomap.h.

◆ BLSP1_QUP2_BASE

#define BLSP1_QUP2_BASE ((void *)0x078B7000)

Definition at line 97 of file iomap.h.

◆ BLSP1_QUP3_BASE

#define BLSP1_QUP3_BASE ((void *)0x078B8000)

Definition at line 98 of file iomap.h.

◆ BLSP1_SLEEP

#define BLSP1_SLEEP (1 << 9)

Definition at line 31 of file iomap.h.

◆ BLSP_MINI_CORE_I2C

#define BLSP_MINI_CORE_I2C (0x2u << BLSP_MINI_CORE_SHIFT)

Definition at line 115 of file iomap.h.

◆ BLSP_MINI_CORE_MASK

#define BLSP_MINI_CORE_MASK (0xfu << BLSP_MINI_CORE_SHIFT)

Definition at line 116 of file iomap.h.

◆ BLSP_MINI_CORE_SHIFT

#define BLSP_MINI_CORE_SHIFT 8

Definition at line 114 of file iomap.h.

◆ BOOT_ROM_AHB

#define BOOT_ROM_AHB (1 << 7)

Definition at line 33 of file iomap.h.

◆ clrsetbits32_i

#define clrsetbits32_i	(	addr,
		clear,
		set
	)	clrsetbits32(((void *)(addr)), (clear), (set))

Definition at line 17 of file iomap.h.

◆ CRYPTO

#define CRYPTO (1 << 2)

Definition at line 38 of file iomap.h.

◆ CRYPTO_AHB

#define CRYPTO_AHB (1 << 0)

Definition at line 40 of file iomap.h.

◆ CRYPTO_AXI

#define CRYPTO_AXI (1 << 1)

Definition at line 39 of file iomap.h.

◆ EINVAL

#define EINVAL -11

Definition at line 119 of file iomap.h.

◆ EIO

#define EIO -12

Definition at line 120 of file iomap.h.

◆ ETIMEDOUT

#define ETIMEDOUT -10

Definition at line 118 of file iomap.h.

◆ GCC_BLSP1_QUP1_I2C_APPS_CBCR

#define GCC_BLSP1_QUP1_I2C_APPS_CBCR (MSM_CLK_CTL_BASE + 0x2008)

Definition at line 42 of file iomap.h.

◆ GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR

#define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR (MSM_CLK_CTL_BASE + 0x2010)

Definition at line 44 of file iomap.h.

◆ GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR

#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR (MSM_CLK_CTL_BASE + 0x200c)

Definition at line 43 of file iomap.h.

◆ GCC_BLSP1_QUP2_I2C_APPS_CBCR

#define GCC_BLSP1_QUP2_I2C_APPS_CBCR (MSM_CLK_CTL_BASE + 0x3010)

Definition at line 45 of file iomap.h.

◆ GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR

#define GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR (MSM_CLK_CTL_BASE + 0x3004)

Definition at line 47 of file iomap.h.

◆ GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR

#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR (MSM_CLK_CTL_BASE + 0x3000)

Definition at line 46 of file iomap.h.

◆ GCC_BLSP1_UART_APPS_CBCR

#define GCC_BLSP1_UART_APPS_CBCR ( x ) (GCC_BLSP1_UART_BCR(x) + 4)

Definition at line 87 of file iomap.h.

◆ GCC_BLSP1_UART_APPS_CFG_RCGR

#define GCC_BLSP1_UART_APPS_CFG_RCGR ( x ) (GCC_BLSP1_UART_APPS_CMD_RCGR(x) + 4)

Definition at line 89 of file iomap.h.

◆ GCC_BLSP1_UART_APPS_CMD_RCGR

#define GCC_BLSP1_UART_APPS_CMD_RCGR ( x ) (GCC_BLSP1_UART_APPS_CBCR(x) + 8)

Definition at line 88 of file iomap.h.

◆ GCC_BLSP1_UART_APPS_D

#define GCC_BLSP1_UART_APPS_D ( x ) (GCC_BLSP1_UART_APPS_N(x) + 4)

Definition at line 92 of file iomap.h.

◆ GCC_BLSP1_UART_APPS_M

#define GCC_BLSP1_UART_APPS_M ( x ) (GCC_BLSP1_UART_APPS_CFG_RCGR(x) + 4)

Definition at line 90 of file iomap.h.

◆ GCC_BLSP1_UART_APPS_N

#define GCC_BLSP1_UART_APPS_N ( x ) (GCC_BLSP1_UART_APPS_M(x) + 4)

Definition at line 91 of file iomap.h.

◆ GCC_BLSP1_UART_BCR

#define GCC_BLSP1_UART_BCR ( x ) (GCC_BLSP1_UART_BCR_BASE + (x) * 0xff0)

Definition at line 86 of file iomap.h.

◆ GCC_BLSP1_UART_BCR_BASE

#define GCC_BLSP1_UART_BCR_BASE (GCC_CLK_CTL_REG + 0x2038)

Definition at line 85 of file iomap.h.

◆ GCC_BLSP1_UART_MISC

#define GCC_BLSP1_UART_MISC ( x ) (GCC_BLSP1_UART_APPS_D(x) + 4)

Definition at line 93 of file iomap.h.

◆ GCC_CLK_BRANCH_ENA

#define GCC_CLK_BRANCH_ENA (GCC_CLK_CTL_REG + 0x6000)

Definition at line 22 of file iomap.h.

◆ GCC_CLK_CTL_REG

#define GCC_CLK_CTL_REG ((void *)0x01800000u)

Definition at line 20 of file iomap.h.

◆ GCNT_CNTCR

#define GCNT_CNTCR (GCNT_GLOBAL_CTRL_BASE + 0x1000)

Definition at line 50 of file iomap.h.

◆ GCNT_CNTCV_HI

#define GCNT_CNTCV_HI (GCNT_GLOBAL_CTRL_BASE + 0x2004)

Definition at line 54 of file iomap.h.

◆ GCNT_CNTCV_LO

#define GCNT_CNTCV_LO (GCNT_GLOBAL_CTRL_BASE + 0x2000)

Definition at line 53 of file iomap.h.

◆ GCNT_GLB_CNTCV_HI

#define GCNT_GLB_CNTCV_HI (GCNT_GLOBAL_CTRL_BASE + 0x100c)

Definition at line 52 of file iomap.h.

◆ GCNT_GLB_CNTCV_LO

#define GCNT_GLB_CNTCV_LO (GCNT_GLOBAL_CTRL_BASE + 0x1008)

Definition at line 51 of file iomap.h.

◆ GCNT_GLOBAL_CTRL_BASE

#define GCNT_GLOBAL_CTRL_BASE ((void *)0x004a0000u)

Definition at line 49 of file iomap.h.

◆ GCNT_PSHOLD

#define GCNT_PSHOLD ((void *)0x004AB000u)

Definition at line 56 of file iomap.h.

◆ GMEM_SYS_NOC_AXI

#define GMEM_SYS_NOC_AXI (1 << 11)

Definition at line 29 of file iomap.h.

◆ GPIO_CONFIG_ADDR

#define GPIO_CONFIG_ADDR ( x ) (TLMM_BASE_ADDR + 0x1000 * (x))

Definition at line 66 of file iomap.h.

◆ GPIO_IN_OUT_ADDR

#define GPIO_IN_OUT_ADDR ( x ) (GPIO_CONFIG_ADDR(x) + 4)

Definition at line 67 of file iomap.h.

◆ IMEM_AXI

#define IMEM_AXI (1 << 17)

Definition at line 23 of file iomap.h.

◆ MPM_AHB

#define MPM_AHB (1 << 12)

Definition at line 28 of file iomap.h.

◆ MSG_RAM_AHB

#define MSG_RAM_AHB (1 << 6)

Definition at line 34 of file iomap.h.

◆ MSM_CLK_CTL_BASE

#define MSM_CLK_CTL_BASE GCC_CLK_CTL_REG

Definition at line 21 of file iomap.h.

◆ PRNG_AHB

#define PRNG_AHB (1 << 8)

Definition at line 32 of file iomap.h.

◆ readl_i

#define readl_i ( a ) read32((const void *)(a))

Definition at line 15 of file iomap.h.

◆ RPM_FW_MAGIC_NUM

#define RPM_FW_MAGIC_NUM 0x4D505242

Definition at line 63 of file iomap.h.

◆ RPM_INT

#define RPM_INT ((void *)0x63020)

Definition at line 59 of file iomap.h.

◆ RPM_INT_ACK

#define RPM_INT_ACK ((void *)0x63060)

Definition at line 60 of file iomap.h.

◆ RPM_SIGNAL_COOKIE

#define RPM_SIGNAL_COOKIE ((void *)0x47C20)

Definition at line 61 of file iomap.h.

◆ RPM_SIGNAL_ENTRY

#define RPM_SIGNAL_ENTRY ((void *)0x47C24)

Definition at line 62 of file iomap.h.

◆ SPMI_PCNOC_AHB

#define SPMI_PCNOC_AHB (1 << 3)

Definition at line 37 of file iomap.h.

◆ SYS_NOC_APSS_AHB

#define SYS_NOC_APSS_AHB (1 << 16)

Definition at line 24 of file iomap.h.

◆ TCSR_BOOT_MISC_DETECT

#define TCSR_BOOT_MISC_DETECT ((void *)0x0193D100)

Definition at line 100 of file iomap.h.

◆ TCSR_RESET_DEBUG_SW_ENTRY

#define TCSR_RESET_DEBUG_SW_ENTRY ((void *)0x01940000)

Definition at line 101 of file iomap.h.

◆ TLMM

#define TLMM (1 << 4)

Definition at line 36 of file iomap.h.

◆ TLMM_AHB

#define TLMM_AHB (1 << 5)

Definition at line 35 of file iomap.h.

◆ TLMM_BASE_ADDR

#define TLMM_BASE_ADDR ((void *)0x01000000)

Definition at line 65 of file iomap.h.

◆ UART1_DM_BASE

#define UART1_DM_BASE ((void *)0x078af000)

Definition at line 77 of file iomap.h.

◆ UART2_DM_BASE

#define UART2_DM_BASE ((void *)0x078b0000)

Definition at line 78 of file iomap.h.

◆ USB_HOST1_DWC3_BASE

#define USB_HOST1_DWC3_BASE 0x1100C100

Definition at line 74 of file iomap.h.

◆ USB_HOST1_PHY_BASE

#define USB_HOST1_PHY_BASE 0x110F8800

Definition at line 75 of file iomap.h.

◆ USB_HOST1_XHCI_BASE

#define USB_HOST1_XHCI_BASE 0x11000000

Definition at line 73 of file iomap.h.

◆ USB_HOST2_DWC3_BASE

#define USB_HOST2_DWC3_BASE 0x1000C100

Definition at line 71 of file iomap.h.

◆ USB_HOST2_PHY_BASE

#define USB_HOST2_PHY_BASE 0x100F8800

Definition at line 72 of file iomap.h.

◆ USB_HOST2_XHCI_BASE

#define USB_HOST2_XHCI_BASE 0x10000000

Definition at line 70 of file iomap.h.

◆ writel_i

#define writel_i	(	v,
		a
	)	write32((void *)a, v)

Definition at line 16 of file iomap.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
BLSP1_UART1
BLSP1_UART2

Definition at line 80 of file iomap.h.

Function Documentation

◆ blsp_qup_base()

static void* blsp_qup_base ( blsp_qup_id_t id )

inlinestatic

Definition at line 103 of file iomap.h.

References BLSP1_QUP0_BASE, BLSP1_QUP1_BASE, BLSP1_QUP2_BASE, BLSP1_QUP3_BASE, BLSP_QUP_ID_0, BLSP_QUP_ID_1, BLSP_QUP_ID_2, BLSP_QUP_ID_3, and NULL.

Referenced by blsp_i2c_init().

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Macros

Enumerations

Functions