coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
3
#include <baseboard/gpio.h>
4
#include <baseboard/variants.h>
5
#include <
commonlib/helpers.h
>
6
7
/* Pad configuration in ramstage */
8
static
const
struct
pad_config
override_gpio_table
[] = {
9
/* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
10
PAD_CFG_GPO
(
GPP_A7
, 1, DEEP),
11
/* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
12
PAD_CFG_GPO
(
GPP_A8
, 1, DEEP),
13
/* A10 : I2S2_RXD ==> EN_SPKR_PA */
14
PAD_CFG_GPO
(
GPP_A10
, 1, DEEP),
15
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
16
PAD_CFG_GPO
(
GPP_A13
, 1, DEEP),
17
/* A16 : USB_OC3# ==> USB_C0_OC_ODL */
18
PAD_CFG_NF
(
GPP_A16
,
NONE
, DEEP, NF1),
19
/* A18 : DDSP_HPDB ==> HDMI_HPD */
20
PAD_CFG_NF
(
GPP_A18
,
NONE
, DEEP, NF1),
21
/* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
22
PAD_CFG_GPO
(
GPP_A22
, 1, DEEP),
23
/* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
24
PAD_CFG_NF
(
GPP_A23
,
NONE
, DEEP, NF1),
25
26
/* B2 : VRALERT# ==> EN_PP3300_SSD */
27
PAD_CFG_GPO
(
GPP_B2
, 1, PLTRST),
28
/* B3 : CPU_GP2 ==> PEN_DET_ODL */
29
PAD_CFG_GPI
(
GPP_B3
,
NONE
, DEEP),
30
/* B4 : CPU_GP3==> EN_PP3300_EMMC */
31
PAD_CFG_GPO
(
GPP_B4
, 1, DEEP),
32
/* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
33
PAD_CFG_NF
(
GPP_B9
,
NONE
, DEEP, NF1),
34
/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
35
PAD_CFG_NF
(
GPP_B10
,
NONE
, DEEP, NF1),
36
/* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
37
PAD_CFG_NF
(
GPP_B19
,
NONE
, DEEP, NF1),
38
/* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
39
PAD_CFG_NF
(
GPP_B20
,
NONE
, DEEP, NF1),
40
/* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
41
PAD_CFG_NF
(
GPP_B21
,
NONE
, DEEP, NF1),
42
43
/* C0 : SMBCLK ==> EN_PP3300_WLAN */
44
PAD_CFG_GPO
(
GPP_C0
, 1, DEEP),
45
/* C2 : SMBALERT# ==> GPP_C2_STRAP */
46
PAD_NC
(
GPP_C2
, DN_20K),
47
/* C3 : EMMC_PE_WAKE_ODL*/
48
PAD_CFG_GPI
(
GPP_C3
,
NONE
, DEEP),
49
/* C4 : EMMC_PERST_L*/
50
PAD_CFG_GPO
(
GPP_C4
, 1, DEEP),
51
52
/* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP_0 */
53
PAD_NC
(
GPP_C5
, DN_20K),
54
/* C10 : UART0_RTS# ==> USI_RST_L */
55
PAD_CFG_GPO
(
GPP_C10
, 0, DEEP),
56
/* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
57
PAD_CFG_NF
(
GPP_C16
,
NONE
, DEEP, NF1),
58
/* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
59
PAD_CFG_NF
(
GPP_C17
,
NONE
, DEEP, NF1),
60
/* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
61
PAD_CFG_NF
(
GPP_C18
,
NONE
, DEEP, NF1),
62
/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
63
PAD_CFG_NF
(
GPP_C19
,
NONE
, DEEP, NF1),
64
/* C20 : UART2_RXD ==> FPMCU_INT_L */
65
PAD_CFG_GPI_INT
(
GPP_C20
,
NONE
, PLTRST, LEVEL),
66
/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
67
PAD_CFG_GPO
(
GPP_C22
, 0, DEEP),
68
69
/* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */
70
PAD_CFG_NF
(
GPP_D6
,
NONE
, DEEP, NF1),
71
/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
72
PAD_CFG_NF
(
GPP_D8
,
NONE
, DEEP, NF1),
73
/* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MOSI_STRAP */
74
PAD_CFG_NF
(
GPP_D12
, DN_20K, DEEP, NF7),
75
/* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */
76
PAD_CFG_NF
(
GPP_D13
,
NONE
, DEEP, NF1),
77
/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
78
PAD_CFG_NF
(
GPP_D14
,
NONE
, DEEP, NF1),
79
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
80
PAD_CFG_GPO
(
GPP_D16
, 1, DEEP),
81
/* D17 : ISH_GP4 ==> EN_FCAM_PWR */
82
PAD_CFG_GPO
(
GPP_D17
, 1, DEEP),
83
84
/* E1 : SPI1_IO2 ==> PEN_DET_ODL */
85
PAD_CFG_GPI_SCI_LOW
(
GPP_E1
,
NONE
, DEEP, EDGE_SINGLE),
86
/* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
87
PAD_CFG_GPI
(
GPP_E2
,
NONE
, DEEP),
88
/* E3 : CPU_GP0 ==> USI_REPORT_EN */
89
PAD_CFG_GPO
(
GPP_E3
, 0, DEEP),
90
/* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
91
PAD_CFG_GPI
(
GPP_E4
,
NONE
, DEEP),
92
/* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */
93
PAD_CFG_GPI
(
GPP_E6
,
NONE
, DEEP),
94
/* E7 : CPU_GP1 ==> USI_INT */
95
PAD_CFG_GPI_APIC
(
GPP_E7
,
NONE
, PLTRST, LEVEL,
NONE
),
96
/* E8 : SPI1_CS1# ==> SLP_S0IX */
97
PAD_CFG_GPO
(
GPP_E8
, 0, DEEP),
98
/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
99
PAD_CFG_GPI
(
GPP_E11
,
NONE
, DEEP),
100
/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
101
PAD_CFG_GPI_IRQ_WAKE(
GPP_E15
,
NONE
, DEEP, LEVEL, INVERT),
102
/* E18 : DDP1_CTRLCLK ==> NC */
103
PAD_NC
(
GPP_E18
,
NONE
),
104
/* E20 : DDP2_CTRLCLK ==> NC */
105
PAD_NC
(
GPP_E20
,
NONE
),
106
/* E21 : DDP2_CTRLDATA ==> NC */
107
PAD_NC
(
GPP_E21
,
NONE
),
108
109
/* F7 : GPPF7_STRAP ==> GPP_F7_STRAP */
110
PAD_NC
(
GPP_F7
, DN_20K),
111
/* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */
112
PAD_CFG_GPI_INT
(
GPP_F8
,
NONE
, PLTRST, EDGE_BOTH),
113
/* F11 : THC1_SPI2_CLK ==> NC */
114
PAD_NC
(
GPP_F11
,
NONE
),
115
/* F12 : GSXDOUT ==> NC */
116
PAD_NC
(
GPP_F12
,
NONE
),
117
118
/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
119
PAD_CFG_GPO
(
GPP_F13
, 1, DEEP),
120
/* F19 : SRCCLKREQ6# ==> WLAN_INT_L */
121
PAD_CFG_GPI_SCI_LOW
(
GPP_F19
,
NONE
, DEEP, EDGE_SINGLE),
122
123
/* H0 : GPPH0_BOOT_STRAP1 */
124
PAD_NC
(
GPP_H0
, DN_20K),
125
/* H1 : GPPH1_BOOT_STRAP2 */
126
PAD_NC
(
GPP_H1
, DN_20K),
127
/* H2 : GPPH2_BOOT_STRAP3 */
128
PAD_NC
(
GPP_H2
, DN_20K),
129
/* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
130
PAD_CFG_GPO
(
GPP_H3
, 1, DEEP),
131
/* H10 : SRCCLKREQ4# ==> WLAN_PERST_L*/
132
PAD_CFG_GPO
(
GPP_H10
, 1, DEEP),
133
/* H11 : SRCCLKREQ5# ==> EMMC_CLKREQ_ODL*/
134
PAD_CFG_NF
(
GPP_H11
,
NONE
, DEEP, NF1),
135
/* H16 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
136
PAD_CFG_NF
(
GPP_H16
,
NONE
, DEEP, NF1),
137
/* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */
138
PAD_CFG_NF
(
GPP_H17
,
NONE
, DEEP, NF1),
139
/* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */
140
PAD_CFG_GPI
(
GPP_H19
,
NONE
, DEEP),
141
142
/* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
143
PAD_CFG_NF
(
GPP_R0
,
NONE
, DEEP, NF2),
144
/* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
145
PAD_CFG_NF
(
GPP_R1
,
NONE
, DEEP, NF2),
146
/* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
147
PAD_CFG_NF
(
GPP_R2
, DN_20K, DEEP, NF2),
148
/* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
149
PAD_CFG_NF
(
GPP_R3
,
NONE
, DEEP, NF2),
150
/* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */
151
PAD_CFG_NF
(
GPP_R5
,
NONE
, DEEP, NF2),
152
/* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */
153
PAD_CFG_NF
(
GPP_R6
,
NONE
, DEEP, NF2),
154
/* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */
155
PAD_CFG_NF
(
GPP_R7
,
NONE
, DEEP, NF2),
156
157
/* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */
158
PAD_CFG_NF
(
GPP_S0
,
NONE
, DEEP, NF1),
159
/* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */
160
PAD_CFG_NF
(
GPP_S1
,
NONE
, DEEP, NF1),
161
/* S6 : SNDW3_CLK ==> DMIC_CLK0 */
162
PAD_CFG_NF
(
GPP_S6
,
NONE
, DEEP, NF2),
163
/* S7 : SNDW3_DATA ==> DMIC_DATA0 */
164
PAD_CFG_NF
(
GPP_S7
,
NONE
, DEEP, NF2),
165
166
/* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
167
PAD_CFG_NF
(
GPD9
,
NONE
, DEEP, NF1),
168
169
};
170
171
/* Early pad configuration in bootblock */
172
static
const
struct
pad_config
early_gpio_table
[] = {
173
/* C8 : UART0 RX */
174
PAD_CFG_NF
(
GPP_C8
,
NONE
, DEEP, NF1),
175
/* C9 : UART0 TX */
176
PAD_CFG_NF
(
GPP_C9
,
NONE
, DEEP, NF1),
177
178
/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
179
PAD_CFG_NF
(
GPP_A12
,
NONE
, DEEP, NF1),
180
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
181
/* assert reset on reboot */
182
PAD_CFG_GPO
(
GPP_A13
, 0, DEEP),
183
/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
184
PAD_CFG_GPI
(
GPP_A17
,
NONE
, DEEP),
185
/* B2 : VRALERT# ==> EN_PP3300_SSD */
186
PAD_CFG_GPO
(
GPP_B2
, 1, PLTRST),
187
/* B4 : CPU_GP3==> EN_PP3300_EMMC */
188
PAD_CFG_GPO
(
GPP_B4
, 1, DEEP),
189
190
191
/* B11 : PMCALERT# ==> PCH_WP_OD */
192
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_B11
,
NONE
, DEEP),
193
/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
194
PAD_CFG_NF
(
GPP_B15
,
NONE
, DEEP, NF1),
195
/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
196
PAD_CFG_NF
(
GPP_B16
,
NONE
, DEEP, NF1),
197
/* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
198
PAD_CFG_NF
(
GPP_B17
,
NONE
, DEEP, NF1),
199
/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
200
PAD_CFG_NF
(
GPP_B18
, DN_20K, DEEP, NF1),
201
202
/* C0 : SMBCLK ==> EN_PP3300_WLAN */
203
PAD_CFG_GPO
(
GPP_C0
, 1, DEEP),
204
/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
205
PAD_CFG_GPI_APIC
(
GPP_C21
,
NONE
, PLTRST, LEVEL, INVERT),
206
/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
207
PAD_CFG_GPO
(
GPP_C22
, 0, DEEP),
208
209
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
210
PAD_CFG_GPO
(
GPP_D16
, 1, DEEP),
211
212
/* H10 : SRCCLKREQ5# ==> WLAN_PERST_L */
213
PAD_CFG_GPO
(
GPP_H10
, 1, DEEP),
214
};
215
216
const
struct
pad_config
*
variant_override_gpio_table
(
size_t
*num)
217
{
218
*num =
ARRAY_SIZE
(
override_gpio_table
);
219
return
override_gpio_table
;
220
}
221
222
const
struct
pad_config
*
variant_early_gpio_table
(
size_t
*num)
223
{
224
*num =
ARRAY_SIZE
(
early_gpio_table
);
225
return
early_gpio_table
;
226
}
GPP_H19
#define GPP_H19
Definition:
gpio_soc_defs.h:235
GPD9
#define GPD9
Definition:
gpio_soc_defs.h:390
GPP_C2
#define GPP_C2
Definition:
gpio_soc_defs.h:539
GPP_D8
#define GPP_D8
Definition:
gpio_soc_defs.h:260
GPP_D17
#define GPP_D17
Definition:
gpio_soc_defs.h:269
GPP_E3
#define GPP_E3
Definition:
gpio_soc_defs.h:631
GPP_A18
#define GPP_A18
Definition:
gpio_soc_defs.h:137
GPP_F12
#define GPP_F12
Definition:
gpio_soc_defs.h:585
GPP_H16
#define GPP_H16
Definition:
gpio_soc_defs.h:232
GPP_R7
#define GPP_R7
Definition:
gpio_soc_defs.h:676
GPP_D14
#define GPP_D14
Definition:
gpio_soc_defs.h:266
GPP_S0
#define GPP_S0
Definition:
gpio_soc_defs.h:160
GPP_C5
#define GPP_C5
Definition:
gpio_soc_defs.h:542
GPP_H11
#define GPP_H11
Definition:
gpio_soc_defs.h:227
GPP_H17
#define GPP_H17
Definition:
gpio_soc_defs.h:233
GPP_D12
#define GPP_D12
Definition:
gpio_soc_defs.h:264
GPP_B16
#define GPP_B16
Definition:
gpio_soc_defs.h:69
GPP_B2
#define GPP_B2
Definition:
gpio_soc_defs.h:55
GPP_R3
#define GPP_R3
Definition:
gpio_soc_defs.h:672
GPP_E6
#define GPP_E6
Definition:
gpio_soc_defs.h:634
GPP_D6
#define GPP_D6
Definition:
gpio_soc_defs.h:258
GPP_C9
#define GPP_C9
Definition:
gpio_soc_defs.h:546
GPP_H2
#define GPP_H2
Definition:
gpio_soc_defs.h:218
GPP_C22
#define GPP_C22
Definition:
gpio_soc_defs.h:559
GPP_R6
#define GPP_R6
Definition:
gpio_soc_defs.h:675
GPP_R0
#define GPP_R0
Definition:
gpio_soc_defs.h:669
GPP_B15
#define GPP_B15
Definition:
gpio_soc_defs.h:68
GPP_C8
#define GPP_C8
Definition:
gpio_soc_defs.h:545
GPP_S7
#define GPP_S7
Definition:
gpio_soc_defs.h:167
GPP_H1
#define GPP_H1
Definition:
gpio_soc_defs.h:217
GPP_A23
#define GPP_A23
Definition:
gpio_soc_defs.h:142
GPP_C18
#define GPP_C18
Definition:
gpio_soc_defs.h:555
GPP_C17
#define GPP_C17
Definition:
gpio_soc_defs.h:554
GPP_E8
#define GPP_E8
Definition:
gpio_soc_defs.h:636
GPP_A7
#define GPP_A7
Definition:
gpio_soc_defs.h:126
GPP_S1
#define GPP_S1
Definition:
gpio_soc_defs.h:161
GPP_C20
#define GPP_C20
Definition:
gpio_soc_defs.h:557
GPP_B20
#define GPP_B20
Definition:
gpio_soc_defs.h:73
GPP_A16
#define GPP_A16
Definition:
gpio_soc_defs.h:135
GPP_A12
#define GPP_A12
Definition:
gpio_soc_defs.h:131
GPP_C10
#define GPP_C10
Definition:
gpio_soc_defs.h:547
GPP_E7
#define GPP_E7
Definition:
gpio_soc_defs.h:635
GPP_C16
#define GPP_C16
Definition:
gpio_soc_defs.h:553
GPP_F7
#define GPP_F7
Definition:
gpio_soc_defs.h:580
GPP_F13
#define GPP_F13
Definition:
gpio_soc_defs.h:586
GPP_C4
#define GPP_C4
Definition:
gpio_soc_defs.h:541
GPP_S6
#define GPP_S6
Definition:
gpio_soc_defs.h:166
GPP_B19
#define GPP_B19
Definition:
gpio_soc_defs.h:72
GPP_E2
#define GPP_E2
Definition:
gpio_soc_defs.h:630
GPP_H0
#define GPP_H0
Definition:
gpio_soc_defs.h:215
GPP_C21
#define GPP_C21
Definition:
gpio_soc_defs.h:558
GPP_R2
#define GPP_R2
Definition:
gpio_soc_defs.h:671
GPP_B9
#define GPP_B9
Definition:
gpio_soc_defs.h:62
GPP_E18
#define GPP_E18
Definition:
gpio_soc_defs.h:646
GPP_H3
#define GPP_H3
Definition:
gpio_soc_defs.h:219
GPP_A10
#define GPP_A10
Definition:
gpio_soc_defs.h:129
GPP_A8
#define GPP_A8
Definition:
gpio_soc_defs.h:127
GPP_B11
#define GPP_B11
Definition:
gpio_soc_defs.h:64
GPP_D13
#define GPP_D13
Definition:
gpio_soc_defs.h:265
GPP_B18
#define GPP_B18
Definition:
gpio_soc_defs.h:71
GPP_R5
#define GPP_R5
Definition:
gpio_soc_defs.h:674
GPP_E20
#define GPP_E20
Definition:
gpio_soc_defs.h:648
GPP_F8
#define GPP_F8
Definition:
gpio_soc_defs.h:581
GPP_C19
#define GPP_C19
Definition:
gpio_soc_defs.h:556
GPP_A13
#define GPP_A13
Definition:
gpio_soc_defs.h:132
GPP_E15
#define GPP_E15
Definition:
gpio_soc_defs.h:643
GPP_B10
#define GPP_B10
Definition:
gpio_soc_defs.h:63
GPP_E11
#define GPP_E11
Definition:
gpio_soc_defs.h:639
GPP_B3
#define GPP_B3
Definition:
gpio_soc_defs.h:56
GPP_A22
#define GPP_A22
Definition:
gpio_soc_defs.h:141
GPP_F11
#define GPP_F11
Definition:
gpio_soc_defs.h:584
GPP_B21
#define GPP_B21
Definition:
gpio_soc_defs.h:74
GPP_B4
#define GPP_B4
Definition:
gpio_soc_defs.h:57
GPP_D16
#define GPP_D16
Definition:
gpio_soc_defs.h:268
GPP_H10
#define GPP_H10
Definition:
gpio_soc_defs.h:226
GPP_E21
#define GPP_E21
Definition:
gpio_soc_defs.h:649
GPP_C3
#define GPP_C3
Definition:
gpio_soc_defs.h:540
GPP_A17
#define GPP_A17
Definition:
gpio_soc_defs.h:136
GPP_B17
#define GPP_B17
Definition:
gpio_soc_defs.h:70
GPP_E4
#define GPP_E4
Definition:
gpio_soc_defs.h:632
GPP_C0
#define GPP_C0
Definition:
gpio_soc_defs.h:537
GPP_E1
#define GPP_E1
Definition:
gpio_soc_defs.h:629
GPP_F19
#define GPP_F19
Definition:
gpio_soc_defs.h:592
GPP_R1
#define GPP_R1
Definition:
gpio_soc_defs.h:670
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
helpers.h
variant_early_gpio_table
const struct pad_config * variant_early_gpio_table(size_t *num)
Definition:
gpio.c:204
variant_override_gpio_table
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
Definition:
gpio.c:450
override_gpio_table
static const struct pad_config override_gpio_table[]
Definition:
gpio.c:8
early_gpio_table
static const struct pad_config early_gpio_table[]
Definition:
gpio.c:172
NONE
@ NONE
Definition:
qup_se_handlers_common.h:196
PAD_NC
#define PAD_NC(pin)
Definition:
gpio_defs.h:263
PAD_CFG_GPI
#define PAD_CFG_GPI(pad, pull, rst)
Definition:
gpio_defs.h:284
PAD_CFG_GPI_SCI_LOW
#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig)
Definition:
gpio_defs.h:452
PAD_CFG_NF
#define PAD_CFG_NF(pad, pull, rst, func)
Definition:
gpio_defs.h:197
PAD_CFG_GPI_INT
#define PAD_CFG_GPI_INT(pad, pull, rst, trig)
Definition:
gpio_defs.h:348
PAD_CFG_GPI_APIC
#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:376
PAD_CFG_GPO
#define PAD_CFG_GPO(pad, val, rst)
Definition:
gpio_defs.h:247
PAD_CFG_GPI_GPIO_DRIVER
#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst)
Definition:
gpio_defs.h:323
pad_config
Definition:
gpio.h:75
src
mainboard
google
volteer
variants
chronicler
gpio.c
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