coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
mt6315.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <soc/mt6315.h>
4 
5 static const struct mt6315_setting init_setting_cpu[] = {
6  /* disable magic key protection */
7  {0x3A9, 0x63, 0xFF, 0},
8  {0x3A8, 0x15, 0xFF, 0},
9  {0x3A0, 0x9C, 0xFF, 0},
10  {0x39F, 0xEA, 0xFF, 0},
11  {0x993, 0x47, 0xFF, 0},
12  {0x992, 0x29, 0xFF, 0},
13  {0x1418, 0x55, 0xFF, 0},
14  {0x1417, 0x43, 0xFF, 0},
15  {0x3A2, 0x2A, 0xFF, 0},
16  {0x3A1, 0x7C, 0xFF, 0},
17  /* init setting */
18  {0x13, 0x2, 0x2, 0},
19  {0x15, 0x1F, 0x1F, 0},
20  {0x22, 0x12, 0x12, 0},
21  {0x8A, 0x6, 0xF, 0},
22  {0x10B, 0x3, 0x3, 0},
23  {0x38B, 0x4, 0xFF, 0},
24  {0xA07, 0x0, 0x1, 0},
25  {0xA1A, 0x1F, 0x1F, 0},
26  {0x1457, 0x0, 0xFF, 0},
27  {0x997, 0x7, 0x7F, 0},
28  {0x999, 0xF0, 0xF0, 0},
29  {0x9A0, 0x1, 0x1F, 0},
30  {0x9A1, 0x1, 0x1F, 0},
31  {0x9A2, 0x0, 0x1F, 0},
32  {0x9A3, 0x1, 0x1F, 0},
33  {0x1440, 0x0, 0xA, 0},
34  {0x1487, 0x58, 0xFF, 0},
35  {0x148B, 0x1, 0x7F, 0},
36  {0x148C, 0x2, 0x7F, 0},
37  {0x1507, 0x58, 0xFF, 0},
38  {0x150B, 0x1, 0x7F, 0},
39  {0x150C, 0x2, 0x7F, 0},
40  {0x1587, 0x58, 0xFF, 0},
41  {0x158B, 0x1, 0x7F, 0},
42  {0x158C, 0x4, 0x7F, 0},
43  {0x1607, 0x58, 0xFF, 0},
44  {0x160B, 0x1, 0x7F, 0},
45  {0x160C, 0x2, 0x7F, 0},
46  {0x1687, 0x22, 0x76, 0},
47  {0x1688, 0xE, 0x2F, 0},
48  {0x1689, 0xA1, 0xE1, 0},
49  {0x168A, 0x79, 0x7F, 0},
50  {0x168B, 0x12, 0x3F, 0},
51  {0x168D, 0x0, 0xC, 0},
52  {0x168E, 0xD7, 0xFF, 0},
53  {0x168F, 0x81, 0xFF, 0},
54  {0x1690, 0x13, 0x3F, 0},
55  {0x1691, 0x22, 0x76, 0},
56  {0x1692, 0xE, 0x2F, 0},
57  {0x1693, 0xA1, 0xE1, 0},
58  {0x1694, 0x79, 0x7F, 0},
59  {0x1695, 0x12, 0x3F, 0},
60  {0x1697, 0x0, 0xC, 0},
61  {0x1698, 0xD7, 0xFF, 0},
62  {0x1699, 0x81, 0xFF, 0},
63  {0x169A, 0x13, 0x3F, 0},
64  {0x169B, 0x20, 0x70, 0},
65  {0x169C, 0xE, 0x2F, 0},
66  {0x169D, 0x80, 0xC1, 0},
67  {0x169E, 0xF8, 0xF8, 0},
68  {0x169F, 0x12, 0x3F, 0},
69  {0x16A1, 0x0, 0xC, 0},
70  {0x16A2, 0xDB, 0xFF, 0},
71  {0x16A3, 0xA1, 0xFF, 0},
72  {0x16A4, 0x1, 0xF, 0},
73  {0x16A5, 0x22, 0x76, 0},
74  {0x16A6, 0xE, 0x2F, 0},
75  {0x16A7, 0xA1, 0xE1, 0},
76  {0x16A8, 0x79, 0xFF, 0},
77  {0x16A9, 0x12, 0x3F, 0},
78  {0x16AB, 0x0, 0xC, 0},
79  {0x16AC, 0xD7, 0xFF, 0},
80  {0x16AD, 0x81, 0xFF, 0},
81  {0x16AE, 0x13, 0x3F, 0},
82  /* reset sequence off to zero */
83  {0x139, 0, 0x1, 0},
84  /* enable magic key protection */
85  {0x3A1, 0, 0xFF, 0},
86  {0x3A2, 0, 0xFF, 0},
87  {0x1417, 0, 0xFF, 0},
88  {0x1418, 0, 0xFF, 0},
89  {0x992, 0, 0xFF, 0},
90  {0x993, 0, 0xFF, 0},
91  {0x39F, 0, 0xFF, 0},
92  {0x3A0, 0, 0xFF, 0},
93  {0x3A8, 0, 0xFF, 0},
94  {0x3A9, 0, 0xFF, 0},
95 };
96 
97 static const struct mt6315_setting init_setting_gpu[] = {
98  /* disable magic key protection */
99  {0x3A9, 0x63, 0xFF, 0},
100  {0x3A8, 0x15, 0xFF, 0},
101  {0x3A0, 0x9C, 0xFF, 0},
102  {0x39F, 0xEA, 0xFF, 0},
103  {0x993, 0x47, 0xFF, 0},
104  {0x992, 0x29, 0xFF, 0},
105  {0x1418, 0x55, 0xFF, 0},
106  {0x1417, 0x43, 0xFF, 0},
107  {0x3a2, 0x2A, 0xFF, 0},
108  {0x3a1, 0x7C, 0xFF, 0},
109  /* init setting */
110  {0x13, 0x2, 0x2, 0},
111  {0x15, 0x1F, 0x1F, 0},
112  {0x22, 0x12, 0x12, 0},
113  {0x8A, 0x6, 0xF, 0},
114  {0x10B, 0x3, 0x3, 0},
115  {0x38B, 0x4, 0xFF, 0},
116  {0xA07, 0x0, 0x1, 0},
117  {0xA1A, 0x1F, 0x1F, 0},
118  {0x1457, 0x0, 0xFF, 0},
119  {0x997, 0x2F, 0x7F, 0},
120  {0x999, 0xF0, 0xF0, 0},
121  {0x9A0, 0x0, 0x1F, 0},
122  {0x9A1, 0x0, 0x1F, 0},
123  {0x9A2, 0xB, 0x1F, 0},
124  {0x9A3, 0x0, 0x1F, 0},
125  {0x1440, 0x0, 0xA, 0},
126  {0x1487, 0x58, 0xFF, 0},
127  {0x148B, 0x1, 0x7F, 0},
128  {0x148C, 0x4, 0x7F, 0},
129  {0x1507, 0x58, 0xFF, 0},
130  {0x150B, 0x1, 0x7F, 0},
131  {0x150C, 0x4, 0x7F, 0},
132  {0x1587, 0x58, 0xFF, 0},
133  {0x158B, 0x1, 0x7F, 0},
134  {0x158C, 0x4, 0x7F, 0},
135  {0x1607, 0x58, 0xFF, 0},
136  {0x160B, 0x1, 0x7F, 0},
137  {0x160C, 0x4, 0x7F, 0},
138  {0x1687, 0x22, 0x76, 0},
139  {0x1688, 0xE, 0x2F, 0},
140  {0x1689, 0xA1, 0xE1, 0},
141  {0x168A, 0x79, 0x7F, 0},
142  {0x168B, 0x12, 0x3F, 0},
143  {0x168D, 0x0, 0xC, 0},
144  {0x168E, 0xD7, 0xFF, 0},
145  {0x168F, 0x81, 0xFF, 0},
146  {0x1690, 0x13, 0x3F, 0},
147  {0x1691, 0x22, 0x76, 0},
148  {0x1692, 0xE, 0x2F, 0},
149  {0x1693, 0xA1, 0xE1, 0},
150  {0x1694, 0x79, 0x7F, 0},
151  {0x1695, 0x12, 0x3F, 0},
152  {0x1697, 0x0, 0xC, 0},
153  {0x1698, 0xD7, 0xFF, 0},
154  {0x1699, 0x81, 0xFF, 0},
155  {0x169A, 0x13, 0x3F, 0},
156  {0x169B, 0x22, 0x76, 0},
157  {0x169C, 0xE, 0x2F, 0},
158  {0x169D, 0xA1, 0xE1, 0},
159  {0x169E, 0x79, 0x7F, 0},
160  {0x169F, 0x12, 0x3F, 0},
161  {0x16A1, 0x0, 0xC, 0},
162  {0x16A2, 0xD7, 0xFF, 0},
163  {0x16A3, 0x81, 0xFF, 0},
164  {0x16A4, 0x13, 0x3F, 0},
165  {0x16A5, 0x22, 0x76, 0},
166  {0x16A6, 0xE, 0x2F, 0},
167  {0x16A7, 0xA1, 0xE1, 0},
168  {0x16A8, 0x79, 0xFF, 0},
169  {0x16A9, 0x12, 0x3F, 0},
170  {0x16AB, 0x0, 0xC, 0},
171  {0x16AC, 0xD7, 0xFF, 0},
172  {0x16AD, 0x81, 0xFF, 0},
173  {0x16AE, 0x13, 0x3F, 0},
174  /* Don't remove this! it's MT6315 for GPU only to disable VBUCK3 */
175  {0x1440, 0x0, 0x4, 0},
176  /* reset sequence off to zero */
177  {0x139, 0, 0x1, 0},
178  /* enable magic key protection */
179  {0x3A1, 0, 0xFF, 0},
180  {0x3A2, 0, 0xFF, 0},
181  {0x1417, 0, 0xFF, 0},
182  {0x1418, 0, 0xFF, 0},
183  {0x992, 0, 0xFF, 0},
184  {0x993, 0, 0xFF, 0},
185  {0x39F, 0, 0xFF, 0},
186  {0x3A0, 0, 0xFF, 0},
187  {0x3A8, 0, 0xFF, 0},
188  {0x3A9, 0, 0xFF, 0},
189 };
190 
191 void mt6315_init_setting(void)
192 {
193  for (int i = 0; i < ARRAY_SIZE(init_setting_cpu); i++)
194  mt6315_write_field(MT6315_CPU,
195  init_setting_cpu[i].addr, init_setting_cpu[i].val,
196  init_setting_cpu[i].mask, init_setting_cpu[i].shift);
197 
198  for (int i = 0; i < ARRAY_SIZE(init_setting_gpu); i++)
199  mt6315_write_field(MT6315_GPU,
200  init_setting_gpu[i].addr, init_setting_gpu[i].val,
201  init_setting_gpu[i].mask, init_setting_gpu[i].shift);
202 }
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition: helpers.h:12
addr
static u32 addr
Definition: cirrus.c:14
mt6315_write_field
void mt6315_write_field(u32 slvid, u32 reg, u32 val, u32 mask, u32 shift)
Definition: mt6315.c:20
MT6315_GPU
@ MT6315_GPU
Definition: mt6315.h:18
MT6315_CPU
@ MT6315_CPU
Definition: mt6315.h:17
mt6315_init_setting
void mt6315_init_setting(void)
Definition: mt6315.c:191
init_setting_cpu
static const struct mt6315_setting init_setting_cpu[]
Definition: mt6315.c:5
init_setting_gpu
static const struct mt6315_setting init_setting_gpu[]
Definition: mt6315.c:97
mask
static const int mask[4]
Definition: gpio.c:308
mt6315_setting
Definition: mt6315.h:9
mt6315_setting::shift
unsigned char shift
Definition: mt6315.h:13
val
u8 val
Definition: sys.c:300