coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
bootblock.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
bootblock_common.h
>
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#include <
device/mmio.h
>
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#include <
gpio.h
>
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#include <soc/gpio.h>
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#include <soc/i2c.h>
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#include <soc/pcie.h>
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#include <soc/spi.h>
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#include "
gpio.h
"
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struct
pad_func
{
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u8
pin_id
;
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u8
func
;
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};
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#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func}
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static
void
nor_set_gpio_pinmux
(
void
)
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{
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const
struct
pad_func
*ptr =
NULL
;
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/* GPIO 140 ~ 143 */
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struct
pad_func
nor_pinmux
[] = {
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PAD_FUNC
(SPIM2_CSB, SPINOR_CS),
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PAD_FUNC
(SPIM2_CLK, SPINOR_CK),
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PAD_FUNC
(SPIM2_MO, SPINOR_IO0),
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PAD_FUNC
(SPIM2_MI, SPINOR_IO1),
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};
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ptr =
nor_pinmux
;
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for
(
size_t
i = 0; i <
ARRAY_SIZE
(
nor_pinmux
); i++) {
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gpio_set_pull
((
gpio_t
){.id = ptr[i].
pin_id
},
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GPIO_PULL_ENABLE
,
GPIO_PULL_UP
);
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gpio_set_mode
((
gpio_t
){.id = ptr[i].
pin_id
}, ptr[i].
func
);
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}
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}
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static
void
usb3_hub_reset
(
void
)
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{
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gpio_output
(
GPIO
(DGI_D7), 1);
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}
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void
bootblock_mainboard_init
(
void
)
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{
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/*
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* Initialize PCIe pinmux and assert PERST# early to reduce
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* the impact of 100ms delay.
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*/
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if
(
CONFIG
(PCI))
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mtk_pcie_pre_init
();
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mtk_i2c_bus_init
(CONFIG_DRIVER_TPM_I2C_BUS,
I2C_SPEED_FAST
);
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mtk_spi_init
(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS,
SPI_PAD0_MASK
, 3 *
MHz
, 0);
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nor_set_gpio_pinmux
();
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setup_chromeos_gpios
();
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gpio_eint_configure
(
GPIO_GSC_AP_INT
,
IRQ_TYPE_EDGE_RISING
);
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usb3_hub_reset
();
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}
bootblock_common.h
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
MHz
#define MHz
Definition:
helpers.h:80
GPIO
@ GPIO
Definition:
chip.h:84
CONFIG
@ CONFIG
Definition:
dsi_common.h:201
setup_chromeos_gpios
void setup_chromeos_gpios(void)
Definition:
chromeos.c:10
I2C_SPEED_FAST
@ I2C_SPEED_FAST
Definition:
i2c.h:45
mmio.h
gpio_output
void gpio_output(gpio_t gpio, int value)
Definition:
gpio.c:194
bootblock_mainboard_init
__weak void bootblock_mainboard_init(void)
Definition:
bootblock.c:19
nor_set_gpio_pinmux
static void nor_set_gpio_pinmux(void)
Definition:
bootblock.c:20
usb3_hub_reset
static void usb3_hub_reset(void)
Definition:
bootblock.c:40
PAD_FUNC
#define PAD_FUNC(name, func)
Definition:
bootblock.c:18
GPIO_GSC_AP_INT
#define GPIO_GSC_AP_INT
Definition:
gpio.h:14
IRQ_TYPE_EDGE_RISING
@ IRQ_TYPE_EDGE_RISING
Definition:
gpio_common.h:55
GPIO_PULL_ENABLE
@ GPIO_PULL_ENABLE
Definition:
gpio_common.h:13
gpio_set_pull
void gpio_set_pull(gpio_t gpio, enum pull_enable enable, enum pull_select select)
Definition:
gpio.c:17
mtk_pcie_pre_init
void mtk_pcie_pre_init(void)
Definition:
pcie.c:70
gpio_set_mode
void gpio_set_mode(gpio_t gpio, int mode)
Definition:
gpio.c:45
gpio_eint_configure
void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type)
Definition:
gpio.c:142
mtk_i2c_bus_init
void mtk_i2c_bus_init(uint8_t bus)
Definition:
i2c.c:65
nor_pinmux
static const struct pad_func nor_pinmux[SPI_NOR_GPIO_SET_NUM][4]
Definition:
spi.c:124
GPIO_PULL_UP
#define GPIO_PULL_UP
Definition:
gpio.h:24
gpio.h
SPI_PAD0_MASK
@ SPI_PAD0_MASK
Definition:
spi_common.h:46
mtk_spi_init
void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, unsigned int speed_hz, unsigned int tick_dly)
Definition:
spi.c:56
NULL
#define NULL
Definition:
stddef.h:19
u8
uint8_t u8
Definition:
stdint.h:45
gpio_t
Definition:
gpio_base.h:7
pad_func
Definition:
bootblock.c:13
pad_func::func
u8 func
Definition:
bootblock.c:15
pad_func::pin_id
u8 pin_id
Definition:
bootblock.c:14
src
mainboard
google
cherry
bootblock.c
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