![]() |
coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
|
Go to the source code of this file.
Macros | |
#define | _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) |
#define | _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) |
#define | _PORT(port, a, b) ((a) + (port)*((b)-(a))) |
#define | _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) |
#define | _MASKED_BIT_DISABLE(a) ((a) << 16) |
#define | INTEL_GMCH_CTRL 0x52 |
#define | INTEL_GMCH_VGA_DISABLE (1 << 1) |
#define | SNB_GMCH_CTRL 0x50 |
#define | SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */ |
#define | SNB_GMCH_GGMS_MASK 0x3 |
#define | SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */ |
#define | SNB_GMCH_GMS_MASK 0x1f |
#define | IVB_GMCH_GMS_SHIFT 4 |
#define | IVB_GMCH_GMS_MASK 0xf |
#define | HPLLCC 0xc0 /* 855 only */ |
#define | GC_CLOCK_CONTROL_MASK (0xf << 0) |
#define | GC_CLOCK_133_200 (0 << 0) |
#define | GC_CLOCK_100_200 (1 << 0) |
#define | GC_CLOCK_100_133 (2 << 0) |
#define | GC_CLOCK_166_250 (3 << 0) |
#define | GCFGC2 0xda |
#define | GCFGC 0xf0 /* 915+ only */ |
#define | GC_LOW_FREQUENCY_ENABLE (1 << 7) |
#define | GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) |
#define | GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) |
#define | GC_DISPLAY_CLOCK_MASK (7 << 4) |
#define | GM45_GC_RENDER_CLOCK_MASK (0xf << 0) |
#define | GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) |
#define | GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) |
#define | GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) |
#define | GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) |
#define | I965_GC_RENDER_CLOCK_MASK (0xf << 0) |
#define | I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) |
#define | I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) |
#define | I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) |
#define | I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) |
#define | I945_GC_RENDER_CLOCK_MASK (7 << 0) |
#define | I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) |
#define | I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) |
#define | I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) |
#define | I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) |
#define | I915_GC_RENDER_CLOCK_MASK (7 << 0) |
#define | I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) |
#define | I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) |
#define | I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) |
#define | LBB 0xf4 |
#define | I965_GDRST 0xc0 /* PCI config register */ |
#define | ILK_GDSR 0x2ca4 /* MCHBAR offset */ |
#define | GRDOM_FULL (0<<2) |
#define | GRDOM_RENDER (1<<2) |
#define | GRDOM_MEDIA (3<<2) |
#define | GRDOM_RESET_ENABLE (1<<0) |
#define | GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ |
#define | GEN6_MBC_SNPCR_SHIFT 21 |
#define | GEN6_MBC_SNPCR_MASK (3<<21) |
#define | GEN6_MBC_SNPCR_MAX (0<<21) |
#define | GEN6_MBC_SNPCR_MED (1<<21) |
#define | GEN6_MBC_SNPCR_LOW (2<<21) |
#define | GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ |
#define | GEN6_MBCTL 0x0907c |
#define | GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) |
#define | GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) |
#define | GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) |
#define | GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) |
#define | GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) |
#define | GEN6_GDRST 0x941c |
#define | GEN6_GRDOM_FULL (1 << 0) |
#define | GEN6_GRDOM_RENDER (1 << 1) |
#define | GEN6_GRDOM_MEDIA (1 << 2) |
#define | GEN6_GRDOM_BLT (1 << 3) |
#define | RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) |
#define | RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) |
#define | RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) |
#define | PP_DIR_DCLV_2G 0xffffffff |
#define | GAM_ECOCHK 0x4090 |
#define | ECOCHK_SNB_BIT (1<<10) |
#define | ECOCHK_PPGTT_CACHE64B (0x3<<3) |
#define | ECOCHK_PPGTT_CACHE4B (0x0<<3) |
#define | GAC_ECO_BITS 0x14090 |
#define | ECOBITS_PPGTT_CACHE64B (3<<8) |
#define | ECOBITS_PPGTT_CACHE4B (0<<8) |
#define | GAB_CTL 0x24000 |
#define | GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) |
#define | VGA_ST01_MDA 0x3ba |
#define | VGA_ST01_CGA 0x3da |
#define | VGA_MSR_WRITE 0x3c2 |
#define | VGA_MSR_READ 0x3cc |
#define | VGA_MSR_MEM_EN (1<<1) |
#define | VGA_MSR_CGA_MODE (1<<0) |
#define | VGA_SR_INDEX 0x3c4 |
#define | VGA_SR_DATA 0x3c5 |
#define | VGA_AR_INDEX 0x3c0 |
#define | VGA_AR_VID_EN (1<<5) |
#define | VGA_AR_DATA_WRITE 0x3c0 |
#define | VGA_AR_DATA_READ 0x3c1 |
#define | VGA_GR_INDEX 0x3ce |
#define | VGA_GR_DATA 0x3cf |
#define | VGA_GR_MEM_READ_MODE_SHIFT 3 |
#define | VGA_GR_MEM_READ_MODE_PLANE 1 |
#define | VGA_GR_MEM_MODE_MASK 0xc |
#define | VGA_GR_MEM_MODE_SHIFT 2 |
#define | VGA_GR_MEM_A0000_AFFFF 0 |
#define | VGA_GR_MEM_A0000_BFFFF 1 |
#define | VGA_GR_MEM_B0000_B7FFF 2 |
#define | VGA_GR_MEM_B0000_BFFFF 3 |
#define | VGA_DACMASK 0x3c6 |
#define | VGA_DACRX 0x3c7 |
#define | VGA_DACWX 0x3c8 |
#define | VGA_DACDATA 0x3c9 |
#define | VGA_CR_INDEX_MDA 0x3b4 |
#define | VGA_CR_DATA_MDA 0x3b5 |
#define | VGA_CR_INDEX_CGA 0x3d4 |
#define | VGA_CR_DATA_CGA 0x3d5 |
#define | MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) |
#define | MI_NOOP MI_INSTR(0, 0) |
#define | MI_USER_INTERRUPT MI_INSTR(0x02, 0) |
#define | MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) |
#define | MI_WAIT_FOR_OVERLAY_FLIP (1<<16) |
#define | MI_WAIT_FOR_PLANE_B_FLIP (1<<6) |
#define | MI_WAIT_FOR_PLANE_A_FLIP (1<<2) |
#define | MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) |
#define | MI_FLUSH MI_INSTR(0x04, 0) |
#define | MI_READ_FLUSH (1 << 0) |
#define | MI_EXE_FLUSH (1 << 1) |
#define | MI_NO_WRITE_FLUSH (1 << 2) |
#define | MI_SCENE_COUNT (1 << 3) /* just increment scene count */ |
#define | MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ |
#define | MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ |
#define | MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) |
#define | MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) |
#define | MI_SUSPEND_FLUSH_EN (1<<0) |
#define | MI_REPORT_HEAD MI_INSTR(0x07, 0) |
#define | MI_OVERLAY_FLIP MI_INSTR(0x11, 0) |
#define | MI_OVERLAY_CONTINUE (0x0<<21) |
#define | MI_OVERLAY_ON (0x1<<21) |
#define | MI_OVERLAY_OFF (0x2<<21) |
#define | MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) |
#define | MI_DISPLAY_FLIP MI_INSTR(0x14, 2) |
#define | MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) |
#define | MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) |
#define | MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) |
#define | MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) |
#define | MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) |
#define | MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) |
#define | MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) |
#define | MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) |
#define | MI_ARB_ON_OFF MI_INSTR(0x08, 0) |
#define | MI_ARB_ENABLE (1<<0) |
#define | MI_ARB_DISABLE (0<<0) |
#define | MI_SET_CONTEXT MI_INSTR(0x18, 0) |
#define | MI_MM_SPACE_GTT (1<<8) |
#define | MI_MM_SPACE_PHYSICAL (0<<8) |
#define | MI_SAVE_EXT_STATE_EN (1<<3) |
#define | MI_RESTORE_EXT_STATE_EN (1<<2) |
#define | MI_FORCE_RESTORE (1<<1) |
#define | MI_RESTORE_INHIBIT (1<<0) |
#define | MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) |
#define | MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ |
#define | MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) |
#define | MI_STORE_DWORD_INDEX_SHIFT 2 |
#define | MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) |
#define | MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ |
#define | MI_FLUSH_DW_STORE_INDEX (1<<21) |
#define | MI_INVALIDATE_TLB (1<<18) |
#define | MI_FLUSH_DW_OP_STOREDW (1<<14) |
#define | MI_INVALIDATE_BSD (1<<7) |
#define | MI_FLUSH_DW_USE_GTT (1<<2) |
#define | MI_FLUSH_DW_USE_PPGTT (0<<2) |
#define | MI_BATCH_BUFFER MI_INSTR(0x30, 1) |
#define | MI_BATCH_NON_SECURE (1) |
#define | MI_BATCH_NON_SECURE_I965 (1<<8) |
#define | MI_BATCH_PPGTT_HSW (1<<8) |
#define | MI_BATCH_NON_SECURE_HSW (1<<13) |
#define | MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
#define | MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ |
#define | MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ |
#define | MI_SEMAPHORE_GLOBAL_GTT (1<<22) |
#define | MI_SEMAPHORE_UPDATE (1<<21) |
#define | MI_SEMAPHORE_COMPARE (1<<20) |
#define | MI_SEMAPHORE_REGISTER (1<<18) |
#define | MI_SEMAPHORE_SYNC_RV (2<<16) |
#define | MI_SEMAPHORE_SYNC_RB (0<<16) |
#define | MI_SEMAPHORE_SYNC_VR (0<<16) |
#define | MI_SEMAPHORE_SYNC_VB (2<<16) |
#define | MI_SEMAPHORE_SYNC_BR (2<<16) |
#define | MI_SEMAPHORE_SYNC_BV (0<<16) |
#define | MI_SEMAPHORE_SYNC_INVALID (1<<0) |
#define | GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) |
#define | GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) |
#define | GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
#define | SC_UPDATE_SCISSOR (0x1<<1) |
#define | SC_ENABLE_MASK (0x1<<0) |
#define | SC_ENABLE (0x1<<0) |
#define | GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) |
#define | GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) |
#define | SCI_YMIN_MASK (0xffff<<16) |
#define | SCI_XMIN_MASK (0xffff<<0) |
#define | SCI_YMAX_MASK (0xffff<<16) |
#define | SCI_XMAX_MASK (0xffff<<0) |
#define | GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
#define | GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) |
#define | GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) |
#define | GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) |
#define | GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) |
#define | GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) |
#define | GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) |
#define | GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) |
#define | GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) |
#define | SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) |
#define | XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) |
#define | XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) |
#define | XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) |
#define | XY_SRC_COPY_BLT_WRITE_RGB (1<<20) |
#define | BLT_DEPTH_8 (0<<24) |
#define | BLT_DEPTH_16_565 (1<<24) |
#define | BLT_DEPTH_16_1555 (2<<24) |
#define | BLT_DEPTH_32 (3<<24) |
#define | BLT_ROP_GXCOPY (0xcc<<16) |
#define | XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ |
#define | XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ |
#define | CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) |
#define | ASYNC_FLIP (1<<22) |
#define | DISPLAY_PLANE_A (0<<20) |
#define | DISPLAY_PLANE_B (1<<20) |
#define | GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) |
#define | PIPE_CONTROL_CS_STALL (1<<20) |
#define | PIPE_CONTROL_TLB_INVALIDATE (1<<18) |
#define | PIPE_CONTROL_QW_WRITE (1<<14) |
#define | PIPE_CONTROL_DEPTH_STALL (1<<13) |
#define | PIPE_CONTROL_WRITE_FLUSH (1<<12) |
#define | PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ |
#define | PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ |
#define | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ |
#define | PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) |
#define | PIPE_CONTROL_NOTIFY (1<<8) |
#define | PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) |
#define | PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) |
#define | PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) |
#define | PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) |
#define | PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) |
#define | PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ |
#define | DEBUG_RESET_I830 0x6070 |
#define | DEBUG_RESET_FULL (1<<7) |
#define | DEBUG_RESET_RENDER (1<<8) |
#define | DEBUG_RESET_DISPLAY (1<<9) |
#define | DPIO_PKT 0x2100 |
#define | DPIO_RID (0<<24) |
#define | DPIO_OP_WRITE (1<<16) |
#define | DPIO_OP_READ (0<<16) |
#define | DPIO_PORTID (0x12<<8) |
#define | DPIO_BYTE (0xf<<4) |
#define | DPIO_BUSY (1<<0) /* status only */ |
#define | DPIO_DATA 0x2104 |
#define | DPIO_REG 0x2108 |
#define | DPIO_CTL 0x2110 |
#define | DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ |
#define | DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ |
#define | DPIO_SFR_BYPASS (1<<1) |
#define | DPIO_RESET (1<<0) |
#define | _DPIO_DIV_A 0x800c |
#define | DPIO_POST_DIV_SHIFT (28) /* 3 bits */ |
#define | DPIO_K_SHIFT (24) /* 4 bits */ |
#define | DPIO_P1_SHIFT (21) /* 3 bits */ |
#define | DPIO_P2_SHIFT (16) /* 5 bits */ |
#define | DPIO_N_SHIFT (12) /* 4 bits */ |
#define | DPIO_ENABLE_CALIBRATION (1<<11) |
#define | DPIO_M1DIV_SHIFT (8) /* 3 bits */ |
#define | DPIO_M2DIV_MASK 0xff |
#define | _DPIO_DIV_B 0x802c |
#define | DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B) |
#define | _DPIO_REFSFR_A 0x8014 |
#define | DPIO_REFSEL_OVERRIDE 27 |
#define | DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ |
#define | DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ |
#define | DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ |
#define | DPIO_PLL_REFCLK_SEL_MASK 3 |
#define | DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ |
#define | DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ |
#define | _DPIO_REFSFR_B 0x8034 |
#define | DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B) |
#define | _DPIO_CORE_CLK_A 0x801c |
#define | _DPIO_CORE_CLK_B 0x803c |
#define | DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B) |
#define | _DPIO_LFP_COEFF_A 0x8048 |
#define | _DPIO_LFP_COEFF_B 0x8068 |
#define | DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B) |
#define | DPIO_FASTCLK_DISABLE 0x8100 |
#define | DPIO_DATA_CHANNEL1 0x8220 |
#define | DPIO_DATA_CHANNEL2 0x8420 |
#define | FENCE_REG_830_0 0x2000 |
#define | FENCE_REG_945_8 0x3000 |
#define | I830_FENCE_START_MASK 0x07f80000 |
#define | I830_FENCE_TILING_Y_SHIFT 12 |
#define | I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
#define | I830_FENCE_PITCH_SHIFT 4 |
#define | I830_FENCE_REG_VALID (1<<0) |
#define | I915_FENCE_MAX_PITCH_VAL 4 |
#define | I830_FENCE_MAX_PITCH_VAL 6 |
#define | I830_FENCE_MAX_SIZE_VAL (1<<8) |
#define | I915_FENCE_START_MASK 0x0ff00000 |
#define | I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) |
#define | FENCE_REG_965_0 0x03000 |
#define | I965_FENCE_PITCH_SHIFT 2 |
#define | I965_FENCE_TILING_Y_SHIFT 1 |
#define | I965_FENCE_REG_VALID (1<<0) |
#define | I965_FENCE_MAX_PITCH_VAL 0x0400 |
#define | FENCE_REG_SANDYBRIDGE_0 0x100000 |
#define | SANDYBRIDGE_FENCE_PITCH_SHIFT 32 |
#define | TILECTL 0x101000 |
#define | TILECTL_SWZCTL (1 << 0) |
#define | TILECTL_TLB_PREFETCH_DIS (1 << 2) |
#define | TILECTL_BACKSNOOP_DIS (1 << 3) |
#define | PGTBL_ER 0x02024 |
#define | RENDER_RING_BASE 0x02000 |
#define | BSD_RING_BASE 0x04000 |
#define | GEN6_BSD_RING_BASE 0x12000 |
#define | BLT_RING_BASE 0x22000 |
#define | RING_TAIL(base) ((base)+0x30) |
#define | RING_HEAD(base) ((base)+0x34) |
#define | RING_START(base) ((base)+0x38) |
#define | RING_CTL(base) ((base)+0x3c) |
#define | RING_SYNC_0(base) ((base)+0x40) |
#define | RING_SYNC_1(base) ((base)+0x44) |
#define | GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) |
#define | GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) |
#define | GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) |
#define | GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) |
#define | GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) |
#define | GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) |
#define | RING_MAX_IDLE(base) ((base)+0x54) |
#define | RING_HWS_PGA(base) ((base)+0x80) |
#define | RING_HWS_PGA_GEN6(base) ((base)+0x2080) |
#define | ARB_MODE 0x04030 |
#define | ARB_MODE_SWIZZLE_SNB (1<<4) |
#define | ARB_MODE_SWIZZLE_IVB (1<<5) |
#define | RENDER_HWS_PGA_GEN7 (0x04080) |
#define | RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) |
#define | DONE_REG 0x40b0 |
#define | BSD_HWS_PGA_GEN7 (0x04180) |
#define | BLT_HWS_PGA_GEN7 (0x04280) |
#define | RING_ACTHD(base) ((base)+0x74) |
#define | RING_NOPID(base) ((base)+0x94) |
#define | RING_IMR(base) ((base)+0xa8) |
#define | RING_TIMESTAMP(base) ((base)+0x358) |
#define | TAIL_ADDR 0x001FFFF8 |
#define | HEAD_WRAP_COUNT 0xFFE00000 |
#define | HEAD_WRAP_ONE 0x00200000 |
#define | HEAD_ADDR 0x001FFFFC |
#define | RING_NR_PAGES 0x001FF000 |
#define | RING_REPORT_MASK 0x00000006 |
#define | RING_REPORT_64K 0x00000002 |
#define | RING_REPORT_128K 0x00000004 |
#define | RING_NO_REPORT 0x00000000 |
#define | RING_VALID_MASK 0x00000001 |
#define | RING_VALID 0x00000001 |
#define | RING_INVALID 0x00000000 |
#define | RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ |
#define | RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ |
#define | RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ |
#define | IPEIR_I965 0x02064 |
#define | IPEHR_I965 0x02068 |
#define | INSTDONE_I965 0x0206c |
#define | GEN7_INSTDONE_1 0x0206c |
#define | GEN7_SC_INSTDONE 0x07100 |
#define | GEN7_SAMPLER_INSTDONE 0x0e160 |
#define | GEN7_ROW_INSTDONE 0x0e164 |
#define | I915_NUM_INSTDONE_REG 4 |
#define | RING_IPEIR(base) ((base)+0x64) |
#define | RING_IPEHR(base) ((base)+0x68) |
#define | RING_INSTDONE(base) ((base)+0x6c) |
#define | RING_INSTPS(base) ((base)+0x70) |
#define | RING_DMA_FADD(base) ((base)+0x78) |
#define | RING_INSTPM(base) ((base)+0xc0) |
#define | INSTPS 0x02070 /* 965+ only */ |
#define | INSTDONE1 0x0207c /* 965+ only */ |
#define | ACTHD_I965 0x02074 |
#define | HWS_PGA 0x02080 |
#define | HWS_ADDRESS_MASK 0xfffff000 |
#define | HWS_START_ADDRESS_SHIFT 4 |
#define | PWRCTXA 0x2088 /* 965GM+ only */ |
#define | PWRCTX_EN (1<<0) |
#define | IPEIR 0x02088 |
#define | IPEHR 0x0208c |
#define | INSTDONE 0x02090 |
#define | NOPID 0x02094 |
#define | HWSTAM 0x02098 |
#define | DMA_FADD_I8XX 0x020d0 |
#define | ERROR_GEN6 0x040a0 |
#define | GEN7_ERR_INT 0x44040 |
#define | ERR_INT_MMIO_UNCLAIMED (1<<13) |
#define | DERRMR 0x44050 |
#define | _3D_CHICKEN 0x02084 |
#define | _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) |
#define | _3D_CHICKEN2 0x0208c |
#define | _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) |
#define | _3D_CHICKEN3 0x02090 |
#define | _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) |
#define | _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) |
#define | MI_MODE 0x0209c |
#define | VS_TIMER_DISPATCH (1 << 6) |
#define | MI_FLUSH_ENABLE (1 << 12) |
#define | ASYNC_FLIP_PERF_DISABLE (1 << 14) |
#define | GEN6_GT_MODE 0x20d0 |
#define | GEN6_GT_MODE_HI (1 << 9) |
#define | GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) |
#define | GFX_MODE 0x02520 |
#define | GFX_MODE_GEN7 0x0229c |
#define | RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) |
#define | GFX_RUN_LIST_ENABLE (1<<15) |
#define | GFX_TLB_INVALIDATE_ALWAYS (1<<13) |
#define | GFX_SURFACE_FAULT_ENABLE (1<<12) |
#define | GFX_REPLAY_MODE (1<<11) |
#define | GFX_PSMI_GRANULARITY (1<<10) |
#define | GFX_PPGTT_ENABLE (1<<9) |
#define | VLV_DISPLAY_BASE 0x180000 |
#define | SCPD0 0x0209c /* 915+ only */ |
#define | IER 0x020a0 |
#define | IIR 0x020a4 |
#define | IMR 0x020a8 |
#define | ISR 0x020ac |
#define | VLV_GUNIT_CLOCK_GATE 0x182060 |
#define | GCFG_DIS (1<<8) |
#define | VLV_IIR_RW 0x182084 |
#define | VLV_IER 0x1820a0 |
#define | VLV_IIR 0x1820a4 |
#define | VLV_IMR 0x1820a8 |
#define | VLV_ISR 0x1820ac |
#define | I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
#define | I915_DISPLAY_PORT_INTERRUPT (1<<17) |
#define | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) |
#define | I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ |
#define | I915_HWB_OOM_INTERRUPT (1<<13) |
#define | I915_SYNC_STATUS_INTERRUPT (1<<12) |
#define | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) |
#define | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) |
#define | I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) |
#define | I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) |
#define | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) |
#define | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) |
#define | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) |
#define | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) |
#define | I915_DEBUG_INTERRUPT (1<<2) |
#define | I915_USER_INTERRUPT (1<<1) |
#define | I915_ASLE_INTERRUPT (1<<0) |
#define | I915_BSD_USER_INTERRUPT (1<<25) |
#define | EIR 0x020b0 |
#define | EMR 0x020b4 |
#define | GM45_ERROR_PAGE_TABLE (1<<5) |
#define | GM45_ERROR_MEM_PRIV (1<<4) |
#define | I915_ERROR_PAGE_TABLE (1<<4) |
#define | GM45_ERROR_CP_PRIV (1<<3) |
#define | I915_ERROR_MEMORY_REFRESH (1<<1) |
#define | I915_ERROR_INSTRUCTION (1<<0) |
#define | INSTPM 0x020c0 |
#define | INSTPM_SELF_EN (1<<12) /* 915GM only */ |
#define | INSTPM_AGPBUSY_DIS |
#define | INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ |
#define | ACTHD 0x020c8 |
#define | FW_BLC 0x020d8 |
#define | FW_BLC2 0x020dc |
#define | FW_BLC_SELF 0x020e0 /* 915+ only */ |
#define | FW_BLC_SELF_EN_MASK (1UL<<31) |
#define | FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ |
#define | FW_BLC_SELF_EN (1<<15) /* 945 only */ |
#define | MM_BURST_LENGTH 0x00700000 |
#define | MM_FIFO_WATERMARK 0x0001F000 |
#define | LM_BURST_LENGTH 0x00000700 |
#define | LM_FIFO_WATERMARK 0x0000001F |
#define | MI_ARB_STATE 0x020e4 /* 915+ only */ |
#define | MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) |
#define | MI_ARB_ISOCH_WAIT_GTT (1 << 14) |
#define | MI_ARB_BLOCK_GRANT_MASK (3 << 12) |
#define | MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ |
#define | MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ |
#define | MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ |
#define | MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ |
#define | MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) |
#define | MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) |
#define | MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) |
#define | MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) |
#define | MI_ARB_TIME_SLICE_MASK (7 << 5) |
#define | MI_ARB_TIME_SLICE_1 (0 << 5) |
#define | MI_ARB_TIME_SLICE_2 (1 << 5) |
#define | MI_ARB_TIME_SLICE_4 (2 << 5) |
#define | MI_ARB_TIME_SLICE_6 (3 << 5) |
#define | MI_ARB_TIME_SLICE_8 (4 << 5) |
#define | MI_ARB_TIME_SLICE_10 (5 << 5) |
#define | MI_ARB_TIME_SLICE_14 (6 << 5) |
#define | MI_ARB_TIME_SLICE_16 (7 << 5) |
#define | MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ |
#define | MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) |
#define | MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) |
#define | MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ |
#define | MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ |
#define | CACHE_MODE_0 0x02120 /* 915+ only */ |
#define | CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) |
#define | CM0_IZ_OPT_DISABLE (1<<6) |
#define | CM0_ZR_OPT_DISABLE (1<<5) |
#define | CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) |
#define | CM0_DEPTH_EVICT_DISABLE (1<<4) |
#define | CM0_COLOR_EVICT_DISABLE (1<<3) |
#define | CM0_DEPTH_WRITE_DISABLE (1<<1) |
#define | CM0_RC_OP_FLUSH_DISABLE (1<<0) |
#define | BB_ADDR 0x02140 /* 8 bytes */ |
#define | GFX_FLSH_CNTL 0x02170 /* 915+ only */ |
#define | GFX_FLSH_CNTL_GEN6 0x101008 |
#define | GFX_FLSH_CNTL_EN (1<<0) |
#define | ECOSKPD 0x021d0 |
#define | ECO_GATING_CX_ONLY (1<<3) |
#define | ECO_FLIP_DONE (1<<0) |
#define | CACHE_MODE_1 0x7004 /* IVB+ */ |
#define | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) |
#define | GEN6_RENDER_HWSTAM 0x2098 |
#define | GEN6_RENDER_IMR 0x20a8 |
#define | GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) |
#define | GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) |
#define | GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) |
#define | GEN6_RENDER_L3_PARITY_ERROR (1 << 5) |
#define | GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) |
#define | GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) |
#define | GEN6_RENDER_SYNC_STATUS (1 << 2) |
#define | GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) |
#define | GEN6_RENDER_USER_INTERRUPT (1 << 0) |
#define | GEN6_BLITTER_HWSTAM 0x22098 |
#define | GEN6_BLITTER_IMR 0x220a8 |
#define | GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) |
#define | GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) |
#define | GEN6_BLITTER_SYNC_STATUS (1 << 24) |
#define | GEN6_BLITTER_USER_INTERRUPT (1 << 22) |
#define | GEN6_BLITTER_ECOSKPD 0x221d0 |
#define | GEN6_BLITTER_LOCK_SHIFT 16 |
#define | GEN6_BLITTER_FBC_NOTIFY (1<<3) |
#define | GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 |
#define | GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) |
#define | GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) |
#define | GEN6_BSD_SLEEP_INDICATOR (1 << 3) |
#define | GEN6_BSD_GO_INDICATOR (1 << 4) |
#define | GEN6_BSD_HWSTAM 0x12098 |
#define | GEN6_BSD_IMR 0x120a8 |
#define | GEN6_BSD_USER_INTERRUPT (1 << 12) |
#define | GEN6_BSD_RNCID 0x12198 |
#define | GEN7_FF_THREAD_MODE 0x20a0 |
#define | GEN7_FF_SCHED_MASK 0x0077070 |
#define | GEN7_FF_TS_SCHED_HS1 (0x5<<16) |
#define | GEN7_FF_TS_SCHED_HS0 (0x3<<16) |
#define | GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) |
#define | GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ |
#define | GEN7_FF_VS_SCHED_HS1 (0x5<<12) |
#define | GEN7_FF_VS_SCHED_HS0 (0x3<<12) |
#define | GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ |
#define | GEN7_FF_VS_SCHED_HW (0x0<<12) |
#define | GEN7_FF_DS_SCHED_HS1 (0x5<<4) |
#define | GEN7_FF_DS_SCHED_HS0 (0x3<<4) |
#define | GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ |
#define | GEN7_FF_DS_SCHED_HW (0x0<<4) |
#define | FBC_CFB_BASE 0x03200 /* 4k page aligned */ |
#define | FBC_LL_BASE 0x03204 /* 4k page aligned */ |
#define | FBC_CONTROL 0x03208 |
#define | FBC_CTL_EN (1UL<<31) |
#define | FBC_CTL_PERIODIC (1<<30) |
#define | FBC_CTL_INTERVAL_SHIFT (16) |
#define | FBC_CTL_UNCOMPRESSIBLE (1<<14) |
#define | FBC_CTL_C3_IDLE (1<<13) |
#define | FBC_CTL_STRIDE_SHIFT (5) |
#define | FBC_CTL_FENCENO (1<<0) |
#define | FBC_COMMAND 0x0320c |
#define | FBC_CMD_COMPRESS (1<<0) |
#define | FBC_STATUS 0x03210 |
#define | FBC_STAT_COMPRESSING (1UL<<31) |
#define | FBC_STAT_COMPRESSED (1<<30) |
#define | FBC_STAT_MODIFIED (1<<29) |
#define | FBC_STAT_CURRENT_LINE (1<<0) |
#define | FBC_CONTROL2 0x03214 |
#define | FBC_CTL_FENCE_DBL (0<<4) |
#define | FBC_CTL_IDLE_IMM (0<<2) |
#define | FBC_CTL_IDLE_FULL (1<<2) |
#define | FBC_CTL_IDLE_LINE (2<<2) |
#define | FBC_CTL_IDLE_DEBUG (3<<2) |
#define | FBC_CTL_CPU_FENCE (1<<1) |
#define | FBC_CTL_PLANEA (0<<0) |
#define | FBC_CTL_PLANEB (1<<0) |
#define | FBC_FENCE_OFF 0x0321b |
#define | FBC_TAG 0x03300 |
#define | FBC_LL_SIZE (1536) |
#define | DPFC_CB_BASE 0x3200 |
#define | DPFC_CONTROL 0x3208 |
#define | DPFC_CTL_EN (1UL<<31) |
#define | DPFC_CTL_PLANEA (0<<30) |
#define | DPFC_CTL_PLANEB (1<<30) |
#define | DPFC_CTL_FENCE_EN (1<<29) |
#define | DPFC_CTL_PERSISTENT_MODE (1<<25) |
#define | DPFC_SR_EN (1<<10) |
#define | DPFC_CTL_LIMIT_1X (0<<6) |
#define | DPFC_CTL_LIMIT_2X (1<<6) |
#define | DPFC_CTL_LIMIT_4X (2<<6) |
#define | DPFC_RECOMP_CTL 0x320c |
#define | DPFC_RECOMP_STALL_EN (1<<27) |
#define | DPFC_RECOMP_STALL_WM_SHIFT (16) |
#define | DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) |
#define | DPFC_RECOMP_TIMER_COUNT_SHIFT (0) |
#define | DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) |
#define | DPFC_STATUS 0x3210 |
#define | DPFC_INVAL_SEG_SHIFT (16) |
#define | DPFC_INVAL_SEG_MASK (0x07ff0000) |
#define | DPFC_COMP_SEG_SHIFT (0) |
#define | DPFC_COMP_SEG_MASK (0x000003ff) |
#define | DPFC_STATUS2 0x3214 |
#define | DPFC_FENCE_YOFF 0x3218 |
#define | DPFC_CHICKEN 0x3224 |
#define | DPFC_HT_MODIFY (1UL<<31) |
#define | ILK_DPFC_CB_BASE 0x43200 |
#define | ILK_DPFC_CONTROL 0x43208 |
#define | DPFC_RESERVED (0x1FFFFF00) |
#define | ILK_DPFC_RECOMP_CTL 0x4320c |
#define | ILK_DPFC_STATUS 0x43210 |
#define | ILK_DPFC_FENCE_YOFF 0x43218 |
#define | ILK_DPFC_CHICKEN 0x43224 |
#define | ILK_FBC_RT_BASE 0x2128 |
#define | ILK_FBC_RT_VALID (1<<0) |
#define | ILK_DISPLAY_CHICKEN1 0x42000 |
#define | ILK_FBCQ_DIS (1<<22) |
#define | ILK_PABSTRETCH_DIS (1<<21) |
#define | SNB_DPFC_CTL_SA 0x100100 |
#define | SNB_CPU_FENCE_ENABLE (1<<29) |
#define | DPFC_CPU_FENCE_OFFSET 0x100104 |
#define | GPIOA 0x5010 |
#define | GPIOB 0x5014 |
#define | GPIOC 0x5018 |
#define | GPIOD 0x501c |
#define | GPIOE 0x5020 |
#define | GPIOF 0x5024 |
#define | GPIOG 0x5028 |
#define | GPIOH 0x502c |
#define | GPIO_CLOCK_DIR_MASK (1 << 0) |
#define | GPIO_CLOCK_DIR_IN (0 << 1) |
#define | GPIO_CLOCK_DIR_OUT (1 << 1) |
#define | GPIO_CLOCK_VAL_MASK (1 << 2) |
#define | GPIO_CLOCK_VAL_OUT (1 << 3) |
#define | GPIO_CLOCK_VAL_IN (1 << 4) |
#define | GPIO_CLOCK_PULLUP_DISABLE (1 << 5) |
#define | GPIO_DATA_DIR_MASK (1 << 8) |
#define | GPIO_DATA_DIR_IN (0 << 9) |
#define | GPIO_DATA_DIR_OUT (1 << 9) |
#define | GPIO_DATA_VAL_MASK (1 << 10) |
#define | GPIO_DATA_VAL_OUT (1 << 11) |
#define | GPIO_DATA_VAL_IN (1 << 12) |
#define | GPIO_DATA_PULLUP_DISABLE (1 << 13) |
#define | GMBUS0 0x5100 /* clock/port select */ |
#define | GMBUS_RATE_100KHZ (0<<8) |
#define | GMBUS_RATE_50KHZ (1<<8) |
#define | GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ |
#define | GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ |
#define | GMBUS_RATE_MASK (3<<8) |
#define | GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ |
#define | GMBUS_PORT_DISABLED 0 |
#define | GMBUS_PORT_SSC 1 |
#define | GMBUS_PORT_VGADDC 2 |
#define | GMBUS_PORT_PANEL 3 |
#define | GMBUS_PORT_DPC 4 /* HDMIC */ |
#define | GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ |
#define | GMBUS_PORT_DPD 6 /* HDMID */ |
#define | GMBUS_PORT_RESERVED 7 /* 7 reserved */ |
#define | GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) |
#define | GMBUS_PORT_MASK 7 |
#define | GMBUS1 0x5104 /* command/status */ |
#define | GMBUS_SW_CLR_INT (1UL<<31) |
#define | GMBUS_SW_RDY (1<<30) |
#define | GMBUS_ENT (1<<29) /* enable timeout */ |
#define | GMBUS_CYCLE_NONE (0<<25) |
#define | GMBUS_CYCLE_WAIT (1<<25) |
#define | GMBUS_CYCLE_INDEX (2<<25) |
#define | GMBUS_CYCLE_STOP (4<<25) |
#define | GMBUS_BYTE_COUNT_SHIFT 16 |
#define | GMBUS_SLAVE_INDEX_SHIFT 8 |
#define | GMBUS_SLAVE_ADDR_SHIFT 1 |
#define | GMBUS_SLAVE_READ (1<<0) |
#define | GMBUS_SLAVE_WRITE (0<<0) |
#define | GMBUS2 0x5108 /* status */ |
#define | GMBUS_INUSE (1<<15) |
#define | GMBUS_HW_WAIT_PHASE (1<<14) |
#define | GMBUS_STALL_TIMEOUT (1<<13) |
#define | GMBUS_INT (1<<12) |
#define | GMBUS_HW_RDY (1<<11) |
#define | GMBUS_SATOER (1<<10) |
#define | GMBUS_ACTIVE (1<<9) |
#define | GMBUS3 0x510c /* data buffer bytes 3-0 */ |
#define | GMBUS4 0x5110 /* interrupt mask (Pineview+) */ |
#define | GMBUS_SLAVE_TIMEOUT_EN (1<<4) |
#define | GMBUS_NAK_EN (1<<3) |
#define | GMBUS_IDLE_EN (1<<2) |
#define | GMBUS_HW_WAIT_EN (1<<1) |
#define | GMBUS_HW_RDY_EN (1<<0) |
#define | GMBUS5 0x5120 /* byte index */ |
#define | GMBUS_2BYTE_INDEX_EN (1UL<<31) |
#define | VGA0 0x6000 |
#define | VGA1 0x6004 |
#define | VGA_PD 0x6010 |
#define | VGA0_PD_P2_DIV_4 (1 << 7) |
#define | VGA0_PD_P1_DIV_2 (1 << 5) |
#define | VGA0_PD_P1_SHIFT 0 |
#define | VGA0_PD_P1_MASK (0x1f << 0) |
#define | VGA1_PD_P2_DIV_4 (1 << 15) |
#define | VGA1_PD_P1_DIV_2 (1 << 13) |
#define | VGA1_PD_P1_SHIFT 8 |
#define | VGA1_PD_P1_MASK (0x1f << 8) |
#define | _DPLL_A 0x06014 |
#define | _DPLL_B 0x06018 |
#define | DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) |
#define | DPLL_VCO_ENABLE (1UL << 31) |
#define | DPLL_DVO_HIGH_SPEED (1 << 30) |
#define | DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) |
#define | DPLL_SYNCLOCK_ENABLE (1 << 29) |
#define | DPLL_REFA_CLK_ENABLE_VLV (1 << 29) |
#define | DPLL_VGA_MODE_DIS (1 << 28) |
#define | DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ |
#define | DPLLB_MODE_LVDS (2 << 26) /* i915 */ |
#define | DPLL_MODE_MASK (3 << 26) |
#define | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ |
#define | DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ |
#define | DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ |
#define | DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ |
#define | DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ |
#define | DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
#define | DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
#define | DPLL_LOCK_VLV (1<<15) |
#define | DPLL_INTEGRATED_CLOCK_VLV (1<<13) |
#define | SRX_INDEX 0x3c4 |
#define | SRX_DATA 0x3c5 |
#define | SR01 1 |
#define | SR01_SCREEN_OFF (1<<5) |
#define | PPCR 0x61204 |
#define | PPCR_ON (1<<0) |
#define | DVOB 0x61140 |
#define | DVOB_ON (1UL<<31) |
#define | DVOC 0x61160 |
#define | DVOC_ON (1UL<<31) |
#define | LVDS 0x61180 |
#define | LVDS_ON (1UL<<31) |
#define | LVDS_CLOCK_A_POWERUP_ALL (3 << 8) |
#define | LVDS_CLOCK_B_POWERUP_ALL (3 << 4) |
#define | LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) |
#define | LVDS_BORDER_ENABLE (1 << 15) |
#define | LVDS_DETECTED (1 << 1) |
#define | DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 |
#define | DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 |
#define | DPLL_FPA01_P1_POST_DIV_SHIFT 16 |
#define | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 |
#define | PLL_P2_DIVIDE_BY_4 (1 << 23) |
#define | PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ |
#define | PLL_REF_INPUT_DREFCLK (0 << 13) |
#define | PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ |
#define | PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ |
#define | PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) |
#define | PLL_REF_INPUT_MASK (3 << 13) |
#define | PLL_LOAD_PULSE_PHASE_SHIFT 9 |
#define | PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 |
#define | PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) |
#define | PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) |
#define | DPLL_FPA1_P1_POST_DIV_SHIFT 0 |
#define | DPLL_FPA1_P1_POST_DIV_MASK 0xff |
#define | PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) |
#define | DISPLAY_RATE_SELECT_FPA1 (1 << 8) |
#define | SDVO_MULTIPLIER_MASK 0x000000ff |
#define | SDVO_MULTIPLIER_SHIFT_HIRES 4 |
#define | SDVO_MULTIPLIER_SHIFT_VGA 0 |
#define | _DPLL_A_MD 0x0601c /* 965+ only */ |
#define | DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 |
#define | DPLL_MD_UDI_DIVIDER_SHIFT 24 |
#define | DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 |
#define | DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 |
#define | DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 |
#define | DPLL_MD_UDI_MULTIPLIER_SHIFT 8 |
#define | DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f |
#define | DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 |
#define | _DPLL_B_MD 0x06020 /* 965+ only */ |
#define | DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) |
#define | _FPA0 0x06040 |
#define | _FPA1 0x06044 |
#define | _FPB0 0x06048 |
#define | _FPB1 0x0604c |
#define | FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) |
#define | FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) |
#define | FP_N_DIV_MASK 0x003f0000 |
#define | FP_N_PINEVIEW_DIV_MASK 0x00ff0000 |
#define | FP_N_DIV_SHIFT 16 |
#define | FP_M1_DIV_MASK 0x00003f00 |
#define | FP_M1_DIV_SHIFT 8 |
#define | FP_M2_DIV_MASK 0x0000003f |
#define | FP_M2_PINEVIEW_DIV_MASK 0x000000ff |
#define | FP_M2_DIV_SHIFT 0 |
#define | DPLL_TEST 0x606c |
#define | DPLLB_TEST_SDVO_DIV_1 (0 << 22) |
#define | DPLLB_TEST_SDVO_DIV_2 (1 << 22) |
#define | DPLLB_TEST_SDVO_DIV_4 (2 << 22) |
#define | DPLLB_TEST_SDVO_DIV_MASK (3 << 22) |
#define | DPLLB_TEST_N_BYPASS (1 << 19) |
#define | DPLLB_TEST_M_BYPASS (1 << 18) |
#define | DPLLB_INPUT_BUFFER_ENABLE (1 << 16) |
#define | DPLLA_TEST_N_BYPASS (1 << 3) |
#define | DPLLA_TEST_M_BYPASS (1 << 2) |
#define | DPLLA_INPUT_BUFFER_ENABLE (1 << 0) |
#define | D_STATE 0x6104 |
#define | DSTATE_GFX_RESET_I830 (1<<6) |
#define | DSTATE_PLL_D3_OFF (1<<3) |
#define | DSTATE_GFX_CLOCK_GATING (1<<1) |
#define | DSTATE_DOT_CLOCK_GATING (1<<0) |
#define | DSPCLK_GATE_D 0x6200 |
#define | DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ |
#define | VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ |
#define | VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ |
#define | VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ |
#define | AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ |
#define | DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ |
#define | DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ |
#define | TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ |
#define | TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ |
#define | TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ |
#define | TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ |
#define | DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ |
#define | DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ |
#define | DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ |
#define | DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ |
#define | DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ |
#define | DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ |
#define | DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ |
#define | DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ |
#define | DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) |
#define | DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) |
#define | DCUNIT_CLOCK_GATE_DISABLE (1 << 9) |
#define | DPUNIT_CLOCK_GATE_DISABLE (1 << 8) |
#define | VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ |
#define | OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ |
#define | DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ |
#define | OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) |
#define | OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) |
#define | OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) |
This bit must be set on the 830 to prevent hangs when turning off the overlay scaler. More... | |
#define | OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) |
#define | OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) |
#define | ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ |
#define | OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ |
#define | RENCLK_GATE_D1 0x6204 |
#define | BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ |
#define | MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ |
#define | PC_FE_CLOCK_GATE_DISABLE (1 << 11) |
#define | PC_BE_CLOCK_GATE_DISABLE (1 << 10) |
#define | WINDOWER_CLOCK_GATE_DISABLE (1 << 9) |
#define | INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) |
#define | COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) |
#define | MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) |
#define | MAG_CLOCK_GATE_DISABLE (1 << 5) |
#define | MECI_CLOCK_GATE_DISABLE (1 << 4) |
This bit must be unset on 855,865. More... | |
#define | DCMP_CLOCK_GATE_DISABLE (1 << 3) |
#define | MEC_CLOCK_GATE_DISABLE (1 << 2) |
#define | MECO_CLOCK_GATE_DISABLE (1 << 1) |
#define | SV_CLOCK_GATE_DISABLE (1 << 0) |
This bit must be set on 855,865. More... | |
#define | I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) |
#define | I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) |
#define | I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) |
#define | I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) |
#define | I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) |
#define | I915_WM_CLOCK_GATE_DISABLE (1 << 11) |
#define | I915_IZ_CLOCK_GATE_DISABLE (1 << 10) |
#define | I915_PI_CLOCK_GATE_DISABLE (1 << 9) |
#define | I915_DI_CLOCK_GATE_DISABLE (1 << 8) |
#define | I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) |
#define | I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) |
#define | I915_SC_CLOCK_GATE_DISABLE (1 << 5) |
#define | I915_FL_CLOCK_GATE_DISABLE (1 << 4) |
#define | I915_DM_CLOCK_GATE_DISABLE (1 << 3) |
#define | I915_PS_CLOCK_GATE_DISABLE (1 << 2) |
#define | I915_CC_CLOCK_GATE_DISABLE (1 << 1) |
#define | I915_BY_CLOCK_GATE_DISABLE (1 << 0) |
#define | I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) |
#define | I965_RCC_CLOCK_GATE_DISABLE (1 << 29) |
This bit must always be set on 965G/965GM. More... | |
#define | I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) |
#define | I965_DAP_CLOCK_GATE_DISABLE (1 << 27) |
#define | I965_ROC_CLOCK_GATE_DISABLE (1 << 26) |
#define | I965_GW_CLOCK_GATE_DISABLE (1 << 25) |
#define | I965_TD_CLOCK_GATE_DISABLE (1 << 24) |
#define | I965_ISC_CLOCK_GATE_DISABLE (1 << 23) |
This bit must always be set on 965G. More... | |
#define | I965_IC_CLOCK_GATE_DISABLE (1 << 22) |
#define | I965_EU_CLOCK_GATE_DISABLE (1 << 21) |
#define | I965_IF_CLOCK_GATE_DISABLE (1 << 20) |
#define | I965_TC_CLOCK_GATE_DISABLE (1 << 19) |
#define | I965_SO_CLOCK_GATE_DISABLE (1 << 17) |
#define | I965_FBC_CLOCK_GATE_DISABLE (1 << 16) |
#define | I965_MARI_CLOCK_GATE_DISABLE (1 << 15) |
#define | I965_MASF_CLOCK_GATE_DISABLE (1 << 14) |
#define | I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) |
#define | I965_EM_CLOCK_GATE_DISABLE (1 << 12) |
#define | I965_UC_CLOCK_GATE_DISABLE (1 << 11) |
#define | I965_SI_CLOCK_GATE_DISABLE (1 << 6) |
#define | I965_MT_CLOCK_GATE_DISABLE (1 << 5) |
#define | I965_PL_CLOCK_GATE_DISABLE (1 << 4) |
#define | I965_DG_CLOCK_GATE_DISABLE (1 << 3) |
#define | I965_QC_CLOCK_GATE_DISABLE (1 << 2) |
#define | I965_FT_CLOCK_GATE_DISABLE (1 << 1) |
#define | I965_DM_CLOCK_GATE_DISABLE (1 << 0) |
#define | RENCLK_GATE_D2 0x6208 |
#define | VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) |
#define | GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) |
#define | CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) |
#define | RAMCLK_GATE_D 0x6210 /* CRL only */ |
#define | DEUC 0x6214 /* CRL only */ |
#define | FW_BLC_SELF_VLV 0x6500 |
#define | FW_CSPWRDWNEN (1<<15) |
#define | _PALETTE_A 0x0a000 |
#define | _PALETTE_B 0x0a800 |
#define | PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B) |
#define | MCHBAR_MIRROR_BASE 0x10000 |
#define | CCID 0x2180 |
#define | CCID_EN (1<<0) |
#define | CXT_SIZE 0x21a0 |
#define | GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) |
#define | GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) |
#define | GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) |
#define | GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) |
#define | GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) |
#define | GEN6_CXT_TOTAL_SIZE(cxt_reg) |
#define | GEN7_CXT_SIZE 0x21a8 |
#define | GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f) |
#define | GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7) |
#define | GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f) |
#define | GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) |
#define | GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) |
#define | GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) |
#define | GEN7_CXT_TOTAL_SIZE(ctx_reg) |
#define | HSW_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 26) & 0x3f) |
#define | HSW_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 23) & 0x7) |
#define | HSW_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 15) & 0xff) |
#define | HSW_CXT_TOTAL_SIZE(ctx_reg) |
#define | OVADD 0x30000 |
#define | DOVSTA 0x30008 |
#define | OC_BUF (0x3<<20) |
#define | OGAMC5 0x30010 |
#define | OGAMC4 0x30014 |
#define | OGAMC3 0x30018 |
#define | OGAMC2 0x3001c |
#define | OGAMC1 0x30020 |
#define | OGAMC0 0x30024 |
#define | _HTOTAL_A 0x60000 |
#define | _HBLANK_A 0x60004 |
#define | _HSYNC_A 0x60008 |
#define | _VTOTAL_A 0x6000c |
#define | _VBLANK_A 0x60010 |
#define | _VSYNC_A 0x60014 |
#define | _PIPEASRC 0x6001c |
#define | _BCLRPAT_A 0x60020 |
#define | _VSYNCSHIFT_A 0x60028 |
#define | _HTOTAL_B 0x61000 |
#define | _HBLANK_B 0x61004 |
#define | _HSYNC_B 0x61008 |
#define | _VTOTAL_B 0x6100c |
#define | _VBLANK_B 0x61010 |
#define | _VSYNC_B 0x61014 |
#define | _PIPEBSRC 0x6101c |
#define | _BCLRPAT_B 0x61020 |
#define | _VSYNCSHIFT_B 0x61028 |
#define | HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B) |
#define | HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B) |
#define | HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) |
#define | VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B) |
#define | VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B) |
#define | VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B) |
#define | BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) |
#define | VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) |
#define | ADPA 0x61100 |
#define | PCH_ADPA 0xe1100 |
#define | VLV_ADPA (VLV_DISPLAY_BASE + ADPA) |
#define | ADPA_DAC_ENABLE (1UL<<31) |
#define | ADPA_DAC_DISABLE 0 |
#define | ADPA_PIPE_SELECT_MASK (1<<30) |
#define | ADPA_PIPE_A_SELECT 0 |
#define | ADPA_PIPE_B_SELECT (1<<30) |
#define | ADPA_PIPE_SELECT(pipe) ((pipe) << 30) |
#define | ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ |
#define | ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) |
#define | ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) |
#define | ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) |
#define | ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) |
#define | ADPA_CRT_HOTPLUG_ENABLE (1<<23) |
#define | ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) |
#define | ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) |
#define | ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) |
#define | ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) |
#define | ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) |
#define | ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) |
#define | ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) |
#define | ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) |
#define | ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) |
#define | ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) |
#define | ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) |
#define | ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) |
#define | ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) |
#define | ADPA_USE_VGA_HVPOLARITY (1<<15) |
#define | ADPA_SETS_HVPOLARITY 0 |
#define | ADPA_VSYNC_CNTL_DISABLE (1<<11) |
#define | ADPA_VSYNC_CNTL_ENABLE 0 |
#define | ADPA_HSYNC_CNTL_DISABLE (1<<10) |
#define | ADPA_HSYNC_CNTL_ENABLE 0 |
#define | ADPA_VSYNC_ACTIVE_HIGH (1<<4) |
#define | ADPA_VSYNC_ACTIVE_LOW 0 |
#define | ADPA_HSYNC_ACTIVE_HIGH (1<<3) |
#define | ADPA_HSYNC_ACTIVE_LOW 0 |
#define | ADPA_DPMS_MASK (~(3<<10)) |
#define | ADPA_DPMS_ON (0<<10) |
#define | ADPA_DPMS_SUSPEND (1<<10) |
#define | ADPA_DPMS_STANDBY (2<<10) |
#define | ADPA_DPMS_OFF (3<<10) |
#define | PORT_HOTPLUG_EN 0x61110 |
#define | HDMIB_HOTPLUG_INT_EN (1 << 29) |
#define | DPB_HOTPLUG_INT_EN (1 << 29) |
#define | HDMIC_HOTPLUG_INT_EN (1 << 28) |
#define | DPC_HOTPLUG_INT_EN (1 << 28) |
#define | HDMID_HOTPLUG_INT_EN (1 << 27) |
#define | DPD_HOTPLUG_INT_EN (1 << 27) |
#define | SDVOB_HOTPLUG_INT_EN (1 << 26) |
#define | SDVOC_HOTPLUG_INT_EN (1 << 25) |
#define | TV_HOTPLUG_INT_EN (1 << 18) |
#define | CRT_HOTPLUG_INT_EN (1 << 9) |
#define | CRT_HOTPLUG_FORCE_DETECT (1 << 3) |
#define | CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) |
#define | CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) |
#define | CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) |
#define | CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) |
#define | CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) |
#define | CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) |
#define | CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) |
#define | CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) |
#define | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) |
#define | CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) |
#define | CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) |
#define | CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) |
#define | CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) |
#define | PORT_HOTPLUG_STAT 0x61114 |
#define | DPB_HOTPLUG_LIVE_STATUS (1 << 29) |
#define | DPC_HOTPLUG_LIVE_STATUS (1 << 28) |
#define | DPD_HOTPLUG_LIVE_STATUS (1 << 27) |
#define | DPD_HOTPLUG_INT_STATUS (3 << 21) |
#define | DPC_HOTPLUG_INT_STATUS (3 << 19) |
#define | DPB_HOTPLUG_INT_STATUS (3 << 17) |
#define | HDMIB_HOTPLUG_LIVE_STATUS (1 << 29) |
#define | HDMIC_HOTPLUG_LIVE_STATUS (1 << 28) |
#define | HDMID_HOTPLUG_LIVE_STATUS (1 << 27) |
#define | HDMID_HOTPLUG_INT_STATUS (3 << 21) |
#define | HDMIC_HOTPLUG_INT_STATUS (3 << 19) |
#define | HDMIB_HOTPLUG_INT_STATUS (3 << 17) |
#define | CRT_HOTPLUG_INT_STATUS (1 << 11) |
#define | TV_HOTPLUG_INT_STATUS (1 << 10) |
#define | CRT_HOTPLUG_MONITOR_MASK (3 << 8) |
#define | CRT_HOTPLUG_MONITOR_COLOR (3 << 8) |
#define | CRT_HOTPLUG_MONITOR_MONO (2 << 8) |
#define | CRT_HOTPLUG_MONITOR_NONE (0 << 8) |
#define | SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) |
#define | SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) |
#define | SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) |
#define | SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) |
#define | SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) |
#define | SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) |
#define | SDVOB 0x61140 |
#define | SDVOC 0x61160 |
#define | SDVO_ENABLE (1UL << 31) |
#define | SDVO_PIPE_B_SELECT (1 << 30) |
#define | SDVO_STALL_SELECT (1 << 29) |
#define | SDVO_INTERRUPT_ENABLE (1 << 26) |
#define | SDVO_PORT_MULTIPLY_MASK (7 << 23) |
915G/GM SDVO pixel multiplier. More... | |
#define | SDVO_PORT_MULTIPLY_SHIFT 23 |
#define | SDVO_PHASE_SELECT_MASK (15 << 19) |
#define | SDVO_PHASE_SELECT_DEFAULT (6 << 19) |
#define | SDVO_CLOCK_OUTPUT_INVERT (1 << 18) |
#define | SDVOC_GANG_MODE (1 << 16) |
#define | SDVO_ENCODING_SDVO (0x0 << 10) |
#define | SDVO_ENCODING_HDMI (0x2 << 10) |
#define | SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) |
Requird for HDMI operation. More... | |
#define | SDVO_COLOR_RANGE_16_235 (1 << 8) |
#define | SDVO_BORDER_ENABLE (1 << 7) |
#define | SDVO_AUDIO_ENABLE (1 << 6) |
#define | SDVO_VSYNC_ACTIVE_HIGH (1 << 4) |
New with 965, default is to be set. More... | |
#define | SDVO_HSYNC_ACTIVE_HIGH (1 << 3) |
New with 965, default is to be set. More... | |
#define | SDVOB_PCIE_CONCURRENCY (1 << 3) |
#define | SDVO_DETECTED (1 << 2) |
#define | SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) |
#define | SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) |
#define | DVOA 0x61120 |
#define | DVOB 0x61140 |
#define | DVOC 0x61160 |
#define | DVO_ENABLE (1UL << 31) |
#define | DVO_PIPE_B_SELECT (1 << 30) |
#define | DVO_PIPE_STALL_UNUSED (0 << 28) |
#define | DVO_PIPE_STALL (1 << 28) |
#define | DVO_PIPE_STALL_TV (2 << 28) |
#define | DVO_PIPE_STALL_MASK (3 << 28) |
#define | DVO_USE_VGA_SYNC (1 << 15) |
#define | DVO_DATA_ORDER_I740 (0 << 14) |
#define | DVO_DATA_ORDER_FP (1 << 14) |
#define | DVO_VSYNC_DISABLE (1 << 11) |
#define | DVO_HSYNC_DISABLE (1 << 10) |
#define | DVO_VSYNC_TRISTATE (1 << 9) |
#define | DVO_HSYNC_TRISTATE (1 << 8) |
#define | DVO_BORDER_ENABLE (1 << 7) |
#define | DVO_DATA_ORDER_GBRG (1 << 6) |
#define | DVO_DATA_ORDER_RGGB (0 << 6) |
#define | DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) |
#define | DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) |
#define | DVO_VSYNC_ACTIVE_HIGH (1 << 4) |
#define | DVO_HSYNC_ACTIVE_HIGH (1 << 3) |
#define | DVO_BLANK_ACTIVE_HIGH (1 << 2) |
#define | DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ |
#define | DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ |
#define | DVO_PRESERVE_MASK (0x7<<24) |
#define | DVOA_SRCDIM 0x61124 |
#define | DVOB_SRCDIM 0x61144 |
#define | DVOC_SRCDIM 0x61164 |
#define | DVO_SRCDIM_HORIZONTAL_SHIFT 12 |
#define | DVO_SRCDIM_VERTICAL_SHIFT 0 |
#define | LVDS 0x61180 |
#define | LVDS_PORT_EN (1UL << 31) |
#define | LVDS_PIPEB_SELECT (1 << 30) |
#define | LVDS_PIPE_MASK (1 << 30) |
#define | LVDS_PIPE(pipe) ((pipe) << 30) |
#define | LVDS_ENABLE_DITHER (1 << 25) |
#define | LVDS_VSYNC_POLARITY (1 << 21) |
#define | LVDS_HSYNC_POLARITY (1 << 20) |
#define | LVDS_BORDER_ENABLE (1 << 15) |
#define | LVDS_A0A2_CLKA_POWER_MASK (3 << 8) |
#define | LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) |
#define | LVDS_A0A2_CLKA_POWER_UP (3 << 8) |
#define | LVDS_A3_POWER_MASK (3 << 6) |
#define | LVDS_A3_POWER_DOWN (0 << 6) |
#define | LVDS_A3_POWER_UP (3 << 6) |
#define | LVDS_CLKB_POWER_MASK (3 << 4) |
#define | LVDS_CLKB_POWER_DOWN (0 << 4) |
#define | LVDS_CLKB_POWER_UP (3 << 4) |
#define | LVDS_B0B3_POWER_MASK (3 << 2) |
#define | LVDS_B0B3_POWER_DOWN (0 << 2) |
#define | LVDS_B0B3_POWER_UP (3 << 2) |
#define | VIDEO_DIP_DATA 0x61178 |
#define | VIDEO_DIP_DATA_SIZE 32 |
#define | VIDEO_DIP_CTL 0x61170 |
#define | VIDEO_DIP_ENABLE (1UL << 31) |
#define | VIDEO_DIP_PORT_B (1 << 29) |
#define | VIDEO_DIP_PORT_C (2 << 29) |
#define | VIDEO_DIP_PORT_D (3 << 29) |
#define | VIDEO_DIP_PORT_MASK (3 << 29) |
#define | VIDEO_DIP_ENABLE_GCP (1 << 25) |
#define | VIDEO_DIP_ENABLE_AVI (1 << 21) |
#define | VIDEO_DIP_ENABLE_VENDOR (2 << 21) |
#define | VIDEO_DIP_ENABLE_GAMUT (4 << 21) |
#define | VIDEO_DIP_ENABLE_SPD (8 << 21) |
#define | VIDEO_DIP_SELECT_AVI (0 << 19) |
#define | VIDEO_DIP_SELECT_VENDOR (1 << 19) |
#define | VIDEO_DIP_SELECT_SPD (3 << 19) |
#define | VIDEO_DIP_SELECT_MASK (3 << 19) |
#define | VIDEO_DIP_FREQ_ONCE (0 << 16) |
#define | VIDEO_DIP_FREQ_VSYNC (1 << 16) |
#define | VIDEO_DIP_FREQ_2VSYNC (2 << 16) |
#define | VIDEO_DIP_FREQ_MASK (3 << 16) |
#define | VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) |
#define | VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) |
#define | VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) |
#define | VIDEO_DIP_ENABLE_VS_HSW (1 << 8) |
#define | VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) |
#define | VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) |
#define | PP_STATUS 0x61200 |
#define | PP_ON (1UL << 31) |
#define | PP_READY (1 << 30) |
#define | PP_SEQUENCE_NONE (0 << 28) |
#define | PP_SEQUENCE_POWER_UP (1 << 28) |
#define | PP_SEQUENCE_POWER_DOWN (2 << 28) |
#define | PP_SEQUENCE_MASK (3 << 28) |
#define | PP_SEQUENCE_SHIFT 28 |
#define | PP_CYCLE_DELAY_ACTIVE (1 << 27) |
#define | PP_SEQUENCE_STATE_MASK 0x0000000f |
#define | PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) |
#define | PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) |
#define | PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) |
#define | PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) |
#define | PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) |
#define | PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) |
#define | PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) |
#define | PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) |
#define | PP_SEQUENCE_STATE_RESET (0xf << 0) |
#define | PP_CONTROL 0x61204 |
#define | POWER_TARGET_ON (1 << 0) |
#define | PP_ON_DELAYS 0x61208 |
#define | PP_OFF_DELAYS 0x6120c |
#define | PP_DIVISOR 0x61210 |
#define | PFIT_CONTROL 0x61230 |
#define | PFIT_ENABLE (1UL << 31) |
#define | PFIT_PIPE_MASK (3 << 29) |
#define | PFIT_PIPE_SHIFT 29 |
#define | VERT_INTERP_DISABLE (0 << 10) |
#define | VERT_INTERP_BILINEAR (1 << 10) |
#define | VERT_INTERP_MASK (3 << 10) |
#define | VERT_AUTO_SCALE (1 << 9) |
#define | HORIZ_INTERP_DISABLE (0 << 6) |
#define | HORIZ_INTERP_BILINEAR (1 << 6) |
#define | HORIZ_INTERP_MASK (3 << 6) |
#define | HORIZ_AUTO_SCALE (1 << 5) |
#define | PANEL_8TO6_DITHER_ENABLE (1 << 3) |
#define | PFIT_FILTER_FUZZY (0 << 24) |
#define | PFIT_SCALING_AUTO (0 << 26) |
#define | PFIT_SCALING_PROGRAMMED (1 << 26) |
#define | PFIT_SCALING_PILLAR (2 << 26) |
#define | PFIT_SCALING_LETTER (3 << 26) |
#define | PFIT_PGM_RATIOS 0x61234 |
#define | PFIT_VERT_SCALE_MASK 0xfff00000 |
#define | PFIT_HORIZ_SCALE_MASK 0x0000fff0 |
#define | PFIT_VERT_SCALE_SHIFT 20 |
#define | PFIT_VERT_SCALE_MASK 0xfff00000 |
#define | PFIT_HORIZ_SCALE_SHIFT 4 |
#define | PFIT_HORIZ_SCALE_MASK 0x0000fff0 |
#define | PFIT_VERT_SCALE_SHIFT_965 16 |
#define | PFIT_VERT_SCALE_MASK_965 0x1fff0000 |
#define | PFIT_HORIZ_SCALE_SHIFT_965 0 |
#define | PFIT_HORIZ_SCALE_MASK_965 0x00001fff |
#define | PFIT_AUTO_RATIOS 0x61238 |
#define | BLC_PWM_CTL2 0x61250 /* 965+ only */ |
#define | BLM_PWM_ENABLE (1UL << 31) |
#define | BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ |
#define | BLM_PIPE_SELECT (1 << 29) |
#define | BLM_PIPE_SELECT_IVB (3 << 29) |
#define | BLM_PIPE_A (0 << 29) |
#define | BLM_PIPE_B (1 << 29) |
#define | BLM_PIPE_C (2 << 29) /* ivb + */ |
#define | BLM_PIPE(pipe) ((pipe) << 29) |
#define | BLM_POLARITY_I965 (1 << 28) /* gen4 only */ |
#define | BLM_PHASE_IN_INTERRUPT_STATUS (1 << 26) |
#define | BLM_PHASE_IN_ENABLE (1 << 25) |
#define | BLM_PHASE_IN_INTERRUPT_ENABL (1 << 24) |
#define | BLM_PHASE_IN_TIME_BASE_SHIFT (16) |
#define | BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) |
#define | BLM_PHASE_IN_COUNT_SHIFT (8) |
#define | BLM_PHASE_IN_COUNT_MASK (0xff << 8) |
#define | BLM_PHASE_IN_INCR_SHIFT (0) |
#define | BLM_PHASE_IN_INCR_MASK (0xff << 0) |
#define | BLC_PWM_CTL 0x61254 |
#define | BACKLIGHT_MODULATION_FREQ_SHIFT (17) |
#define | BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) |
#define | BLM_LEGACY_MODE (1 << 16) /* gen2 only */ |
#define | BACKLIGHT_DUTY_CYCLE_SHIFT (0) |
#define | BACKLIGHT_DUTY_CYCLE_MASK (0xffff) |
#define | BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) |
#define | BLM_POLARITY_PNV (1 << 0) /* pnv only */ |
#define | BLC_HIST_CTL 0x61260 |
#define | BLC_PWM_CPU_CTL2 0x48250 |
#define | BLC_PWM2_ENABLE (1UL<<31) |
#define | BLC_PWM_CPU_CTL 0x48254 |
#define | BLM_HIST_CTL 0x48260 |
#define | ENH_HIST_ENABLE (1UL<<31) |
#define | ENH_MODIF_TBL_ENABLE (1<<30) |
#define | ENH_PIPE_A_SELECT (0<<29) |
#define | ENH_PIPE_B_SELECT (1<<29) |
#define | ENH_PIPE(pipe) _PIPE(pipe, ENH_PIPE_A_SELECT, ENH_PIPE_B_SELECT) |
#define | HIST_MODE_YUV (0<<24) |
#define | HIST_MODE_HSV (1<<24) |
#define | ENH_MODE_DIRECT (0<<13) |
#define | ENH_MODE_ADDITIVE (1<<13) |
#define | ENH_MODE_MULTIPLICATIVE (2<<13) |
#define | BIN_REGISTER_SET (1<<11) |
#define | ENH_NUM_BINS 32 |
#define | BLM_HIST_ENH 0x48264 |
#define | BLM_HIST_GUARD_BAND 0x48268 |
#define | BLM_HIST_INTR_ENABLE (1UL<<31) |
#define | BLM_HIST_EVENT_STATUS (1<<30) |
#define | BLM_HIST_INTR_DELAY_MASK (0xFF<<22) |
#define | BLM_HIST_INTR_DELAY_SHIFT 22 |
#define | BLC_PWM_PCH_CTL1 0xc8250 |
#define | BLM_PCH_PWM_ENABLE (1UL << 31) |
#define | BLM_PCH_OVERRIDE_ENABLE (1 << 30) |
#define | BLM_PCH_POLARITY (1 << 29) |
#define | BLC_PWM_PCH_CTL2 0xc8254 |
#define | UTIL_PIN_CTL 0x48400 |
#define | UTIL_PIN_ENABLE (1 << 31) |
#define | UTIL_PIN_PIPE(x) ((x) << 29) |
#define | UTIL_PIN_PIPE_MASK (3 << 29) |
#define | UTIL_PIN_MODE_PWM (1 << 24) |
#define | UTIL_PIN_MODE_MASK (0xf << 24) |
#define | UTIL_PIN_POLARITY (1 << 22) |
#define | _BXT_BLC_PWM_CTL1 0xC8250 |
#define | BXT_BLC_PWM_ENABLE (1 << 31) |
#define | BXT_BLC_PWM_POLARITY (1 << 29) |
#define | _BXT_BLC_PWM_FREQ1 0xC8254 |
#define | _BXT_BLC_PWM_DUTY1 0xC8258 |
#define | _BXT_BLC_PWM_CTL2 0xC8350 |
#define | _BXT_BLC_PWM_FREQ2 0xC8354 |
#define | _BXT_BLC_PWM_DUTY2 0xC8358 |
#define | BXT_BLC_PWM_CTL(controller) |
#define | BXT_BLC_PWM_FREQ(controller) |
#define | BXT_BLC_PWM_DUTY(controller) |
#define | TV_CTL 0x68000 |
#define | TV_ENC_ENABLE (1UL << 31) |
Enables the TV encoder. More... | |
#define | TV_ENC_PIPEB_SELECT (1 << 30) |
Sources the TV encoder input from pipe B instead of A. More... | |
#define | TV_ENC_OUTPUT_COMPOSITE (0 << 28) |
Outputs composite video (DAC A only) More... | |
#define | TV_ENC_OUTPUT_SVIDEO (1 << 28) |
Outputs SVideo video (DAC B/C) More... | |
#define | TV_ENC_OUTPUT_COMPONENT (2 << 28) |
Outputs Component video (DAC A/B/C) More... | |
#define | TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) |
Outputs Composite and SVideo (DAC A/B/C) More... | |
#define | TV_TRILEVEL_SYNC (1 << 21) |
#define | TV_SLOW_SYNC (1 << 20) |
Enables slow sync generation (945GM only) More... | |
#define | TV_OVERSAMPLE_4X (0 << 18) |
Selects 4x oversampling for 480i and 576p. More... | |
#define | TV_OVERSAMPLE_2X (1 << 18) |
Selects 2x oversampling for 720p and 1080i. More... | |
#define | TV_OVERSAMPLE_NONE (2 << 18) |
Selects no oversampling for 1080p. More... | |
#define | TV_OVERSAMPLE_8X (3 << 18) |
Selects 8x oversampling. More... | |
#define | TV_PROGRESSIVE (1 << 17) |
Selects progressive mode rather than interlaced. More... | |
#define | TV_PAL_BURST (1 << 16) |
Sets the colorburst to PAL mode. More... | |
#define | TV_YC_SKEW_MASK (7 << 12) |
Field for setting delay of Y compared to C. More... | |
#define | TV_ENC_SDP_FIX (1 << 11) |
Enables a fix for 480p/576p standard definition modes on the 915GM only. More... | |
#define | TV_ENC_C0_FIX (1 << 10) |
Enables a fix for the 915GM only. More... | |
#define | TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) |
Bits that must be preserved by software. More... | |
#define | TV_FUSE_STATE_MASK (3 << 4) |
#define | TV_FUSE_STATE_ENABLED (0 << 4) |
Read-only state that reports all features enabled. More... | |
#define | TV_FUSE_STATE_NO_MACROVISION (1 << 4) |
Read-only state that reports that Macrovision is disabled in hardware. More... | |
#define | TV_FUSE_STATE_DISABLED (2 << 4) |
Read-only state that reports that TV-out is disabled in hardware. More... | |
#define | TV_TEST_MODE_NORMAL (0 << 0) |
Normal operation. More... | |
#define | TV_TEST_MODE_PATTERN_1 (1 << 0) |
Encoder test pattern 1 - combo pattern. More... | |
#define | TV_TEST_MODE_PATTERN_2 (2 << 0) |
Encoder test pattern 2 - full screen vertical 75% color bars. More... | |
#define | TV_TEST_MODE_PATTERN_3 (3 << 0) |
Encoder test pattern 3 - full screen horizontal 75% color bars. More... | |
#define | TV_TEST_MODE_PATTERN_4 (4 << 0) |
Encoder test pattern 4 - random noise. More... | |
#define | TV_TEST_MODE_PATTERN_5 (5 << 0) |
Encoder test pattern 5 - linear color ramps. More... | |
#define | TV_TEST_MODE_MONITOR_DETECT (7 << 0) |
This test mode forces the DACs to 50% of full output. More... | |
#define | TV_TEST_MODE_MASK (7 << 0) |
#define | TV_DAC 0x68004 |
#define | TV_DAC_SAVE 0x00ffff00 |
#define | TVDAC_STATE_CHG (1UL << 31) |
Reports that DAC state change logic has reported change (RO). More... | |
#define | TVDAC_SENSE_MASK (7 << 28) |
#define | TVDAC_A_SENSE (1 << 30) |
Reports that DAC A voltage is above the detect threshold. More... | |
#define | TVDAC_B_SENSE (1 << 29) |
Reports that DAC B voltage is above the detect threshold. More... | |
#define | TVDAC_C_SENSE (1 << 28) |
Reports that DAC C voltage is above the detect threshold. More... | |
#define | TVDAC_STATE_CHG_EN (1 << 27) |
Enables DAC state detection logic, for load-based TV detection. More... | |
#define | TVDAC_A_SENSE_CTL (1 << 26) |
Sets the DAC A sense value to high. More... | |
#define | TVDAC_B_SENSE_CTL (1 << 25) |
Sets the DAC B sense value to high. More... | |
#define | TVDAC_C_SENSE_CTL (1 << 24) |
Sets the DAC C sense value to high. More... | |
#define | DAC_CTL_OVERRIDE (1 << 7) |
Overrides the ENC_ENABLE and DAC voltage levels. More... | |
#define | ENC_TVDAC_SLEW_FAST (1 << 6) |
Sets the slew rate. More... | |
#define | DAC_A_1_3_V (0 << 4) |
#define | DAC_A_1_1_V (1 << 4) |
#define | DAC_A_0_7_V (2 << 4) |
#define | DAC_A_MASK (3 << 4) |
#define | DAC_B_1_3_V (0 << 2) |
#define | DAC_B_1_1_V (1 << 2) |
#define | DAC_B_0_7_V (2 << 2) |
#define | DAC_B_MASK (3 << 2) |
#define | DAC_C_1_3_V (0 << 0) |
#define | DAC_C_1_1_V (1 << 0) |
#define | DAC_C_0_7_V (2 << 0) |
#define | DAC_C_MASK (3 << 0) |
#define | TV_CSC_Y 0x68010 |
CSC coefficients are stored in a floating point format with 9 bits of mantissa and 2 or 3 bits of exponent. More... | |
#define | TV_RY_MASK 0x07ff0000 |
#define | TV_RY_SHIFT 16 |
#define | TV_GY_MASK 0x00000fff |
#define | TV_GY_SHIFT 0 |
#define | TV_CSC_Y2 0x68014 |
#define | TV_BY_MASK 0x07ff0000 |
#define | TV_BY_SHIFT 16 |
#define | TV_AY_MASK 0x000003ff |
Y attenuation for component video. More... | |
#define | TV_AY_SHIFT 0 |
#define | TV_CSC_U 0x68018 |
#define | TV_RU_MASK 0x07ff0000 |
#define | TV_RU_SHIFT 16 |
#define | TV_GU_MASK 0x000007ff |
#define | TV_GU_SHIFT 0 |
#define | TV_CSC_U2 0x6801c |
#define | TV_BU_MASK 0x07ff0000 |
#define | TV_BU_SHIFT 16 |
#define | TV_AU_MASK 0x000003ff |
U attenuation for component video. More... | |
#define | TV_AU_SHIFT 0 |
#define | TV_CSC_V 0x68020 |
#define | TV_RV_MASK 0x0fff0000 |
#define | TV_RV_SHIFT 16 |
#define | TV_GV_MASK 0x000007ff |
#define | TV_GV_SHIFT 0 |
#define | TV_CSC_V2 0x68024 |
#define | TV_BV_MASK 0x07ff0000 |
#define | TV_BV_SHIFT 16 |
#define | TV_AV_MASK 0x000007ff |
V attenuation for component video. More... | |
#define | TV_AV_SHIFT 0 |
#define | TV_CLR_KNOBS 0x68028 |
#define | TV_BRIGHTNESS_MASK 0xff000000 |
2s-complement brightness adjustment More... | |
#define | TV_BRIGHTNESS_SHIFT 24 |
#define | TV_CONTRAST_MASK 0x00ff0000 |
Contrast adjustment, as a 2.6 unsigned floating point number. More... | |
#define | TV_CONTRAST_SHIFT 16 |
#define | TV_SATURATION_MASK 0x0000ff00 |
Saturation adjustment, as a 2.6 unsigned floating point number. More... | |
#define | TV_SATURATION_SHIFT 8 |
#define | TV_HUE_MASK 0x000000ff |
Hue adjustment, as an integer phase angle in degrees. More... | |
#define | TV_HUE_SHIFT 0 |
#define | TV_CLR_LEVEL 0x6802c |
#define | TV_BLACK_LEVEL_MASK 0x01ff0000 |
Controls the DAC level for black. More... | |
#define | TV_BLACK_LEVEL_SHIFT 16 |
#define | TV_BLANK_LEVEL_MASK 0x000001ff |
Controls the DAC level for blanking. More... | |
#define | TV_BLANK_LEVEL_SHIFT 0 |
#define | TV_H_CTL_1 0x68030 |
#define | TV_HSYNC_END_MASK 0x1fff0000 |
Number of pixels in the hsync. More... | |
#define | TV_HSYNC_END_SHIFT 16 |
#define | TV_HTOTAL_MASK 0x00001fff |
Total number of pixels minus one in the line (display and blanking). More... | |
#define | TV_HTOTAL_SHIFT 0 |
#define | TV_H_CTL_2 0x68034 |
#define | TV_BURST_ENA (1UL << 31) |
Enables the colorburst (needed for non-component color) More... | |
#define | TV_HBURST_START_SHIFT 16 |
Offset of the colorburst from the start of hsync, in pixels minus one. More... | |
#define | TV_HBURST_START_MASK 0x1fff0000 |
#define | TV_HBURST_LEN_SHIFT 0 |
Length of the colorburst. More... | |
#define | TV_HBURST_LEN_MASK 0x0001fff |
#define | TV_H_CTL_3 0x68038 |
#define | TV_HBLANK_END_SHIFT 16 |
End of hblank, measured in pixels minus one from start of hsync. More... | |
#define | TV_HBLANK_END_MASK 0x1fff0000 |
#define | TV_HBLANK_START_SHIFT 0 |
Start of hblank, measured in pixels minus one from start of hsync. More... | |
#define | TV_HBLANK_START_MASK 0x0001fff |
#define | TV_V_CTL_1 0x6803c |
#define | TV_NBR_END_SHIFT 16 |
XXX. More... | |
#define | TV_NBR_END_MASK 0x07ff0000 |
#define | TV_VI_END_F1_SHIFT 8 |
XXX. More... | |
#define | TV_VI_END_F1_MASK 0x00003f00 |
#define | TV_VI_END_F2_SHIFT 0 |
XXX. More... | |
#define | TV_VI_END_F2_MASK 0x0000003f |
#define | TV_V_CTL_2 0x68040 |
#define | TV_VSYNC_LEN_MASK 0x07ff0000 |
Length of vsync, in half lines. More... | |
#define | TV_VSYNC_LEN_SHIFT 16 |
#define | TV_VSYNC_START_F1_MASK 0x00007f00 |
Offset of the start of vsync in field 1, measured in one less than the number of half lines. More... | |
#define | TV_VSYNC_START_F1_SHIFT 8 |
#define | TV_VSYNC_START_F2_MASK 0x0000007f |
Offset of the start of vsync in field 2, measured in one less than the number of half lines. More... | |
#define | TV_VSYNC_START_F2_SHIFT 0 |
#define | TV_V_CTL_3 0x68044 |
#define | TV_EQUAL_ENA (1UL << 31) |
Enables generation of the equalization signal. More... | |
#define | TV_VEQ_LEN_MASK 0x007f0000 |
Length of vsync, in half lines. More... | |
#define | TV_VEQ_LEN_SHIFT 16 |
#define | TV_VEQ_START_F1_MASK 0x0007f00 |
Offset of the start of equalization in field 1, measured in one less than the number of half lines. More... | |
#define | TV_VEQ_START_F1_SHIFT 8 |
#define | TV_VEQ_START_F2_MASK 0x000007f |
Offset of the start of equalization in field 2, measured in one less than the number of half lines. More... | |
#define | TV_VEQ_START_F2_SHIFT 0 |
#define | TV_V_CTL_4 0x68048 |
#define | TV_VBURST_START_F1_MASK 0x003f0000 |
Offset to start of vertical colorburst, measured in one less than the number of lines from vertical start. More... | |
#define | TV_VBURST_START_F1_SHIFT 16 |
#define | TV_VBURST_END_F1_MASK 0x000000ff |
Offset to the end of vertical colorburst, measured in one less than the number of lines from the start of NBR. More... | |
#define | TV_VBURST_END_F1_SHIFT 0 |
#define | TV_V_CTL_5 0x6804c |
#define | TV_VBURST_START_F2_MASK 0x003f0000 |
Offset to start of vertical colorburst, measured in one less than the number of lines from vertical start. More... | |
#define | TV_VBURST_START_F2_SHIFT 16 |
#define | TV_VBURST_END_F2_MASK 0x000000ff |
Offset to the end of vertical colorburst, measured in one less than the number of lines from the start of NBR. More... | |
#define | TV_VBURST_END_F2_SHIFT 0 |
#define | TV_V_CTL_6 0x68050 |
#define | TV_VBURST_START_F3_MASK 0x003f0000 |
Offset to start of vertical colorburst, measured in one less than the number of lines from vertical start. More... | |
#define | TV_VBURST_START_F3_SHIFT 16 |
#define | TV_VBURST_END_F3_MASK 0x000000ff |
Offset to the end of vertical colorburst, measured in one less than the number of lines from the start of NBR. More... | |
#define | TV_VBURST_END_F3_SHIFT 0 |
#define | TV_V_CTL_7 0x68054 |
#define | TV_VBURST_START_F4_MASK 0x003f0000 |
Offset to start of vertical colorburst, measured in one less than the number of lines from vertical start. More... | |
#define | TV_VBURST_START_F4_SHIFT 16 |
#define | TV_VBURST_END_F4_MASK 0x000000ff |
Offset to the end of vertical colorburst, measured in one less than the number of lines from the start of NBR. More... | |
#define | TV_VBURST_END_F4_SHIFT 0 |
#define | TV_SC_CTL_1 0x68060 |
#define | TV_SC_DDA1_EN (1UL << 31) |
Turns on the first subcarrier phase generation DDA. More... | |
#define | TV_SC_DDA2_EN (1 << 30) |
Turns on the first subcarrier phase generation DDA. More... | |
#define | TV_SC_DDA3_EN (1 << 29) |
Turns on the first subcarrier phase generation DDA. More... | |
#define | TV_SC_RESET_EVERY_2 (0 << 24) |
Sets the subcarrier DDA to reset frequency every other field. More... | |
#define | TV_SC_RESET_EVERY_4 (1 << 24) |
Sets the subcarrier DDA to reset frequency every fourth field. More... | |
#define | TV_SC_RESET_EVERY_8 (2 << 24) |
Sets the subcarrier DDA to reset frequency every eighth field. More... | |
#define | TV_SC_RESET_NEVER (3 << 24) |
Sets the subcarrier DDA to never reset the frequency. More... | |
#define | TV_BURST_LEVEL_MASK 0x00ff0000 |
Sets the peak amplitude of the colorburst. More... | |
#define | TV_BURST_LEVEL_SHIFT 16 |
#define | TV_SCDDA1_INC_MASK 0x00000fff |
Sets the increment of the first subcarrier phase generation DDA. More... | |
#define | TV_SCDDA1_INC_SHIFT 0 |
#define | TV_SC_CTL_2 0x68064 |
#define | TV_SCDDA2_SIZE_MASK 0x7fff0000 |
Sets the rollover for the second subcarrier phase generation DDA. More... | |
#define | TV_SCDDA2_SIZE_SHIFT 16 |
#define | TV_SCDDA2_INC_MASK 0x00007fff |
Sets the increent of the second subcarrier phase generation DDA. More... | |
#define | TV_SCDDA2_INC_SHIFT 0 |
#define | TV_SC_CTL_3 0x68068 |
#define | TV_SCDDA3_SIZE_MASK 0x7fff0000 |
Sets the rollover for the third subcarrier phase generation DDA. More... | |
#define | TV_SCDDA3_SIZE_SHIFT 16 |
#define | TV_SCDDA3_INC_MASK 0x00007fff |
Sets the increent of the third subcarrier phase generation DDA. More... | |
#define | TV_SCDDA3_INC_SHIFT 0 |
#define | TV_WIN_POS 0x68070 |
#define | TV_XPOS_MASK 0x1fff0000 |
X coordinate of the display from the start of horizontal active. More... | |
#define | TV_XPOS_SHIFT 16 |
#define | TV_YPOS_MASK 0x00000fff |
Y coordinate of the display from the start of vertical active (NBR) More... | |
#define | TV_YPOS_SHIFT 0 |
#define | TV_WIN_SIZE 0x68074 |
#define | TV_XSIZE_MASK 0x1fff0000 |
Horizontal size of the display window, measured in pixels. More... | |
#define | TV_XSIZE_SHIFT 16 |
#define | TV_YSIZE_MASK 0x00000fff |
Vertical size of the display window, measured in pixels. More... | |
#define | TV_YSIZE_SHIFT 0 |
#define | TV_FILTER_CTL_1 0x68080 |
#define | TV_AUTO_SCALE (1UL << 31) |
Enables automatic scaling calculation. More... | |
#define | TV_V_FILTER_BYPASS (1 << 29) |
Disables the vertical filter. More... | |
#define | TV_VADAPT (1 << 28) |
Enables adaptive vertical filtering. More... | |
#define | TV_VADAPT_MODE_MASK (3 << 26) |
#define | TV_VADAPT_MODE_LEAST (0 << 26) |
Selects the least adaptive vertical filtering mode. More... | |
#define | TV_VADAPT_MODE_MODERATE (1 << 26) |
Selects the moderately adaptive vertical filtering mode. More... | |
#define | TV_VADAPT_MODE_MOST (3 << 26) |
Selects the most adaptive vertical filtering mode. More... | |
#define | TV_HSCALE_FRAC_MASK 0x00003fff |
Sets the horizontal scaling factor. More... | |
#define | TV_HSCALE_FRAC_SHIFT 0 |
#define | TV_FILTER_CTL_2 0x68084 |
#define | TV_VSCALE_INT_MASK 0x00038000 |
Sets the integer part of the 3.15 fixed-point vertical scaling factor. More... | |
#define | TV_VSCALE_INT_SHIFT 15 |
#define | TV_VSCALE_FRAC_MASK 0x00007fff |
Sets the fractional part of the 3.15 fixed-point vertical scaling factor. More... | |
#define | TV_VSCALE_FRAC_SHIFT 0 |
#define | TV_FILTER_CTL_3 0x68088 |
#define | TV_VSCALE_IP_INT_MASK 0x00038000 |
Sets the integer part of the 3.15 fixed-point vertical scaling factor. More... | |
#define | TV_VSCALE_IP_INT_SHIFT 15 |
#define | TV_VSCALE_IP_FRAC_MASK 0x00007fff |
Sets the fractional part of the 3.15 fixed-point vertical scaling factor. More... | |
#define | TV_VSCALE_IP_FRAC_SHIFT 0 |
#define | TV_CC_CONTROL 0x68090 |
#define | TV_CC_ENABLE (1UL << 31) |
#define | TV_CC_FID_MASK (1 << 27) |
Specifies which field to send the CC data in. More... | |
#define | TV_CC_FID_SHIFT 27 |
#define | TV_CC_HOFF_MASK 0x03ff0000 |
Sets the horizontal position of the CC data. More... | |
#define | TV_CC_HOFF_SHIFT 16 |
#define | TV_CC_LINE_MASK 0x0000003f |
Sets the vertical position of the CC data. More... | |
#define | TV_CC_LINE_SHIFT 0 |
#define | TV_CC_DATA 0x68094 |
#define | TV_CC_RDY (1UL << 31) |
#define | TV_CC_DATA_2_MASK 0x007f0000 |
Second word of CC data to be transmitted. More... | |
#define | TV_CC_DATA_2_SHIFT 16 |
#define | TV_CC_DATA_1_MASK 0x0000007f |
First word of CC data to be transmitted. More... | |
#define | TV_CC_DATA_1_SHIFT 0 |
#define | TV_H_LUMA_0 0x68100 |
#define | TV_H_LUMA_59 0x681ec |
#define | TV_H_CHROMA_0 0x68200 |
#define | TV_H_CHROMA_59 0x682ec |
#define | TV_V_LUMA_0 0x68300 |
#define | TV_V_LUMA_42 0x683a8 |
#define | TV_V_CHROMA_0 0x68400 |
#define | TV_V_CHROMA_42 0x684a8 |
#define | DP_A 0x64000 /* eDP */ |
#define | DP_B 0x64100 |
#define | DP_C 0x64200 |
#define | DP_D 0x64300 |
#define | DP_PORT_EN (1UL << 31) |
#define | DP_PIPEB_SELECT (1 << 30) |
#define | DP_PIPE_MASK (1 << 30) |
#define | DP_LINK_TRAIN_PAT_1 (0 << 28) |
#define | DP_LINK_TRAIN_PAT_2 (1 << 28) |
#define | DP_LINK_TRAIN_PAT_IDLE (2 << 28) |
#define | DP_LINK_TRAIN_OFF (3 << 28) |
#define | DP_LINK_TRAIN_MASK (3 << 28) |
#define | DP_LINK_TRAIN_SHIFT 28 |
#define | DP_LINK_TRAIN_PAT_1_CPT (0 << 8) |
#define | DP_LINK_TRAIN_PAT_2_CPT (1 << 8) |
#define | DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) |
#define | DP_LINK_TRAIN_OFF_CPT (3 << 8) |
#define | DP_LINK_TRAIN_MASK_CPT (7 << 8) |
#define | DP_LINK_TRAIN_SHIFT_CPT 8 |
#define | DP_VOLTAGE_0_4 (0 << 25) |
#define | DP_VOLTAGE_0_6 (1 << 25) |
#define | DP_VOLTAGE_0_8 (2 << 25) |
#define | DP_VOLTAGE_1_2 (3 << 25) |
#define | DP_VOLTAGE_MASK (7 << 25) |
#define | DP_VOLTAGE_SHIFT 25 |
#define | DP_PRE_EMPHASIS_0 (0 << 22) |
#define | DP_PRE_EMPHASIS_3_5 (1 << 22) |
#define | DP_PRE_EMPHASIS_6 (2 << 22) |
#define | DP_PRE_EMPHASIS_9_5 (3 << 22) |
#define | DP_PRE_EMPHASIS_MASK (7 << 22) |
#define | DP_PRE_EMPHASIS_SHIFT 22 |
#define | DP_PORT_WIDTH_1 (0 << 19) |
#define | DP_PORT_WIDTH_2 (1 << 19) |
#define | DP_PORT_WIDTH_4 (3 << 19) |
#define | DP_PORT_WIDTH_MASK (7 << 19) |
#define | DP_ENHANCED_FRAMING (1 << 18) |
#define | DP_PLL_FREQ_270MHZ (0 << 16) |
#define | DP_PLL_FREQ_160MHZ (1 << 16) |
#define | DP_PLL_FREQ_MASK (3 << 16) |
#define | DP_PORT_REVERSAL (1 << 15) |
locked once port is enabled More... | |
#define | DP_PLL_ENABLE (1 << 14) |
#define | DP_CLOCK_OUTPUT_ENABLE (1 << 13) |
sends the clock on lane 15 of the PEG for debug More... | |
#define | DP_SCRAMBLING_DISABLE (1 << 12) |
#define | DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) |
#define | DP_COLOR_RANGE_16_235 (1 << 8) |
limit RGB values to avoid confusing TVs More... | |
#define | DP_AUDIO_OUTPUT_ENABLE (1 << 6) |
Turn on the audio link. More... | |
#define | DP_SYNC_VS_HIGH (1 << 4) |
vs and hs sync polarity More... | |
#define | DP_SYNC_HS_HIGH (1 << 3) |
#define | DP_DETECTED (1 << 2) |
A fantasy. More... | |
#define | DPA_AUX_CH_CTL 0x64010 |
The aux channel provides a way to talk to the signal sink for DDC etc. More... | |
#define | DPA_AUX_CH_DATA1 0x64014 |
#define | DPA_AUX_CH_DATA2 0x64018 |
#define | DPA_AUX_CH_DATA3 0x6401c |
#define | DPA_AUX_CH_DATA4 0x64020 |
#define | DPA_AUX_CH_DATA5 0x64024 |
#define | DPB_AUX_CH_CTL 0x64110 |
#define | DPB_AUX_CH_DATA1 0x64114 |
#define | DPB_AUX_CH_DATA2 0x64118 |
#define | DPB_AUX_CH_DATA3 0x6411c |
#define | DPB_AUX_CH_DATA4 0x64120 |
#define | DPB_AUX_CH_DATA5 0x64124 |
#define | DPC_AUX_CH_CTL 0x64210 |
#define | DPC_AUX_CH_DATA1 0x64214 |
#define | DPC_AUX_CH_DATA2 0x64218 |
#define | DPC_AUX_CH_DATA3 0x6421c |
#define | DPC_AUX_CH_DATA4 0x64220 |
#define | DPC_AUX_CH_DATA5 0x64224 |
#define | DPD_AUX_CH_CTL 0x64310 |
#define | DPD_AUX_CH_DATA1 0x64314 |
#define | DPD_AUX_CH_DATA2 0x64318 |
#define | DPD_AUX_CH_DATA3 0x6431c |
#define | DPD_AUX_CH_DATA4 0x64320 |
#define | DPD_AUX_CH_DATA5 0x64324 |
#define | DP_AUX_CH_CTL_SEND_BUSY (1UL << 31) |
#define | DP_AUX_CH_CTL_DONE (1 << 30) |
#define | DP_AUX_CH_CTL_INTERRUPT (1 << 29) |
#define | DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) |
#define | DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) |
#define | DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) |
#define | DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) |
#define | DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) |
#define | DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) |
#define | DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) |
#define | DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) |
#define | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 |
#define | DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) |
#define | DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 |
#define | DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) |
#define | DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) |
#define | DP_AUX_CH_CTL_SYNC_TEST (1 << 13) |
#define | DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) |
#define | DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) |
#define | DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) |
#define | DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 |
#define | _PIPEA_GMCH_DATA_M 0x70050 |
#define | _PIPEB_GMCH_DATA_M 0x71050 |
#define | PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) |
#define | PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 |
#define | PIPE_GMCH_DATA_M_MASK (0xffffff) |
#define | _PIPEA_GMCH_DATA_N 0x70054 |
#define | _PIPEB_GMCH_DATA_N 0x71054 |
#define | PIPE_GMCH_DATA_N_MASK (0xffffff) |
#define | _PIPEA_DP_LINK_M 0x70060 |
#define | _PIPEB_DP_LINK_M 0x71060 |
#define | PIPEA_DP_LINK_M_MASK (0xffffff) |
#define | _PIPEA_DP_LINK_N 0x70064 |
#define | _PIPEB_DP_LINK_N 0x71064 |
#define | PIPEA_DP_LINK_N_MASK (0xffffff) |
#define | PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) |
#define | PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) |
#define | PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M) |
#define | PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N) |
#define | _PIPEADSL 0x70000 |
#define | DSL_LINEMASK_GEN2 0x00000fff |
#define | DSL_LINEMASK_GEN3 0x00001fff |
#define | _PIPEACONF 0x70008 |
#define | PIPECONF_ENABLE (1UL<<31) |
#define | PIPECONF_DISABLE 0 |
#define | PIPECONF_DOUBLE_WIDE (1<<30) |
#define | I965_PIPECONF_ACTIVE (1<<30) |
#define | PIPECONF_FRAME_START_DELAY_MASK (3<<27) |
#define | PIPECONF_SINGLE_WIDE 0 |
#define | PIPECONF_PIPE_UNLOCKED 0 |
#define | PIPECONF_PIPE_LOCKED (1<<25) |
#define | PIPECONF_PALETTE 0 |
#define | PIPECONF_GAMMA (1<<24) |
#define | PIPECONF_FORCE_BORDER (1<<25) |
#define | PIPECONF_INTERLACE_MASK (7 << 21) |
#define | PIPECONF_INTERLACE_MASK_HSW (3 << 21) |
#define | PIPECONF_PROGRESSIVE (0 << 21) |
#define | PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ |
#define | PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ |
#define | PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) |
#define | PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ |
#define | PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) |
#define | PIPECONF_INTERLACED_ILK (3 << 21) |
#define | PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ |
#define | PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ |
#define | PIPECONF_CXSR_DOWNCLOCK (1<<16) |
#define | PIPECONF_BPP_MASK (0x000000e0) |
#define | PIPECONF_BPP_8 (0<<5) |
#define | PIPECONF_BPP_10 (1<<5) |
#define | PIPECONF_BPP_6 (2<<5) |
#define | PIPECONF_BPP_12 (3<<5) |
#define | PIPECONF_DITHER_EN (1<<4) |
#define | PIPECONF_DITHER_TYPE_MASK (0x0000000c) |
#define | PIPECONF_DITHER_TYPE_SP (0<<2) |
#define | PIPECONF_DITHER_TYPE_ST1 (1<<2) |
#define | PIPECONF_DITHER_TYPE_ST2 (2<<2) |
#define | PIPECONF_DITHER_TYPE_TEMP (3<<2) |
#define | _PIPEASTAT 0x70024 |
#define | PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) |
#define | SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30) |
#define | PIPE_CRC_ERROR_ENABLE (1UL<<29) |
#define | PIPE_CRC_DONE_ENABLE (1UL<<28) |
#define | PIPE_GMBUS_EVENT_ENABLE (1UL<<27) |
#define | PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) |
#define | PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) |
#define | PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) |
#define | PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) |
#define | PIPE_DPST_EVENT_ENABLE (1UL<<23) |
#define | SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<26) |
#define | PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) |
#define | PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) |
#define | PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) |
#define | PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ |
#define | PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ |
#define | PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) |
#define | PIPEA_HBLANK_INT_EN_VLV (1UL<<16) |
#define | PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) |
#define | SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15) |
#define | SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<15) |
#define | PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) |
#define | PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) |
#define | PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) |
#define | PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10) |
#define | PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) |
#define | PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) |
#define | PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) |
#define | PIPE_DPST_EVENT_STATUS (1UL<<7) |
#define | PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) |
#define | PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) |
#define | PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) |
#define | PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ |
#define | PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ |
#define | PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) |
#define | PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) |
#define | PIPE_BPC_MASK (7 << 5) /* Ironlake */ |
#define | PIPE_8BPC (0 << 5) |
#define | PIPE_10BPC (1 << 5) |
#define | PIPE_6BPC (2 << 5) |
#define | PIPE_12BPC (3 << 5) |
#define | PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) |
#define | PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF) |
#define | PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) |
#define | PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) |
#define | PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) |
#define | PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) |
#define | VLV_DPFLIPSTAT 0x70028 |
#define | PIPEB_LINE_COMPARE_INT_EN (1<<29) |
#define | PIPEB_HLINE_INT_EN (1<<28) |
#define | PIPEB_VBLANK_INT_EN (1<<27) |
#define | SPRITED_FLIPDONE_INT_EN (1<<26) |
#define | SPRITEC_FLIPDONE_INT_EN (1<<25) |
#define | PLANEB_FLIPDONE_INT_EN (1<<24) |
#define | PIPEA_LINE_COMPARE_INT_EN (1<<21) |
#define | PIPEA_HLINE_INT_EN (1<<20) |
#define | PIPEA_VBLANK_INT_EN (1<<19) |
#define | SPRITEB_FLIPDONE_INT_EN (1<<18) |
#define | SPRITEA_FLIPDONE_INT_EN (1<<17) |
#define | PLANEA_FLIPDONE_INT_EN (1<<16) |
#define | DPINVGTT 0x7002c /* VLV only */ |
#define | CURSORB_INVALID_GTT_INT_EN (1<<23) |
#define | CURSORA_INVALID_GTT_INT_EN (1<<22) |
#define | SPRITED_INVALID_GTT_INT_EN (1<<21) |
#define | SPRITEC_INVALID_GTT_INT_EN (1<<20) |
#define | PLANEB_INVALID_GTT_INT_EN (1<<19) |
#define | SPRITEB_INVALID_GTT_INT_EN (1<<18) |
#define | SPRITEA_INVALID_GTT_INT_EN (1<<17) |
#define | PLANEA_INVALID_GTT_INT_EN (1<<16) |
#define | DPINVGTT_EN_MASK 0xff0000 |
#define | CURSORB_INVALID_GTT_STATUS (1<<7) |
#define | CURSORA_INVALID_GTT_STATUS (1<<6) |
#define | SPRITED_INVALID_GTT_STATUS (1<<5) |
#define | SPRITEC_INVALID_GTT_STATUS (1<<4) |
#define | PLANEB_INVALID_GTT_STATUS (1<<3) |
#define | SPRITEB_INVALID_GTT_STATUS (1<<2) |
#define | SPRITEA_INVALID_GTT_STATUS (1<<1) |
#define | PLANEA_INVALID_GTT_STATUS (1<<0) |
#define | DPINVGTT_STATUS_MASK 0xff |
#define | DSPARB 0x70030 |
#define | DSPARB_CSTART_MASK (0x7f << 7) |
#define | DSPARB_CSTART_SHIFT 7 |
#define | DSPARB_BSTART_MASK (0x7f) |
#define | DSPARB_BSTART_SHIFT 0 |
#define | DSPARB_BEND_SHIFT 9 /* on 855 */ |
#define | DSPARB_AEND_SHIFT 0 |
#define | DSPFW1 0x70034 |
#define | DSPFW_SR_SHIFT 23 |
#define | DSPFW_SR_MASK (0x1ff<<23) |
#define | DSPFW_CURSORB_SHIFT 16 |
#define | DSPFW_CURSORB_MASK (0x3f<<16) |
#define | DSPFW_PLANEB_SHIFT 8 |
#define | DSPFW_PLANEB_MASK (0x7f<<8) |
#define | DSPFW_PLANEA_MASK (0x7f) |
#define | DSPFW2 0x70038 |
#define | DSPFW_CURSORA_MASK 0x00003f00 |
#define | DSPFW_CURSORA_SHIFT 8 |
#define | DSPFW_PLANEC_MASK (0x7f) |
#define | DSPFW3 0x7003c |
#define | DSPFW_HPLL_SR_EN (1UL<<31) |
#define | DSPFW_CURSOR_SR_SHIFT 24 |
#define | PINEVIEW_SELF_REFRESH_EN (1<<30) |
#define | DSPFW_CURSOR_SR_MASK (0x3f<<24) |
#define | DSPFW_HPLL_CURSOR_SHIFT 16 |
#define | DSPFW_HPLL_CURSOR_MASK (0x3f<<16) |
#define | DSPFW_HPLL_SR_MASK (0x1ff) |
#define | DRAIN_LATENCY_PRECISION_32 32 |
#define | DRAIN_LATENCY_PRECISION_16 16 |
#define | VLV_DDL1 0x70050 |
#define | DDL_CURSORA_PRECISION_32 (1UL<<31) |
#define | DDL_CURSORA_PRECISION_16 (0UL<<31) |
#define | DDL_CURSORA_SHIFT 24 |
#define | DDL_PLANEA_PRECISION_32 (1<<7) |
#define | DDL_PLANEA_PRECISION_16 (0<<7) |
#define | VLV_DDL2 0x70054 |
#define | DDL_CURSORB_PRECISION_32 (1UL<<31) |
#define | DDL_CURSORB_PRECISION_16 (0UL<<31) |
#define | DDL_CURSORB_SHIFT 24 |
#define | DDL_PLANEB_PRECISION_32 (1<<7) |
#define | DDL_PLANEB_PRECISION_16 (0<<7) |
#define | G4X_FIFO_LINE_SIZE 64 |
#define | I915_FIFO_LINE_SIZE 64 |
#define | I830_FIFO_LINE_SIZE 32 |
#define | VALLEYVIEW_FIFO_SIZE 255 |
#define | G4X_FIFO_SIZE 127 |
#define | I965_FIFO_SIZE 512 |
#define | I945_FIFO_SIZE 127 |
#define | I915_FIFO_SIZE 95 |
#define | I855GM_FIFO_SIZE 127 /* In cachelines */ |
#define | I830_FIFO_SIZE 95 |
#define | VALLEYVIEW_MAX_WM 0xff |
#define | G4X_MAX_WM 0x3f |
#define | I915_MAX_WM 0x3f |
#define | PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ |
#define | PINEVIEW_FIFO_LINE_SIZE 64 |
#define | PINEVIEW_MAX_WM 0x1ff |
#define | PINEVIEW_DFT_WM 0x3f |
#define | PINEVIEW_DFT_HPLLOFF_WM 0 |
#define | PINEVIEW_GUARD_WM 10 |
#define | PINEVIEW_CURSOR_FIFO 64 |
#define | PINEVIEW_CURSOR_MAX_WM 0x3f |
#define | PINEVIEW_CURSOR_DFT_WM 0 |
#define | PINEVIEW_CURSOR_GUARD_WM 5 |
#define | VALLEYVIEW_CURSOR_MAX_WM 64 |
#define | I965_CURSOR_FIFO 64 |
#define | I965_CURSOR_MAX_WM 32 |
#define | I965_CURSOR_DFT_WM 8 |
#define | WM0_PIPEA_ILK 0x45100 |
#define | WM0_PIPE_PLANE_MASK (0x7f<<16) |
#define | WM0_PIPE_PLANE_SHIFT 16 |
#define | WM0_PIPE_SPRITE_MASK (0x3f<<8) |
#define | WM0_PIPE_SPRITE_SHIFT 8 |
#define | WM0_PIPE_CURSOR_MASK (0x1f) |
#define | WM0_PIPEB_ILK 0x45104 |
#define | WM0_PIPEC_IVB 0x45200 |
#define | WM1_LP_ILK 0x45108 |
#define | WM1_LP_SR_EN (1UL<<31) |
#define | WM1_LP_LATENCY_SHIFT 24 |
#define | WM1_LP_LATENCY_MASK (0x7f<<24) |
#define | WM1_LP_FBC_MASK (0xf<<20) |
#define | WM1_LP_FBC_SHIFT 20 |
#define | WM1_LP_SR_MASK (0x1ff<<8) |
#define | WM1_LP_SR_SHIFT 8 |
#define | WM1_LP_CURSOR_MASK (0x3f) |
#define | WM2_LP_ILK 0x4510c |
#define | WM2_LP_EN (1UL<<31) |
#define | WM3_LP_ILK 0x45110 |
#define | WM3_LP_EN (1UL<<31) |
#define | WM1S_LP_ILK 0x45120 |
#define | WM2S_LP_IVB 0x45124 |
#define | WM3S_LP_IVB 0x45128 |
#define | WM1S_LP_EN (1UL<<31) |
#define | MLTR_ILK 0x11222 |
#define | MLTR_WM1_SHIFT 0 |
#define | MLTR_WM2_SHIFT 8 |
#define | ILK_SRLT_MASK 0x3f |
#define | ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK) |
#define | ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT) |
#define | ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT) |
#define | ILK_DISPLAY_FIFO 128 |
#define | ILK_DISPLAY_MAXWM 64 |
#define | ILK_DISPLAY_DFTWM 8 |
#define | ILK_CURSOR_FIFO 32 |
#define | ILK_CURSOR_MAXWM 16 |
#define | ILK_CURSOR_DFTWM 8 |
#define | ILK_DISPLAY_SR_FIFO 512 |
#define | ILK_DISPLAY_MAX_SRWM 0x1ff |
#define | ILK_DISPLAY_DFT_SRWM 0x3f |
#define | ILK_CURSOR_SR_FIFO 64 |
#define | ILK_CURSOR_MAX_SRWM 0x3f |
#define | ILK_CURSOR_DFT_SRWM 8 |
#define | ILK_FIFO_LINE_SIZE 64 |
#define | SNB_DISPLAY_FIFO 128 |
#define | SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */ |
#define | SNB_DISPLAY_DFTWM 8 |
#define | SNB_CURSOR_FIFO 32 |
#define | SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */ |
#define | SNB_CURSOR_DFTWM 8 |
#define | SNB_DISPLAY_SR_FIFO 512 |
#define | SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */ |
#define | SNB_DISPLAY_DFT_SRWM 0x3f |
#define | SNB_CURSOR_SR_FIFO 64 |
#define | SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */ |
#define | SNB_CURSOR_DFT_SRWM 8 |
#define | SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */ |
#define | SNB_FIFO_LINE_SIZE 64 |
#define | _PIPEAFRAMEHIGH 0x70040 |
#define | PIPE_FRAME_HIGH_MASK 0x0000ffff |
#define | PIPE_FRAME_HIGH_SHIFT 0 |
#define | _PIPEAFRAMEPIXEL 0x70044 |
#define | PIPE_FRAME_LOW_MASK 0xff000000 |
#define | PIPE_FRAME_LOW_SHIFT 24 |
#define | PIPE_PIXEL_MASK 0x00ffffff |
#define | PIPE_PIXEL_SHIFT 0 |
#define | _PIPEA_FRMCOUNT_GM45 0x70040 |
#define | _PIPEA_FLIPCOUNT_GM45 0x70044 |
#define | PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45) |
#define | _CURACNTR 0x70080 |
#define | CURSOR_ENABLE 0x80000000 |
#define | CURSOR_GAMMA_ENABLE 0x40000000 |
#define | CURSOR_STRIDE_MASK 0x30000000 |
#define | CURSOR_FORMAT_SHIFT 24 |
#define | CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) |
#define | CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) |
#define | CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) |
#define | CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) |
#define | CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) |
#define | CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) |
#define | CURSOR_MODE 0x27 |
#define | CURSOR_MODE_DISABLE 0x00 |
#define | CURSOR_MODE_64_32B_AX 0x07 |
#define | CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) |
#define | MCURSOR_PIPE_SELECT (1 << 28) |
#define | MCURSOR_PIPE_A 0x00 |
#define | MCURSOR_PIPE_B (1 << 28) |
#define | MCURSOR_GAMMA_ENABLE (1 << 26) |
#define | _CURABASE 0x70084 |
#define | _CURAPOS 0x70088 |
#define | CURSOR_POS_MASK 0x007FF |
#define | CURSOR_POS_SIGN 0x8000 |
#define | CURSOR_X_SHIFT 0 |
#define | CURSOR_Y_SHIFT 16 |
#define | CURSIZE 0x700a0 |
#define | _CURBCNTR 0x700c0 |
#define | _CURBBASE 0x700c4 |
#define | _CURBPOS 0x700c8 |
#define | _CURBCNTR_IVB 0x71080 |
#define | _CURBBASE_IVB 0x71084 |
#define | _CURBPOS_IVB 0x71088 |
#define | CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR) |
#define | CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE) |
#define | CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS) |
#define | CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB) |
#define | CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB) |
#define | CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB) |
#define | _DSPACNTR 0x70180 |
#define | DISPLAY_PLANE_ENABLE (1UL<<31) |
#define | DISPLAY_PLANE_DISABLE 0 |
#define | DISPPLANE_GAMMA_ENABLE (1<<30) |
#define | DISPPLANE_GAMMA_DISABLE 0 |
#define | DISPPLANE_PIXFORMAT_MASK (0xf<<26) |
#define | DISPPLANE_YUV422 (0x0<<26) |
#define | DISPPLANE_8BPP (0x2<<26) |
#define | DISPPLANE_BGRA555 (0x3<<26) |
#define | DISPPLANE_BGRX555 (0x4<<26) |
#define | DISPPLANE_BGRX565 (0x5<<26) |
#define | DISPPLANE_BGRX888 (0x6<<26) |
#define | DISPPLANE_BGRA888 (0x7<<26) |
#define | DISPPLANE_RGBX101010 (0x8<<26) |
#define | DISPPLANE_RGBA101010 (0x9<<26) |
#define | DISPPLANE_BGRX101010 (0xa<<26) |
#define | DISPPLANE_RGBX161616 (0xc<<26) |
#define | DISPPLANE_RGBX888 (0xe<<26) |
#define | DISPPLANE_RGBA888 (0xf<<26) |
#define | DISPPLANE_STEREO_ENABLE (1<<25) |
#define | DISPPLANE_STEREO_DISABLE 0 |
#define | DISPPLANE_SEL_PIPE_SHIFT 24 |
#define | DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) |
#define | DISPPLANE_SEL_PIPE_A 0 |
#define | DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) |
#define | DISPPLANE_SRC_KEY_ENABLE (1<<22) |
#define | DISPPLANE_SRC_KEY_DISABLE 0 |
#define | DISPPLANE_LINE_DOUBLE (1<<20) |
#define | DISPPLANE_NO_LINE_DOUBLE 0 |
#define | DISPPLANE_STEREO_POLARITY_FIRST 0 |
#define | DISPPLANE_STEREO_POLARITY_SECOND (1<<18) |
#define | DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ |
#define | DISPPLANE_TILED (1<<10) |
#define | _DSPAADDR 0x70184 |
#define | _DSPASTRIDE 0x70188 |
#define | _DSPAPOS 0x7018C /* reserved */ |
#define | _DSPASIZE 0x70190 |
#define | _DSPASURF 0x7019C /* 965+ only */ |
#define | _DSPATILEOFF 0x701A4 /* 965+ only */ |
#define | _DSPAOFFSET 0x701A4 /* HSW */ |
#define | _DSPASURFLIVE 0x701AC |
#define | DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) |
#define | DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) |
#define | DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) |
#define | DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) |
#define | DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) |
#define | DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) |
#define | DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) |
#define | DSPLINOFF(plane) DSPADDR(plane) |
#define | DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET) |
#define | DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE) |
#define | DISP_BASEADDR_MASK (0xfffff000) |
#define | I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) |
#define | I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) |
#define | I915_MODIFY_DISPBASE(reg, gfx_addr) (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg)))) |
#define | SWF00 0x71410 |
#define | SWF01 0x71414 |
#define | SWF02 0x71418 |
#define | SWF03 0x7141c |
#define | SWF04 0x71420 |
#define | SWF05 0x71424 |
#define | SWF06 0x71428 |
#define | SWF10 0x70410 |
#define | SWF11 0x70414 |
#define | SWF14 0x71420 |
#define | SWF30 0x72414 |
#define | SWF31 0x72418 |
#define | SWF32 0x7241c |
#define | _PIPEBDSL 0x71000 |
#define | _PIPEBCONF 0x71008 |
#define | _PIPEBSTAT 0x71024 |
#define | _PIPEBFRAMEHIGH 0x71040 |
#define | _PIPEBFRAMEPIXEL 0x71044 |
#define | _PIPEB_FRMCOUNT_GM45 0x71040 |
#define | _PIPEB_FLIPCOUNT_GM45 0x71044 |
#define | _DSPBCNTR 0x71180 |
#define | DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) |
#define | DISPPLANE_ALPHA_TRANS_DISABLE 0 |
#define | DISPPLANE_SPRITE_ABOVE_DISPLAY 0 |
#define | DISPPLANE_SPRITE_ABOVE_OVERLAY (1) |
#define | _DSPBADDR 0x71184 |
#define | _DSPBSTRIDE 0x71188 |
#define | _DSPBPOS 0x7118C |
#define | _DSPBSIZE 0x71190 |
#define | _DSPBSURF 0x7119C |
#define | _DSPBTILEOFF 0x711A4 |
#define | _DSPBOFFSET 0x711A4 |
#define | _DSPBSURFLIVE 0x711AC |
#define | _DVSACNTR 0x72180 |
#define | DVS_ENABLE (1UL<<31) |
#define | DVS_GAMMA_ENABLE (1<<30) |
#define | DVS_PIXFORMAT_MASK (3<<25) |
#define | DVS_FORMAT_YUV422 (0<<25) |
#define | DVS_FORMAT_RGBX101010 (1<<25) |
#define | DVS_FORMAT_RGBX888 (2<<25) |
#define | DVS_FORMAT_RGBX161616 (3<<25) |
#define | DVS_SOURCE_KEY (1<<22) |
#define | DVS_RGB_ORDER_XBGR (1<<20) |
#define | DVS_YUV_BYTE_ORDER_MASK (3<<16) |
#define | DVS_YUV_ORDER_YUYV (0<<16) |
#define | DVS_YUV_ORDER_UYVY (1<<16) |
#define | DVS_YUV_ORDER_YVYU (2<<16) |
#define | DVS_YUV_ORDER_VYUY (3<<16) |
#define | DVS_DEST_KEY (1<<2) |
#define | DVS_TRICKLE_FEED_DISABLE (1<<14) |
#define | DVS_TILED (1<<10) |
#define | _DVSALINOFF 0x72184 |
#define | _DVSASTRIDE 0x72188 |
#define | _DVSAPOS 0x7218c |
#define | _DVSASIZE 0x72190 |
#define | _DVSAKEYVAL 0x72194 |
#define | _DVSAKEYMSK 0x72198 |
#define | _DVSASURF 0x7219c |
#define | _DVSAKEYMAXVAL 0x721a0 |
#define | _DVSATILEOFF 0x721a4 |
#define | _DVSASURFLIVE 0x721ac |
#define | _DVSASCALE 0x72204 |
#define | DVS_SCALE_ENABLE (1UL<<31) |
#define | DVS_FILTER_MASK (3<<29) |
#define | DVS_FILTER_MEDIUM (0<<29) |
#define | DVS_FILTER_ENHANCING (1<<29) |
#define | DVS_FILTER_SOFTENING (2<<29) |
#define | DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ |
#define | DVS_VERTICAL_OFFSET_ENABLE (1<<27) |
#define | _DVSAGAMC 0x72300 |
#define | _DVSBCNTR 0x73180 |
#define | _DVSBLINOFF 0x73184 |
#define | _DVSBSTRIDE 0x73188 |
#define | _DVSBPOS 0x7318c |
#define | _DVSBSIZE 0x73190 |
#define | _DVSBKEYVAL 0x73194 |
#define | _DVSBKEYMSK 0x73198 |
#define | _DVSBSURF 0x7319c |
#define | _DVSBKEYMAXVAL 0x731a0 |
#define | _DVSBTILEOFF 0x731a4 |
#define | _DVSBSURFLIVE 0x731ac |
#define | _DVSBSCALE 0x73204 |
#define | _DVSBGAMC 0x73300 |
#define | DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) |
#define | DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) |
#define | DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) |
#define | DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) |
#define | DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) |
#define | DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) |
#define | DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) |
#define | DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) |
#define | DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) |
#define | DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) |
#define | DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) |
#define | DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) |
#define | _SPRA_CTL 0x70280 |
#define | SPRITE_ENABLE (1UL<<31) |
#define | SPRITE_GAMMA_ENABLE (1<<30) |
#define | SPRITE_PIXFORMAT_MASK (7<<25) |
#define | SPRITE_FORMAT_YUV422 (0<<25) |
#define | SPRITE_FORMAT_RGBX101010 (1<<25) |
#define | SPRITE_FORMAT_RGBX888 (2<<25) |
#define | SPRITE_FORMAT_RGBX161616 (3<<25) |
#define | SPRITE_FORMAT_YUV444 (4<<25) |
#define | SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ |
#define | SPRITE_CSC_ENABLE (1<<24) |
#define | SPRITE_SOURCE_KEY (1<<22) |
#define | SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ |
#define | SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) |
#define | SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ |
#define | SPRITE_YUV_BYTE_ORDER_MASK (3<<16) |
#define | SPRITE_YUV_ORDER_YUYV (0<<16) |
#define | SPRITE_YUV_ORDER_UYVY (1<<16) |
#define | SPRITE_YUV_ORDER_YVYU (2<<16) |
#define | SPRITE_YUV_ORDER_VYUY (3<<16) |
#define | SPRITE_TRICKLE_FEED_DISABLE (1<<14) |
#define | SPRITE_INT_GAMMA_ENABLE (1<<13) |
#define | SPRITE_TILED (1<<10) |
#define | SPRITE_DEST_KEY (1<<2) |
#define | _SPRA_LINOFF 0x70284 |
#define | _SPRA_STRIDE 0x70288 |
#define | _SPRA_POS 0x7028c |
#define | _SPRA_SIZE 0x70290 |
#define | _SPRA_KEYVAL 0x70294 |
#define | _SPRA_KEYMSK 0x70298 |
#define | _SPRA_SURF 0x7029c |
#define | _SPRA_KEYMAX 0x702a0 |
#define | _SPRA_TILEOFF 0x702a4 |
#define | _SPRA_OFFSET 0x702a4 |
#define | _SPRA_SURFLIVE 0x702ac |
#define | _SPRA_SCALE 0x70304 |
#define | SPRITE_SCALE_ENABLE (1UL<<31) |
#define | SPRITE_FILTER_MASK (3<<29) |
#define | SPRITE_FILTER_MEDIUM (0<<29) |
#define | SPRITE_FILTER_ENHANCING (1<<29) |
#define | SPRITE_FILTER_SOFTENING (2<<29) |
#define | SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ |
#define | SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) |
#define | _SPRA_GAMC 0x70400 |
#define | _SPRB_CTL 0x71280 |
#define | _SPRB_LINOFF 0x71284 |
#define | _SPRB_STRIDE 0x71288 |
#define | _SPRB_POS 0x7128c |
#define | _SPRB_SIZE 0x71290 |
#define | _SPRB_KEYVAL 0x71294 |
#define | _SPRB_KEYMSK 0x71298 |
#define | _SPRB_SURF 0x7129c |
#define | _SPRB_KEYMAX 0x712a0 |
#define | _SPRB_TILEOFF 0x712a4 |
#define | _SPRB_OFFSET 0x712a4 |
#define | _SPRB_SURFLIVE 0x712ac |
#define | _SPRB_SCALE 0x71304 |
#define | _SPRB_GAMC 0x71400 |
#define | SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) |
#define | SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) |
#define | SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) |
#define | SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) |
#define | SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) |
#define | SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) |
#define | SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) |
#define | SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) |
#define | SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) |
#define | SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) |
#define | SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) |
#define | SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) |
#define | SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) |
#define | SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) |
#define | VGACNTRL 0x71400 |
#define | VGA_DISP_DISABLE (1UL << 31) |
#define | VGA_2X_MODE (1 << 30) |
#define | VGA_PIPE_B_SELECT (1 << 29) |
#define | CPU_VGACNTRL 0x41000 |
#define | CPU_VGA_DISABLE (1UL<<31) |
#define | DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 |
#define | DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) |
#define | DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) |
#define | DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) |
#define | DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) |
#define | DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) |
#define | DIGITAL_PORTA_NO_DETECT (0 << 0) |
#define | DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) |
#define | DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) |
#define | RR_HW_CTL 0x45300 |
#define | RR_HW_LOW_POWER_FRAMES_MASK 0xff |
#define | RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 |
#define | FDI_PLL_BIOS_0 0x46000 |
#define | FDI_PLL_FB_CLOCK_MASK 0xff |
#define | FDI_PLL_BIOS_1 0x46004 |
#define | FDI_PLL_BIOS_2 0x46008 |
#define | DISPLAY_PORT_PLL_BIOS_0 0x4600c |
#define | DISPLAY_PORT_PLL_BIOS_1 0x46010 |
#define | DISPLAY_PORT_PLL_BIOS_2 0x46014 |
#define | PCH_3DCGDIS0 0x46020 |
#define | MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) |
#define | SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) |
#define | PCH_3DCGDIS1 0x46024 |
#define | VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) |
#define | FDI_PLL_FREQ_CTL 0x46030 |
#define | FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) |
#define | FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 |
#define | FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff |
#define | _PIPEA_DATA_M1 0x60030 |
#define | TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ |
#define | TU_SIZE_MASK 0x7e000000 |
#define | DATA_LINK_M_N_MASK (0xffffff) |
#define | DATA_LINK_N_MAX (0x800000) |
#define | PIPE_DATA_M1_OFFSET 0 |
#define | _PIPEA_DATA_N1 0x60034 |
#define | PIPE_DATA_N1_OFFSET 0 |
#define | _PIPEA_DATA_M2 0x60038 |
#define | PIPE_DATA_M2_OFFSET 0 |
#define | _PIPEA_DATA_N2 0x6003c |
#define | PIPE_DATA_N2_OFFSET 0 |
#define | _PIPEA_LINK_M1 0x60040 |
#define | PIPE_LINK_M1_OFFSET 0 |
#define | _PIPEA_LINK_N1 0x60044 |
#define | PIPE_LINK_N1_OFFSET 0 |
#define | _PIPEA_LINK_M2 0x60048 |
#define | PIPE_LINK_M2_OFFSET 0 |
#define | _PIPEA_LINK_N2 0x6004c |
#define | PIPE_LINK_N2_OFFSET 0 |
#define | _PIPEB_DATA_M1 0x61030 |
#define | _PIPEB_DATA_N1 0x61034 |
#define | _PIPEB_DATA_M2 0x61038 |
#define | _PIPEB_DATA_N2 0x6103c |
#define | _PIPEB_LINK_M1 0x61040 |
#define | _PIPEB_LINK_N1 0x61044 |
#define | _PIPEB_LINK_M2 0x61048 |
#define | _PIPEB_LINK_N2 0x6104c |
#define | PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1) |
#define | PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1) |
#define | PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2) |
#define | PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2) |
#define | PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1) |
#define | PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1) |
#define | PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2) |
#define | PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2) |
#define | _PFA_CTL_1 0x68080 |
#define | _PFB_CTL_1 0x68880 |
#define | PF_ENABLE (1UL<<31) |
#define | PF_PIPE_SEL_MASK_IVB (3<<29) |
#define | PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) |
#define | PF_FILTER_MASK (3<<23) |
#define | PF_FILTER_PROGRAMMED (0<<23) |
#define | PF_FILTER_MED_3x3 (1<<23) |
#define | PF_FILTER_EDGE_ENHANCE (2<<23) |
#define | PF_FILTER_EDGE_SOFTEN (3<<23) |
#define | _PFA_WIN_SZ 0x68074 |
#define | _PFB_WIN_SZ 0x68874 |
#define | _PFA_WIN_POS 0x68070 |
#define | _PFB_WIN_POS 0x68870 |
#define | _PFA_VSCALE 0x68084 |
#define | _PFB_VSCALE 0x68884 |
#define | _PFA_HSCALE 0x68090 |
#define | _PFB_HSCALE 0x68890 |
#define | PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) |
#define | PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) |
#define | PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) |
#define | PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) |
#define | PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) |
#define | _LGC_PALETTE_A 0x4a000 |
#define | _LGC_PALETTE_B 0x4a800 |
#define | LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) |
#define | DE_MASTER_IRQ_CONTROL (1UL << 31) |
#define | DE_SPRITEB_FLIP_DONE (1 << 29) |
#define | DE_SPRITEA_FLIP_DONE (1 << 28) |
#define | DE_PLANEB_FLIP_DONE (1 << 27) |
#define | DE_PLANEA_FLIP_DONE (1 << 26) |
#define | DE_PCU_EVENT (1 << 25) |
#define | DE_GTT_FAULT (1 << 24) |
#define | DE_POISON (1 << 23) |
#define | DE_PERFORM_COUNTER (1 << 22) |
#define | DE_PCH_EVENT (1 << 21) |
#define | DE_AUX_CHANNEL_A (1 << 20) |
#define | DE_DP_A_HOTPLUG (1 << 19) |
#define | DE_GSE (1 << 18) |
#define | DE_PIPEB_VBLANK (1 << 15) |
#define | DE_PIPEB_EVEN_FIELD (1 << 14) |
#define | DE_PIPEB_ODD_FIELD (1 << 13) |
#define | DE_PIPEB_LINE_COMPARE (1 << 12) |
#define | DE_PIPEB_VSYNC (1 << 11) |
#define | DE_PIPEB_FIFO_UNDERRUN (1 << 8) |
#define | DE_PIPEA_VBLANK (1 << 7) |
#define | DE_PIPEA_EVEN_FIELD (1 << 6) |
#define | DE_PIPEA_ODD_FIELD (1 << 5) |
#define | DE_PIPEA_LINE_COMPARE (1 << 4) |
#define | DE_PIPEA_VSYNC (1 << 3) |
#define | DE_PIPEA_FIFO_UNDERRUN (1 << 0) |
#define | DE_ERR_DEBUG_IVB (1<<30) |
#define | DE_GSE_IVB (1<<29) |
#define | DE_PCH_EVENT_IVB (1<<28) |
#define | DE_DP_A_HOTPLUG_IVB (1<<27) |
#define | DE_AUX_CHANNEL_A_IVB (1<<26) |
#define | DE_SPRITEC_FLIP_DONE_IVB (1<<14) |
#define | DE_PLANEC_FLIP_DONE_IVB (1<<13) |
#define | DE_PIPEC_VBLANK_IVB (1<<10) |
#define | DE_SPRITEB_FLIP_DONE_IVB (1<<9) |
#define | DE_PLANEB_FLIP_DONE_IVB (1<<8) |
#define | DE_PIPEB_VBLANK_IVB (1<<5) |
#define | DE_SPRITEA_FLIP_DONE_IVB (1<<4) |
#define | DE_PLANEA_FLIP_DONE_IVB (1<<3) |
#define | DE_PIPEA_VBLANK_IVB (1<<0) |
#define | VLV_MASTER_IER 0x4400c /* Gunit master IER */ |
#define | MASTER_INTERRUPT_ENABLE (1UL<<31) |
#define | DEISR 0x44000 |
#define | DEIMR 0x44004 |
#define | DEIIR 0x44008 |
#define | DEIER 0x4400c |
#define | GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) |
#define | GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25) |
#define | GT_GEN6_BLT_USER_INTERRUPT (1 << 22) |
#define | GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15) |
#define | GT_GEN6_BSD_USER_INTERRUPT (1 << 12) |
#define | GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */ |
#define | GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5) |
#define | GT_PIPE_NOTIFY (1 << 4) |
#define | GT_RENDER_CS_ERROR_INTERRUPT (1 << 3) |
#define | GT_SYNC_STATUS (1 << 2) |
#define | GT_USER_INTERRUPT (1 << 0) |
#define | GTISR 0x44010 |
#define | GTIMR 0x44014 |
#define | GTIIR 0x44018 |
#define | GTIER 0x4401c |
#define | ILK_DISPLAY_CHICKEN2 0x42004 |
#define | ILK_ELPIN_409_SELECT (1 << 25) |
#define | ILK_DPARB_GATE (1<<22) |
#define | ILK_VSDPFD_FULL (1<<21) |
#define | ILK_DISPLAY_CHICKEN_FUSES 0x42014 |
#define | ILK_INTERNAL_GRAPHICS_DISABLE (1UL<<31) |
#define | ILK_INTERNAL_DISPLAY_DISABLE (1<<30) |
#define | ILK_DISPLAY_DEBUG_DISABLE (1<<29) |
#define | ILK_HDCP_DISABLE (1<<25) |
#define | ILK_eDP_A_DISABLE (1<<24) |
#define | ILK_DESKTOP (1<<23) |
#define | ILK_DSPCLK_GATE_D 0x42020 |
#define | ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) |
#define | ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) |
#define | ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) |
#define | ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) |
#define | ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) |
#define | IVB_CHICKEN3 0x4200c |
#define | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) |
#define | CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) |
#define | DISP_ARB_CTL 0x45000 |
#define | DISP_TILE_SURFACE_SWIZZLING (1<<13) |
#define | DISP_FBC_WM_DIS (1<<15) |
#define | GEN7_COMMON_SLICE_CHICKEN1 0x7010 |
#define | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) |
#define | GEN7_L3CNTLREG1 0xB01C |
#define | GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C |
#define | GEN7_L3AGDIS (1<<19) |
#define | GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 |
#define | GEN7_WA_L3_CHICKEN_MODE 0x20000000 |
#define | GEN7_L3SQCREG4 0xb034 |
#define | L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) |
#define | GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 |
#define | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) |
#define | HSW_FUSE_STRAP 0x42014 |
#define | HSW_CDCLK_LIMIT (1 << 24) |
#define | SDE_AUDIO_POWER_D (1 << 27) |
#define | SDE_AUDIO_POWER_C (1 << 26) |
#define | SDE_AUDIO_POWER_B (1 << 25) |
#define | SDE_AUDIO_POWER_SHIFT (25) |
#define | SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) |
#define | SDE_GMBUS (1 << 24) |
#define | SDE_AUDIO_HDCP_TRANSB (1 << 23) |
#define | SDE_AUDIO_HDCP_TRANSA (1 << 22) |
#define | SDE_AUDIO_HDCP_MASK (3 << 22) |
#define | SDE_AUDIO_TRANSB (1 << 21) |
#define | SDE_AUDIO_TRANSA (1 << 20) |
#define | SDE_AUDIO_TRANS_MASK (3 << 20) |
#define | SDE_POISON (1 << 19) |
#define | SDE_FDI_RXB (1 << 17) |
#define | SDE_FDI_RXA (1 << 16) |
#define | SDE_FDI_MASK (3 << 16) |
#define | SDE_AUXD (1 << 15) |
#define | SDE_AUXC (1 << 14) |
#define | SDE_AUXB (1 << 13) |
#define | SDE_AUX_MASK (7 << 13) |
#define | SDE_CRT_HOTPLUG (1 << 11) |
#define | SDE_PORTD_HOTPLUG (1 << 10) |
#define | SDE_PORTC_HOTPLUG (1 << 9) |
#define | SDE_PORTB_HOTPLUG (1 << 8) |
#define | SDE_SDVOB_HOTPLUG (1 << 6) |
#define | SDE_HOTPLUG_MASK (0xf << 8) |
#define | SDE_TRANSB_CRC_DONE (1 << 5) |
#define | SDE_TRANSB_CRC_ERR (1 << 4) |
#define | SDE_TRANSB_FIFO_UNDER (1 << 3) |
#define | SDE_TRANSA_CRC_DONE (1 << 2) |
#define | SDE_TRANSA_CRC_ERR (1 << 1) |
#define | SDE_TRANSA_FIFO_UNDER (1 << 0) |
#define | SDE_TRANS_MASK (0x3f) |
#define | SDE_AUDIO_POWER_D_CPT (1UL << 31) |
#define | SDE_AUDIO_POWER_C_CPT (1 << 30) |
#define | SDE_AUDIO_POWER_B_CPT (1 << 29) |
#define | SDE_AUDIO_POWER_SHIFT_CPT 29 |
#define | SDE_AUDIO_POWER_MASK_CPT (7 << 29) |
#define | SDE_AUXD_CPT (1 << 27) |
#define | SDE_AUXC_CPT (1 << 26) |
#define | SDE_AUXB_CPT (1 << 25) |
#define | SDE_AUX_MASK_CPT (7 << 25) |
#define | SDE_PORTD_HOTPLUG_CPT (1 << 23) |
#define | SDE_PORTC_HOTPLUG_CPT (1 << 22) |
#define | SDE_PORTB_HOTPLUG_CPT (1 << 21) |
#define | SDE_CRT_HOTPLUG_CPT (1 << 19) |
#define | SDE_HOTPLUG_MASK_CPT |
#define | SDE_GMBUS_CPT (1 << 17) |
#define | SDE_AUDIO_CP_REQ_C_CPT (1 << 10) |
#define | SDE_AUDIO_CP_CHG_C_CPT (1 << 9) |
#define | SDE_FDI_RXC_CPT (1 << 8) |
#define | SDE_AUDIO_CP_REQ_B_CPT (1 << 6) |
#define | SDE_AUDIO_CP_CHG_B_CPT (1 << 5) |
#define | SDE_FDI_RXB_CPT (1 << 4) |
#define | SDE_AUDIO_CP_REQ_A_CPT (1 << 2) |
#define | SDE_AUDIO_CP_CHG_A_CPT (1 << 1) |
#define | SDE_FDI_RXA_CPT (1 << 0) |
#define | SDE_AUDIO_CP_REQ_CPT |
#define | SDE_AUDIO_CP_CHG_CPT |
#define | SDE_FDI_MASK_CPT |
#define | SDEISR 0xc4000 |
#define | SDEIMR 0xc4004 |
#define | SDEIIR 0xc4008 |
#define | SDEIER 0xc400c |
#define | PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ |
#define | PORTD_HOTPLUG_ENABLE (1 << 20) |
#define | PORTD_PULSE_DURATION_2ms (0) |
#define | PORTD_PULSE_DURATION_4_5ms (1 << 18) |
#define | PORTD_PULSE_DURATION_6ms (2 << 18) |
#define | PORTD_PULSE_DURATION_100ms (3 << 18) |
#define | PORTD_PULSE_DURATION_MASK (3 << 18) |
#define | PORTD_HOTPLUG_NO_DETECT (0) |
#define | PORTD_HOTPLUG_SHORT_DETECT (1 << 16) |
#define | PORTD_HOTPLUG_LONG_DETECT (1 << 17) |
#define | PORTC_HOTPLUG_ENABLE (1 << 12) |
#define | PORTC_PULSE_DURATION_2ms (0) |
#define | PORTC_PULSE_DURATION_4_5ms (1 << 10) |
#define | PORTC_PULSE_DURATION_6ms (2 << 10) |
#define | PORTC_PULSE_DURATION_100ms (3 << 10) |
#define | PORTC_PULSE_DURATION_MASK (3 << 10) |
#define | PORTC_HOTPLUG_NO_DETECT (0) |
#define | PORTC_HOTPLUG_SHORT_DETECT (1 << 8) |
#define | PORTC_HOTPLUG_LONG_DETECT (1 << 9) |
#define | PORTB_HOTPLUG_ENABLE (1 << 4) |
#define | PORTB_PULSE_DURATION_2ms (0) |
#define | PORTB_PULSE_DURATION_4_5ms (1 << 2) |
#define | PORTB_PULSE_DURATION_6ms (2 << 2) |
#define | PORTB_PULSE_DURATION_100ms (3 << 2) |
#define | PORTB_PULSE_DURATION_MASK (3 << 2) |
#define | PORTB_HOTPLUG_NO_DETECT (0) |
#define | PORTB_HOTPLUG_SHORT_DETECT (1 << 0) |
#define | PORTB_HOTPLUG_LONG_DETECT (1 << 1) |
#define | PCH_GPIOA 0xc5010 |
#define | PCH_GPIOB 0xc5014 |
#define | PCH_GPIOC 0xc5018 |
#define | PCH_GPIOD 0xc501c |
#define | PCH_GPIOE 0xc5020 |
#define | PCH_GPIOF 0xc5024 |
#define | PCH_GMBUS0 0xc5100 |
#define | PCH_GMBUS1 0xc5104 |
#define | PCH_GMBUS2 0xc5108 |
#define | PCH_GMBUS3 0xc510c |
#define | PCH_GMBUS4 0xc5110 |
#define | PCH_GMBUS5 0xc5120 |
#define | _PCH_DPLL_A 0xc6014 |
#define | _PCH_DPLL_B 0xc6018 |
#define | _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) |
#define | _PCH_FPA0 0xc6040 |
#define | FP_CB_TUNE (0x3<<22) |
#define | _PCH_FPA1 0xc6044 |
#define | _PCH_FPB0 0xc6048 |
#define | _PCH_FPB1 0xc604c |
#define | _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) |
#define | _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) |
#define | PCH_DPLL_TEST 0xc606c |
#define | PCH_DREF_CONTROL 0xC6200 |
#define | DREF_CONTROL_MASK 0x7fc3 |
#define | DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) |
#define | DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) |
#define | DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) |
#define | DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) |
#define | DREF_SSC_SOURCE_DISABLE (0<<11) |
#define | DREF_SSC_SOURCE_ENABLE (2<<11) |
#define | DREF_SSC_SOURCE_MASK (3<<11) |
#define | DREF_NONSPREAD_SOURCE_DISABLE (0<<9) |
#define | DREF_NONSPREAD_CK505_ENABLE (1<<9) |
#define | DREF_NONSPREAD_SOURCE_ENABLE (2<<9) |
#define | DREF_NONSPREAD_SOURCE_MASK (3<<9) |
#define | DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) |
#define | DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) |
#define | DREF_SUPERSPREAD_SOURCE_MASK (3<<7) |
#define | DREF_SSC4_DOWNSPREAD (0<<6) |
#define | DREF_SSC4_CENTERSPREAD (1<<6) |
#define | DREF_SSC1_DISABLE (0<<1) |
#define | DREF_SSC1_ENABLE (1<<1) |
#define | DREF_SSC4_DISABLE (0) |
#define | DREF_SSC4_ENABLE (1) |
#define | PCH_RAWCLK_FREQ 0xc6204 |
#define | FDL_TP1_TIMER_SHIFT 12 |
#define | FDL_TP1_TIMER_MASK (3<<12) |
#define | FDL_TP2_TIMER_SHIFT 10 |
#define | FDL_TP2_TIMER_MASK (3<<10) |
#define | RAWCLK_FREQ_MASK 0x3ff |
#define | PCH_DPLL_TMR_CFG 0xc6208 |
#define | PCH_SSC4_PARMS 0xc6210 |
#define | PCH_SSC4_AUX_PARMS 0xc6214 |
#define | PCH_DPLL_SEL 0xc7000 |
#define | TRANSA_DPLL_ENABLE (1<<3) |
#define | TRANSA_DPLLB_SEL (1<<0) |
#define | TRANSA_DPLLA_SEL 0 |
#define | TRANSB_DPLL_ENABLE (1<<7) |
#define | TRANSB_DPLLB_SEL (1<<4) |
#define | TRANSB_DPLLA_SEL (0) |
#define | TRANSC_DPLL_ENABLE (1<<11) |
#define | TRANSC_DPLLB_SEL (1<<8) |
#define | TRANSC_DPLLA_SEL (0) |
#define | _TRANS_HTOTAL_A 0xe0000 |
#define | TRANS_HTOTAL_SHIFT 16 |
#define | TRANS_HACTIVE_SHIFT 0 |
#define | _TRANS_HBLANK_A 0xe0004 |
#define | TRANS_HBLANK_END_SHIFT 16 |
#define | TRANS_HBLANK_START_SHIFT 0 |
#define | _TRANS_HSYNC_A 0xe0008 |
#define | TRANS_HSYNC_END_SHIFT 16 |
#define | TRANS_HSYNC_START_SHIFT 0 |
#define | _TRANS_VTOTAL_A 0xe000c |
#define | TRANS_VTOTAL_SHIFT 16 |
#define | TRANS_VACTIVE_SHIFT 0 |
#define | _TRANS_VBLANK_A 0xe0010 |
#define | TRANS_VBLANK_END_SHIFT 16 |
#define | TRANS_VBLANK_START_SHIFT 0 |
#define | _TRANS_VSYNC_A 0xe0014 |
#define | TRANS_VSYNC_END_SHIFT 16 |
#define | TRANS_VSYNC_START_SHIFT 0 |
#define | _TRANS_VSYNCSHIFT_A 0xe0028 |
#define | _TRANSA_DATA_M1 0xe0030 |
#define | _TRANSA_DATA_N1 0xe0034 |
#define | _TRANSA_DATA_M2 0xe0038 |
#define | _TRANSA_DATA_N2 0xe003c |
#define | _TRANSA_DP_LINK_M1 0xe0040 |
#define | _TRANSA_DP_LINK_N1 0xe0044 |
#define | _TRANSA_DP_LINK_M2 0xe0048 |
#define | _TRANSA_DP_LINK_N2 0xe004c |
#define | _VIDEO_DIP_CTL_A 0xe0200 |
#define | _VIDEO_DIP_DATA_A 0xe0208 |
#define | _VIDEO_DIP_GCP_A 0xe0210 |
#define | _VIDEO_DIP_CTL_B 0xe1200 |
#define | _VIDEO_DIP_DATA_B 0xe1208 |
#define | _VIDEO_DIP_GCP_B 0xe1210 |
#define | TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) |
#define | TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) |
#define | TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) |
#define | VLV_VIDEO_DIP_CTL_A 0x60200 |
#define | VLV_VIDEO_DIP_DATA_A 0x60208 |
#define | VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210 |
#define | VLV_VIDEO_DIP_CTL_B 0x61170 |
#define | VLV_VIDEO_DIP_DATA_B 0x61174 |
#define | VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178 |
#define | VLV_TVIDEO_DIP_CTL(pipe) _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B) |
#define | VLV_TVIDEO_DIP_DATA(pipe) _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B) |
#define | VLV_TVIDEO_DIP_GCP(pipe) _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B) |
#define | HSW_VIDEO_DIP_CTL_A 0x60200 |
#define | HSW_VIDEO_DIP_AVI_DATA_A 0x60220 |
#define | HSW_VIDEO_DIP_VS_DATA_A 0x60260 |
#define | HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 |
#define | HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 |
#define | HSW_VIDEO_DIP_VSC_DATA_A 0x60320 |
#define | HSW_VIDEO_DIP_AVI_ECC_A 0x60240 |
#define | HSW_VIDEO_DIP_VS_ECC_A 0x60280 |
#define | HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 |
#define | HSW_VIDEO_DIP_GMP_ECC_A 0x60300 |
#define | HSW_VIDEO_DIP_VSC_ECC_A 0x60344 |
#define | HSW_VIDEO_DIP_GCP_A 0x60210 |
#define | HSW_VIDEO_DIP_CTL_B 0x61200 |
#define | HSW_VIDEO_DIP_AVI_DATA_B 0x61220 |
#define | HSW_VIDEO_DIP_VS_DATA_B 0x61260 |
#define | HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 |
#define | HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 |
#define | HSW_VIDEO_DIP_VSC_DATA_B 0x61320 |
#define | HSW_VIDEO_DIP_BVI_ECC_B 0x61240 |
#define | HSW_VIDEO_DIP_VS_ECC_B 0x61280 |
#define | HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 |
#define | HSW_VIDEO_DIP_GMP_ECC_B 0x61300 |
#define | HSW_VIDEO_DIP_VSC_ECC_B 0x61344 |
#define | HSW_VIDEO_DIP_GCP_B 0x61210 |
#define | HSW_TVIDEO_DIP_CTL(pipe) _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B) |
#define | HSW_TVIDEO_DIP_AVI_DATA(pipe) _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B) |
#define | HSW_TVIDEO_DIP_SPD_DATA(pipe) _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B) |
#define | HSW_TVIDEO_DIP_GCP(pipe) _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B) |
#define | _TRANS_HTOTAL_B 0xe1000 |
#define | _TRANS_HBLANK_B 0xe1004 |
#define | _TRANS_HSYNC_B 0xe1008 |
#define | _TRANS_VTOTAL_B 0xe100c |
#define | _TRANS_VBLANK_B 0xe1010 |
#define | _TRANS_VSYNC_B 0xe1014 |
#define | _TRANS_VSYNCSHIFT_B 0xe1028 |
#define | TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) |
#define | TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B) |
#define | TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B) |
#define | TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B) |
#define | TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) |
#define | TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) |
#define | TRANS_VSYNCSHIFT(pipe) |
#define | _TRANSB_DATA_M1 0xe1030 |
#define | _TRANSB_DATA_N1 0xe1034 |
#define | _TRANSB_DATA_M2 0xe1038 |
#define | _TRANSB_DATA_N2 0xe103c |
#define | _TRANSB_DP_LINK_M1 0xe1040 |
#define | _TRANSB_DP_LINK_N1 0xe1044 |
#define | _TRANSB_DP_LINK_M2 0xe1048 |
#define | _TRANSB_DP_LINK_N2 0xe104c |
#define | TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1) |
#define | TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1) |
#define | TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2) |
#define | TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2) |
#define | TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1) |
#define | TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1) |
#define | TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2) |
#define | TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2) |
#define | _TRANSACONF 0xf0008 |
#define | _TRANSBCONF 0xf1008 |
#define | TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF) |
#define | _PCH_TRANSACONF 0xf0008 |
#define | _PCH_TRANSBCONF 0xf1008 |
#define | PCH_TRANSCONF(plane) _PIPE(plane, _PCH_TRANSACONF, _PCH_TRANSBCONF) |
#define | TRANS_DISABLE (0UL<<31) |
#define | TRANS_ENABLE (1UL<<31) |
#define | TRANS_STATE_MASK (1<<30) |
#define | TRANS_STATE_DISABLE (0<<30) |
#define | TRANS_STATE_ENABLE (1<<30) |
#define | TRANS_FSYNC_DELAY_HB1 (0<<27) |
#define | TRANS_FSYNC_DELAY_HB2 (1<<27) |
#define | TRANS_FSYNC_DELAY_HB3 (2<<27) |
#define | TRANS_FSYNC_DELAY_HB4 (3<<27) |
#define | TRANS_DP_AUDIO_ONLY (1<<26) |
#define | TRANS_DP_VIDEO_AUDIO (0<<26) |
#define | TRANS_INTERLACE_MASK (7<<21) |
#define | TRANS_PROGRESSIVE (0<<21) |
#define | TRANS_INTERLACED (3<<21) |
#define | TRANS_LEGACY_INTERLACED_ILK (2<<21) |
#define | TRANS_8BPC (0<<5) |
#define | TRANS_10BPC (1<<5) |
#define | TRANS_6BPC (2<<5) |
#define | TRANS_12BPC (3<<5) |
#define | _TRANSA_CHICKEN1 0xf0060 |
#define | _TRANSB_CHICKEN1 0xf1060 |
#define | TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) |
#define | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) |
#define | _TRANSA_CHICKEN2 0xf0064 |
#define | _TRANSB_CHICKEN2 0xf1064 |
#define | TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) |
#define | TRANS_CHICKEN2_TIMING_OVERRIDE (1UL<<31) |
#define | SOUTH_CHICKEN1 0xc2000 |
#define | FDIA_PHASE_SYNC_SHIFT_OVR 19 |
#define | FDIA_PHASE_SYNC_SHIFT_EN 18 |
#define | FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) |
#define | FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) |
#define | FDI_BC_BIFURCATION_SELECT (1 << 12) |
#define | SOUTH_CHICKEN2 0xc2004 |
#define | FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) |
#define | FDI_MPHY_IOSFSB_RESET_CTL (1<<12) |
#define | LPT_PWM_GRANULARITY (1<<5) |
#define | DPLS_EDP_PPS_FIX_DIS (1<<0) |
#define | _FDI_RXA_CHICKEN 0xc200c |
#define | _FDI_RXB_CHICKEN 0xc2010 |
#define | FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) |
#define | FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) |
#define | FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) |
#define | SOUTH_DSPCLK_GATE_D 0xc2020 |
#define | PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) |
#define | PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) |
#define | _FDI_TXA_CTL 0x60100 |
#define | _FDI_TXB_CTL 0x61100 |
#define | FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) |
#define | FDI_TX_DISABLE (0UL<<31) |
#define | FDI_TX_ENABLE (1UL<<31) |
#define | FDI_LINK_TRAIN_PATTERN_1 (0<<28) |
#define | FDI_LINK_TRAIN_PATTERN_2 (1<<28) |
#define | FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) |
#define | FDI_LINK_TRAIN_NONE (3<<28) |
#define | FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) |
#define | FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) |
#define | FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) |
#define | FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) |
#define | FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) |
#define | FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) |
#define | FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) |
#define | FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) |
#define | FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) |
#define | FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) |
#define | FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) |
#define | FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) |
#define | FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) |
#define | FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) |
#define | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) |
#define | FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) |
#define | FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) |
#define | FDI_DP_PORT_WIDTH_X1 (0<<19) |
#define | FDI_DP_PORT_WIDTH_X2 (1<<19) |
#define | FDI_DP_PORT_WIDTH_X3 (2<<19) |
#define | FDI_DP_PORT_WIDTH_X4 (3<<19) |
#define | FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) |
#define | FDI_TX_PLL_ENABLE (1<<14) |
#define | FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) |
#define | FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) |
#define | FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) |
#define | FDI_LINK_TRAIN_NONE_IVB (3<<8) |
#define | FDI_COMPOSITE_SYNC (1<<11) |
#define | FDI_LINK_TRAIN_AUTO (1<<10) |
#define | FDI_SCRAMBLING_ENABLE (0<<7) |
#define | FDI_SCRAMBLING_DISABLE (1<<7) |
#define | _FDI_RXA_CTL 0xf000c |
#define | _FDI_RXB_CTL 0xf100c |
#define | FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) |
#define | FDI_RX_ENABLE (1UL<<31) |
#define | FDI_FS_ERRC_ENABLE (1<<27) |
#define | FDI_FE_ERRC_ENABLE (1<<26) |
#define | FDI_DP_PORT_WIDTH_X8 (7<<19) |
#define | FDI_RX_POLARITY_REVERSED_LPT (1<<16) |
#define | FDI_8BPC (0<<16) |
#define | FDI_10BPC (1<<16) |
#define | FDI_6BPC (2<<16) |
#define | FDI_12BPC (3<<16) |
#define | FDI_LINK_REVERSE_OVERWRITE (1<<15) |
#define | FDI_DMI_LINK_REVERSE_MASK (1<<14) |
#define | FDI_RX_PLL_ENABLE (1<<13) |
#define | FDI_FS_ERR_CORRECT_ENABLE (1<<11) |
#define | FDI_FE_ERR_CORRECT_ENABLE (1<<10) |
#define | FDI_FS_ERR_REPORT_ENABLE (1<<9) |
#define | FDI_FE_ERR_REPORT_ENABLE (1<<8) |
#define | FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) |
#define | FDI_PCDCLK (1<<4) |
#define | FDI_AUTO_TRAINING (1<<10) |
#define | FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) |
#define | FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) |
#define | FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) |
#define | FDI_LINK_TRAIN_NORMAL_CPT (3<<8) |
#define | FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) |
#define | FDI_PORT_WIDTH_2X_LPT (1<<19) |
#define | FDI_PORT_WIDTH_1X_LPT (0<<19) |
#define | _FDI_RXA_MISC 0xf0010 |
#define | _FDI_RXB_MISC 0xf1010 |
#define | FDI_RX_PWRDN_LANE1_MASK (3<<26) |
#define | FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) |
#define | FDI_RX_PWRDN_LANE0_MASK (3<<24) |
#define | FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) |
#define | FDI_RX_TP1_TO_TP2_48 (2<<20) |
#define | FDI_RX_TP1_TO_TP2_64 (3<<20) |
#define | FDI_RX_FDI_DELAY_90 (0x90<<0) |
#define | FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) |
#define | _FDI_RXA_TUSIZE1 0xf0030 |
#define | _FDI_RXA_TUSIZE2 0xf0038 |
#define | _FDI_RXB_TUSIZE1 0xf1030 |
#define | _FDI_RXB_TUSIZE2 0xf1038 |
#define | FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) |
#define | FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) |
#define | FDI_RX_INTER_LANE_ALIGN (1<<10) |
#define | FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ |
#define | FDI_RX_BIT_LOCK (1<<8) /* train 1 */ |
#define | FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) |
#define | FDI_RX_FS_CODE_ERR (1<<6) |
#define | FDI_RX_FE_CODE_ERR (1<<5) |
#define | FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) |
#define | FDI_RX_HDCP_LINK_FAIL (1<<3) |
#define | FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) |
#define | FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) |
#define | FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) |
#define | _FDI_RXA_IIR 0xf0014 |
#define | _FDI_RXA_IMR 0xf0018 |
#define | _FDI_RXB_IIR 0xf1014 |
#define | _FDI_RXB_IMR 0xf1018 |
#define | FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) |
#define | FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) |
#define | FDI_PLL_CTL_1 0xfe000 |
#define | FDI_PLL_CTL_2 0xfe004 |
#define | HDMIB 0xe1140 |
#define | PORT_ENABLE (1UL << 31) |
#define | TRANSCODER(pipe) ((pipe) << 30) |
#define | TRANSCODER_CPT(pipe) ((pipe) << 29) |
#define | TRANSCODER_MASK (1 << 30) |
#define | TRANSCODER_MASK_CPT (3 << 29) |
#define | COLOR_FORMAT_8bpc (0) |
#define | COLOR_FORMAT_12bpc (3 << 26) |
#define | SDVOB_HOTPLUG_ENABLE (1 << 23) |
#define | SDVO_ENCODING (0) |
#define | TMDS_ENCODING (2 << 10) |
#define | NULL_PACKET_VSYNC_ENABLE (1 << 9) |
#define | HDMI_MODE_SELECT (1 << 9) |
#define | DVI_MODE_SELECT (0) |
#define | SDVOB_BORDER_ENABLE (1 << 7) |
#define | AUDIO_ENABLE (1 << 6) |
#define | VSYNC_ACTIVE_HIGH (1 << 4) |
#define | HSYNC_ACTIVE_HIGH (1 << 3) |
#define | PORT_DETECTED (1 << 2) |
#define | PCH_SDVOB HDMIB |
#define | HDMIC 0xe1150 |
#define | HDMID 0xe1160 |
#define | PCH_LVDS 0xe1180 |
#define | LVDS_DETECTED (1 << 1) |
#define | LVDS_BORDER_ENABLE (1 << 15) |
#define | LVDS_PORT_ENABLE (1UL << 31) |
#define | LVDS_CLOCK_A_POWERUP_ALL (3 << 8) |
#define | LVDS_CLOCK_B_POWERUP_ALL (3 << 4) |
#define | LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) |
#define | PIPEA_PP_STATUS 0x61200 |
#define | PIPEA_PP_CONTROL 0x61204 |
#define | PIPEA_PP_ON_DELAYS 0x61208 |
#define | PIPEA_PP_OFF_DELAYS 0x6120c |
#define | PIPEA_PP_DIVISOR 0x61210 |
#define | PIPEB_PP_STATUS 0x61300 |
#define | PIPEB_PP_CONTROL 0x61304 |
#define | PIPEB_PP_ON_DELAYS 0x61308 |
#define | PIPEB_PP_OFF_DELAYS 0x6130c |
#define | PIPEB_PP_DIVISOR 0x61310 |
#define | PCH_PP_STATUS 0xc7200 |
#define | PCH_PP_CONTROL 0xc7204 |
#define | PANEL_UNLOCK_REGS (0xabcd << 16) |
#define | PANEL_UNLOCK_MASK (0xffff << 16) |
#define | EDP_FORCE_VDD (1 << 3) |
#define | EDP_BLC_ENABLE (1 << 2) |
#define | PANEL_POWER_RESET (1 << 1) |
#define | PANEL_POWER_OFF (0 << 0) |
#define | PANEL_POWER_ON (1 << 0) |
#define | PCH_PP_ON_DELAYS 0xc7208 |
#define | PANEL_PORT_SELECT_MASK (3 << 30) |
#define | PANEL_PORT_SELECT_LVDS (0 << 30) |
#define | PANEL_PORT_SELECT_DPA (1 << 30) |
#define | EDP_PANEL (1 << 30) |
#define | PANEL_PORT_SELECT_DPC (2 << 30) |
#define | PANEL_PORT_SELECT_DPD (3 << 30) |
#define | PANEL_POWER_UP_DELAY_MASK (0x1fff0000) |
#define | PANEL_POWER_UP_DELAY_SHIFT 16 |
#define | PANEL_LIGHT_ON_DELAY_MASK (0x1fff) |
#define | PANEL_LIGHT_ON_DELAY_SHIFT 0 |
#define | PCH_PP_OFF_DELAYS 0xc720c |
#define | PANEL_POWER_PORT_SELECT_MASK (0x3 << 30) |
#define | PANEL_POWER_PORT_LVDS (0 << 30) |
#define | PANEL_POWER_PORT_DP_A (1 << 30) |
#define | PANEL_POWER_PORT_DP_C (2 << 30) |
#define | PANEL_POWER_PORT_DP_D (3 << 30) |
#define | PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) |
#define | PANEL_POWER_DOWN_DELAY_SHIFT 16 |
#define | PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) |
#define | PANEL_LIGHT_OFF_DELAY_SHIFT 0 |
#define | PCH_PP_DIVISOR 0xc7210 |
#define | PP_REFERENCE_DIVIDER_MASK (0xffffff00) |
#define | PP_REFERENCE_DIVIDER_SHIFT 8 |
#define | PANEL_POWER_CYCLE_DELAY_MASK (0x1f) |
#define | PANEL_POWER_CYCLE_DELAY_SHIFT 0 |
#define | PCH_DP_B 0xe4100 |
#define | PCH_DPB_AUX_CH_CTL 0xe4110 |
#define | PCH_DPB_AUX_CH_DATA1 0xe4114 |
#define | PCH_DPB_AUX_CH_DATA2 0xe4118 |
#define | PCH_DPB_AUX_CH_DATA3 0xe411c |
#define | PCH_DPB_AUX_CH_DATA4 0xe4120 |
#define | PCH_DPB_AUX_CH_DATA5 0xe4124 |
#define | PCH_DP_C 0xe4200 |
#define | PCH_DPC_AUX_CH_CTL 0xe4210 |
#define | PCH_DPC_AUX_CH_DATA1 0xe4214 |
#define | PCH_DPC_AUX_CH_DATA2 0xe4218 |
#define | PCH_DPC_AUX_CH_DATA3 0xe421c |
#define | PCH_DPC_AUX_CH_DATA4 0xe4220 |
#define | PCH_DPC_AUX_CH_DATA5 0xe4224 |
#define | PCH_DP_D 0xe4300 |
#define | PCH_DPD_AUX_CH_CTL 0xe4310 |
#define | PCH_DPD_AUX_CH_DATA1 0xe4314 |
#define | PCH_DPD_AUX_CH_DATA2 0xe4318 |
#define | PCH_DPD_AUX_CH_DATA3 0xe431c |
#define | PCH_DPD_AUX_CH_DATA4 0xe4320 |
#define | PCH_DPD_AUX_CH_DATA5 0xe4324 |
#define | PORT_TRANS_A_SEL_CPT 0 |
#define | PORT_TRANS_B_SEL_CPT (1<<29) |
#define | PORT_TRANS_C_SEL_CPT (2<<29) |
#define | PORT_TRANS_SEL_MASK (3<<29) |
#define | PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) |
#define | PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) |
#define | PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) |
#define | TRANS_DP_CTL_A 0xe0300 |
#define | TRANS_DP_CTL_B 0xe1300 |
#define | TRANS_DP_CTL_C 0xe2300 |
#define | TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B) |
#define | TRANS_DP_OUTPUT_ENABLE (1UL<<31) |
#define | TRANS_DP_PORT_SEL_B (0<<29) |
#define | TRANS_DP_PORT_SEL_C (1<<29) |
#define | TRANS_DP_PORT_SEL_D (2<<29) |
#define | TRANS_DP_PORT_SEL_NONE (3<<29) |
#define | TRANS_DP_PORT_SEL_MASK (3<<29) |
#define | TRANS_DP_AUDIO_ONLY (1<<26) |
#define | TRANS_DP_ENH_FRAMING (1<<18) |
#define | TRANS_DP_8BPC (0<<9) |
#define | TRANS_DP_10BPC (1<<9) |
#define | TRANS_DP_6BPC (2<<9) |
#define | TRANS_DP_12BPC (3<<9) |
#define | TRANS_DP_BPC_MASK (3<<9) |
#define | TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) |
#define | TRANS_DP_VSYNC_ACTIVE_LOW 0 |
#define | TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) |
#define | TRANS_DP_HSYNC_ACTIVE_LOW 0 |
#define | TRANS_DP_SYNC_MASK (3<<3) |
#define | EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) |
#define | EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) |
#define | EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) |
#define | EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) |
#define | EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) |
#define | EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) |
#define | EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) |
#define | EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) |
#define | EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) |
#define | EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) |
#define | EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) |
#define | EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) |
#define | EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) |
#define | EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) |
#define | EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) |
#define | EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) |
#define | EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22) |
#define | EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) |
#define | EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) |
#define | EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) |
#define | EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) |
#define | EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) |
#define | EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) |
#define | FORCEWAKE 0xA18C |
#define | FORCEWAKE_VLV 0x1300b0 |
#define | FORCEWAKE_ACK_VLV 0x1300b4 |
#define | FORCEWAKE_ACK_HSW 0x130044 |
#define | FORCEWAKE_ACK 0x130090 |
#define | FORCEWAKE_MT 0xa188 /* multi-threaded */ |
#define | FORCEWAKE_KERNEL 0x1 |
#define | FORCEWAKE_USER 0x2 |
#define | FORCEWAKE_MT_ACK 0x130040 |
#define | ECOBUS 0xa180 |
#define | FORCEWAKE_MT_ENABLE (1<<5) |
#define | GTFIFODBG 0x120000 |
#define | GT_FIFO_CPU_ERROR_MASK 7 |
#define | GT_FIFO_OVFERR (1<<2) |
#define | GT_FIFO_IAWRERR (1<<1) |
#define | GT_FIFO_IARDERR (1<<0) |
#define | GT_FIFO_FREE_ENTRIES 0x120008 |
#define | GT_FIFO_NUM_RESERVED_ENTRIES 20 |
#define | GEN6_UCGCTL1 0x9400 |
#define | GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) |
#define | GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) |
#define | GEN6_UCGCTL2 0x9404 |
#define | GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) |
#define | GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) |
#define | GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) |
#define | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) |
#define | GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) |
#define | GEN7_UCGCTL4 0x940c |
#define | GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) |
#define | GEN6_RPNSWREQ 0xA008 |
#define | GEN6_TURBO_DISABLE (1UL<<31) |
#define | GEN6_FREQUENCY(x) ((x)<<25) |
#define | GEN6_OFFSET(x) ((x)<<19) |
#define | GEN6_AGGRESSIVE_TURBO (0<<15) |
#define | GEN6_RC_VIDEO_FREQ 0xA00C |
#define | GEN6_RC_CONTROL 0xA090 |
#define | GEN6_RC_CTL_RC6pp_ENABLE (1<<16) |
#define | GEN6_RC_CTL_RC6p_ENABLE (1<<17) |
#define | GEN6_RC_CTL_RC6_ENABLE (1<<18) |
#define | GEN6_RC_CTL_RC1e_ENABLE (1<<20) |
#define | GEN6_RC_CTL_RC7_ENABLE (1<<22) |
#define | GEN6_RC_CTL_EI_MODE(x) ((x)<<27) |
#define | GEN6_RC_CTL_HW_ENABLE (1UL<<31) |
#define | GEN6_RP_DOWN_TIMEOUT 0xA010 |
#define | GEN6_RP_INTERRUPT_LIMITS 0xA014 |
#define | GEN6_RPSTAT1 0xA01C |
#define | GEN6_CAGF_SHIFT 8 |
#define | GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) |
#define | GEN6_RP_CONTROL 0xA024 |
#define | GEN6_RP_MEDIA_TURBO (1<<11) |
#define | GEN6_RP_MEDIA_MODE_MASK (3<<9) |
#define | GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) |
#define | GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) |
#define | GEN6_RP_MEDIA_HW_MODE (1<<9) |
#define | GEN6_RP_MEDIA_SW_MODE (0<<9) |
#define | GEN6_RP_MEDIA_IS_GFX (1<<8) |
#define | GEN6_RP_ENABLE (1<<7) |
#define | GEN6_RP_UP_IDLE_MIN (0x1<<3) |
#define | GEN6_RP_UP_BUSY_AVG (0x2<<3) |
#define | GEN6_RP_UP_BUSY_CONT (0x4<<3) |
#define | GEN7_RP_DOWN_IDLE_AVG (0x2<<0) |
#define | GEN6_RP_DOWN_IDLE_CONT (0x1<<0) |
#define | GEN6_RP_UP_THRESHOLD 0xA02C |
#define | GEN6_RP_DOWN_THRESHOLD 0xA030 |
#define | GEN6_RP_CUR_UP_EI 0xA050 |
#define | GEN6_CURICONT_MASK 0xffffff |
#define | GEN6_RP_CUR_UP 0xA054 |
#define | GEN6_CURBSYTAVG_MASK 0xffffff |
#define | GEN6_RP_PREV_UP 0xA058 |
#define | GEN6_RP_CUR_DOWN_EI 0xA05C |
#define | GEN6_CURIAVG_MASK 0xffffff |
#define | GEN6_RP_CUR_DOWN 0xA060 |
#define | GEN6_RP_PREV_DOWN 0xA064 |
#define | GEN6_RP_UP_EI 0xA068 |
#define | GEN6_RP_DOWN_EI 0xA06C |
#define | GEN6_RP_IDLE_HYSTERSIS 0xA070 |
#define | GEN6_RC_STATE 0xA094 |
#define | GEN6_RC1_WAKE_RATE_LIMIT 0xA098 |
#define | GEN6_RC6_WAKE_RATE_LIMIT 0xA09C |
#define | GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 |
#define | GEN6_RC_EVALUATION_INTERVAL 0xA0A8 |
#define | GEN6_RC_IDLE_HYSTERSIS 0xA0AC |
#define | GEN6_RC_SLEEP 0xA0B0 |
#define | GEN6_RC1e_THRESHOLD 0xA0B4 |
#define | GEN6_RC6_THRESHOLD 0xA0B8 |
#define | GEN6_RC6p_THRESHOLD 0xA0BC |
#define | GEN6_RC6pp_THRESHOLD 0xA0C0 |
#define | GEN6_PMINTRMSK 0xA168 |
#define | GEN6_PMISR 0x44020 |
#define | GEN6_PMIMR 0x44024 /* rps_lock */ |
#define | GEN6_PMIIR 0x44028 |
#define | GEN6_PMIER 0x4402C |
#define | GEN6_PM_MBOX_EVENT (1<<25) |
#define | GEN6_PM_THERMAL_EVENT (1<<24) |
#define | GEN6_PM_RP_DOWN_TIMEOUT (1<<6) |
#define | GEN6_PM_RP_UP_THRESHOLD (1<<5) |
#define | GEN6_PM_RP_DOWN_THRESHOLD (1<<4) |
#define | GEN6_PM_RP_UP_EI_EXPIRED (1<<2) |
#define | GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) |
#define | GEN6_PM_DEFERRED_EVENTS |
#define | GEN6_GT_GFX_RC6_LOCKED 0x138104 |
#define | GEN6_GT_GFX_RC6 0x138108 |
#define | GEN6_GT_GFX_RC6p 0x13810C |
#define | GEN6_GT_GFX_RC6pp 0x138110 |
#define | GEN6_PCODE_MAILBOX 0x138124 |
#define | GEN6_PCODE_READY (1UL<<31) |
#define | GEN6_READ_OC_PARAMS 0xc |
#define | GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
#define | GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 |
#define | GEN6_PCODE_WRITE_RC6VIDS 0x4 |
#define | GEN6_PCODE_READ_RC6VIDS 0x5 |
#define | GEN6_ENCODE_RC6_VID(mv) (((mv) / 5) - 245) < 0 ?: 0 |
#define | GEN6_DECODE_RC6_VID(vids) (((vids) * 5) > 0 ? ((vids) * 5) + 245 : 0) |
#define | GEN6_PCODE_DATA 0x138128 |
#define | GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
#define | GEN6_GT_CORE_STATUS 0x138060 |
#define | GEN6_CORE_CPD_STATE_MASK (7<<4) |
#define | GEN6_RCn_MASK 7 |
#define | GEN6_RC0 0 |
#define | GEN6_RC3 2 |
#define | GEN6_RC6 3 |
#define | GEN6_RC7 4 |
#define | GEN7_MISCCPCTL (0x9424) |
#define | GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) |
#define | GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ |
#define | GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) |
#define | GEN7_PARITY_ERROR_VALID (1<<13) |
#define | GEN7_L3CDERRST1_BANK_MASK (3<<11) |
#define | GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) |
#define | GEN7_PARITY_ERROR_ROW(reg) ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) |
#define | GEN7_PARITY_ERROR_BANK(reg) ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) |
#define | GEN7_PARITY_ERROR_SUBBANK(reg) ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) |
#define | GEN7_L3CDERRST1_ENABLE (1<<7) |
#define | GEN7_L3LOG_BASE 0xB070 |
#define | GEN7_L3LOG_SIZE 0x80 |
#define | GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ |
#define | GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 |
#define | GEN7_MAX_PS_THREAD_DEP (8<<12) |
#define | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) |
#define | GEN7_ROW_CHICKEN2 0xe4f4 |
#define | GEN7_ROW_CHICKEN2_GT2 0xf4f4 |
#define | DOP_CLOCK_GATING_DISABLE (1<<0) |
#define | G4X_AUD_VID_DID 0x62020 |
#define | INTEL_AUDIO_DEVCL 0x808629FB |
#define | INTEL_AUDIO_DEVBLC 0x80862801 |
#define | INTEL_AUDIO_DEVCTG 0x80862802 |
#define | G4X_AUD_CNTL_ST 0x620B4 |
#define | G4X_ELDV_DEVCL_DEVBLC (1 << 13) |
#define | G4X_ELDV_DEVCTG (1 << 14) |
#define | G4X_ELD_ADDR (0xf << 5) |
#define | G4X_ELD_ACK (1 << 4) |
#define | G4X_HDMIW_HDMIEDID 0x6210C |
#define | IBX_HDMIW_HDMIEDID_A 0xE2050 |
#define | IBX_HDMIW_HDMIEDID_B 0xE2150 |
#define | IBX_HDMIW_HDMIEDID(pipe) |
#define | IBX_AUD_CNTL_ST_A 0xE20B4 |
#define | IBX_AUD_CNTL_ST_B 0xE21B4 |
#define | IBX_AUD_CNTL_ST(pipe) |
#define | IBX_ELD_BUFFER_SIZE (0x1f << 10) |
#define | IBX_ELD_ADDRESS (0x1f << 5) |
#define | IBX_ELD_ACK (1 << 4) |
#define | IBX_AUD_CNTL_ST2 0xE20C0 |
#define | IBX_ELD_VALIDB (1 << 0) |
#define | IBX_CP_READYB (1 << 1) |
#define | CPT_HDMIW_HDMIEDID_A 0xE5050 |
#define | CPT_HDMIW_HDMIEDID_B 0xE5150 |
#define | CPT_HDMIW_HDMIEDID(pipe) |
#define | CPT_AUD_CNTL_ST_A 0xE50B4 |
#define | CPT_AUD_CNTL_ST_B 0xE51B4 |
#define | CPT_AUD_CNTL_ST(pipe) |
#define | CPT_AUD_CNTRL_ST2 0xE50C0 |
#define | GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) |
#define | IBX_AUD_CONFIG_A 0xe2000 |
#define | IBX_AUD_CONFIG_B 0xe2100 |
#define | IBX_AUD_CFG(pipe) |
#define | CPT_AUD_CONFIG_A 0xe5000 |
#define | CPT_AUD_CONFIG_B 0xe5100 |
#define | CPT_AUD_CFG(pipe) |
#define | AUD_CONFIG_N_VALUE_INDEX (1 << 29) |
#define | AUD_CONFIG_N_PROG_ENABLE (1 << 28) |
#define | AUD_CONFIG_UPPER_N_SHIFT 20 |
#define | AUD_CONFIG_UPPER_N_VALUE (0xff << 20) |
#define | AUD_CONFIG_LOWER_N_SHIFT 4 |
#define | AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) |
#define | AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 |
#define | AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) |
#define | AUD_CONFIG_DISABLE_NCTS (1 << 3) |
#define | HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */ |
#define | HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */ |
#define | HSW_AUD_CFG(pipe) |
#define | HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */ |
#define | HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */ |
#define | HSW_AUD_MISC_CTRL(pipe) |
#define | HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */ |
#define | HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */ |
#define | HSW_AUD_DIP_ELD_CTRL(pipe) |
#define | HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */ |
#define | HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */ |
#define | AUD_DIG_CNVT(pipe) |
#define | DIP_PORT_SEL_MASK 0x3 |
#define | HSW_AUD_EDID_DATA_A 0x65050 |
#define | HSW_AUD_EDID_DATA_B 0x65150 |
#define | HSW_AUD_EDID_DATA(pipe) |
#define | HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */ |
#define | HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */ |
#define | AUDIO_INACTIVE_C (1<<11) |
#define | AUDIO_INACTIVE_B (1<<7) |
#define | AUDIO_INACTIVE_A (1<<3) |
#define | AUDIO_OUTPUT_ENABLE_A (1<<2) |
#define | AUDIO_OUTPUT_ENABLE_B (1<<6) |
#define | AUDIO_OUTPUT_ENABLE_C (1<<10) |
#define | AUDIO_ELD_VALID_A (1<<0) |
#define | AUDIO_ELD_VALID_B (1<<4) |
#define | AUDIO_ELD_VALID_C (1<<8) |
#define | AUDIO_CP_READY_A (1<<1) |
#define | AUDIO_CP_READY_B (1<<5) |
#define | AUDIO_CP_READY_C (1<<9) |
#define | HSW_PWR_WELL_CTL1 0x45400 /* BIOS */ |
#define | HSW_PWR_WELL_CTL2 0x45404 /* Driver */ |
#define | HSW_PWR_WELL_CTL3 0x45408 /* KVMR */ |
#define | HSW_PWR_WELL_CTL4 0x4540C /* Debug */ |
#define | HSW_PWR_WELL_ENABLE (1UL<<31) |
#define | HSW_PWR_WELL_STATE (1<<30) |
#define | HSW_PWR_WELL_CTL5 0x45410 |
#define | HSW_PWR_WELL_ENABLE_SINGLE_STEP (1UL<<31) |
#define | HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) |
#define | HSW_PWR_WELL_FORCE_ON (1<<19) |
#define | HSW_PWR_WELL_CTL6 0x45414 |
#define | TRANS_DDI_FUNC_CTL_A 0x60400 |
#define | TRANS_DDI_FUNC_CTL_B 0x61400 |
#define | TRANS_DDI_FUNC_CTL_C 0x62400 |
#define | TRANS_DDI_FUNC_CTL_EDP 0x6F400 |
#define | TRANS_DDI_FUNC_CTL(tran) |
#define | TRANS_DDI_FUNC_ENABLE (1UL<<31) |
#define | TRANS_DDI_PORT_MASK (7<<28) |
#define | TRANS_DDI_SELECT_PORT(x) ((x)<<28) |
#define | TRANS_DDI_PORT_NONE (0<<28) |
#define | TRANS_DDI_MODE_SELECT_MASK (7<<24) |
#define | TRANS_DDI_MODE_SELECT_HDMI (0<<24) |
#define | TRANS_DDI_MODE_SELECT_DVI (1<<24) |
#define | TRANS_DDI_MODE_SELECT_DP_SST (2<<24) |
#define | TRANS_DDI_MODE_SELECT_DP_MST (3<<24) |
#define | TRANS_DDI_MODE_SELECT_FDI (4<<24) |
#define | TRANS_DDI_BPC_MASK (7<<20) |
#define | TRANS_DDI_BPC_8 (0<<20) |
#define | TRANS_DDI_BPC_10 (1<<20) |
#define | TRANS_DDI_BPC_6 (2<<20) |
#define | TRANS_DDI_BPC_12 (3<<20) |
#define | TRANS_DDI_PVSYNC (1<<17) |
#define | TRANS_DDI_PHSYNC (1<<16) |
#define | TRANS_DDI_EDP_INPUT_MASK (7<<12) |
#define | TRANS_DDI_EDP_INPUT_A_ON (0<<12) |
#define | TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) |
#define | TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) |
#define | TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) |
#define | TRANS_DDI_BFI_ENABLE (1<<4) |
#define | TRANS_DDI_PORT_WIDTH_X1 (0<<1) |
#define | TRANS_DDI_PORT_WIDTH_X2 (1<<1) |
#define | TRANS_DDI_PORT_WIDTH_X4 (3<<1) |
#define | DP_TP_CTL_A 0x64040 |
#define | DP_TP_CTL_B 0x64140 |
#define | DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) |
#define | DP_TP_CTL_ENABLE (1UL<<31) |
#define | DP_TP_CTL_MODE_SST (0<<27) |
#define | DP_TP_CTL_MODE_MST (1<<27) |
#define | DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) |
#define | DP_TP_CTL_FDI_AUTOTRAIN (1<<15) |
#define | DP_TP_CTL_LINK_TRAIN_MASK (7<<8) |
#define | DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) |
#define | DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) |
#define | DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) |
#define | DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) |
#define | DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) |
#define | DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) |
#define | DP_TP_STATUS_A 0x64044 |
#define | DP_TP_STATUS_B 0x64144 |
#define | DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) |
#define | DP_TP_STATUS_IDLE_DONE (1<<25) |
#define | DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) |
#define | DDI_BUF_CTL_A 0x64000 |
#define | DDI_BUF_CTL_B 0x64100 |
#define | DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) |
#define | DDI_BUF_CTL_ENABLE (1UL<<31) |
#define | DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ |
#define | DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ |
#define | DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ |
#define | DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ |
#define | DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ |
#define | DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ |
#define | DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ |
#define | DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ |
#define | DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ |
#define | DDI_BUF_EMP_MASK (0xf<<24) |
#define | DDI_BUF_IS_IDLE (1<<7) |
#define | DDI_A_4_LANES (1<<4) |
#define | DDI_PORT_WIDTH(width) (((width) - 1) << 1) |
#define | DDI_PORT_WIDTH_X1 (0<<1) |
#define | DDI_PORT_WIDTH_X2 (1<<1) |
#define | DDI_PORT_WIDTH_X4 (3<<1) |
#define | DDI_INIT_DISPLAY_DETECTED (1<<0) |
#define | DDI_BUF_TRANS_A 0x64E00 |
#define | DDI_BUF_TRANS_B 0x64E60 |
#define | DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) |
#define | SBI_ADDR 0xC6000 |
#define | SBI_DATA 0xC6004 |
#define | SBI_CTL_STAT 0xC6008 |
#define | SBI_CTL_DEST_ICLK (0x0<<16) |
#define | SBI_CTL_DEST_MPHY (0x1<<16) |
#define | SBI_CTL_OP_IORD (0x2<<8) |
#define | SBI_CTL_OP_IOWR (0x3<<8) |
#define | SBI_CTL_OP_CRRD (0x6<<8) |
#define | SBI_CTL_OP_CRWR (0x7<<8) |
#define | SBI_RESPONSE_FAIL (0x1<<1) |
#define | SBI_RESPONSE_SUCCESS (0x0<<1) |
#define | SBI_BUSY (0x1<<0) |
#define | SBI_READY (0x0<<0) |
#define | SBI_SSCDIVINTPHASE6 0x0600 |
#define | SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) |
#define | SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) |
#define | SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) |
#define | SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) |
#define | SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) |
#define | SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) |
#define | SBI_SSCCTL 0x020c |
#define | SBI_SSCCTL6 0x060C |
#define | SBI_SSCCTL_PATHALT (1<<3) |
#define | SBI_SSCCTL_DISABLE (1<<0) |
#define | SBI_SSCAUXDIV6 0x0610 |
#define | SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) |
#define | SBI_DBUFF0 0x2a00 |
#define | SBI_DBUFF0_ENABLE (1<<0) |
#define | PIXCLK_GATE 0xC6020 |
#define | PIXCLK_GATE_UNGATE (1<<0) |
#define | PIXCLK_GATE_GATE (0<<0) |
#define | SPLL_CTL 0x46020 |
#define | SPLL_PLL_ENABLE (1UL<<31) |
#define | SPLL_PLL_SSC (1<<28) |
#define | SPLL_PLL_NON_SSC (2<<28) |
#define | SPLL_PLL_FREQ_810MHz (0<<26) |
#define | SPLL_PLL_FREQ_1350MHz (1<<26) |
#define | WRPLL_CTL1 0x46040 |
#define | WRPLL_CTL2 0x46060 |
#define | WRPLL_PLL_ENABLE (1UL<<31) |
#define | WRPLL_PLL_SELECT_SSC (0x01<<28) |
#define | WRPLL_PLL_SELECT_NON_SSC (0x02<<28) |
#define | WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) |
#define | WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) |
#define | WRPLL_DIVIDER_POST(x) ((x)<<8) |
#define | WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) |
#define | PORT_CLK_SEL_A 0x46100 |
#define | PORT_CLK_SEL_B 0x46104 |
#define | PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B) |
#define | PORT_CLK_SEL_LCPLL_2700 (0<<29) |
#define | PORT_CLK_SEL_LCPLL_1350 (1<<29) |
#define | PORT_CLK_SEL_LCPLL_810 (2<<29) |
#define | PORT_CLK_SEL_SPLL (3<<29) |
#define | PORT_CLK_SEL_WRPLL1 (4<<29) |
#define | PORT_CLK_SEL_WRPLL2 (5<<29) |
#define | PORT_CLK_SEL_NONE (7<<29) |
#define | TRANS_CLK_SEL_A 0x46140 |
#define | TRANS_CLK_SEL_B 0x46144 |
#define | TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) |
#define | TRANS_CLK_SEL_DISABLED (0x0<<29) |
#define | TRANS_CLK_SEL_PORT(x) ((x+1)<<29) |
#define | _TRANSA_MSA_MISC 0x60410 |
#define | _TRANSB_MSA_MISC 0x61410 |
#define | TRANS_MSA_MISC(tran) |
#define | TRANS_MSA_SYNC_CLK (1<<0) |
#define | TRANS_MSA_6_BPC (0<<5) |
#define | TRANS_MSA_8_BPC (1<<5) |
#define | TRANS_MSA_10_BPC (2<<5) |
#define | TRANS_MSA_12_BPC (3<<5) |
#define | TRANS_MSA_16_BPC (4<<5) |
#define | LCPLL_CTL 0x130040 |
#define | LCPLL_PLL_DISABLE (1UL<<31) |
#define | LCPLL_PLL_LOCK (1<<30) |
#define | LCPLL_CLK_FREQ_MASK (3<<26) |
#define | LCPLL_CLK_FREQ_450 (0<<26) |
#define | LCPLL_CD_CLOCK_DISABLE (1<<25) |
#define | LCPLL_CD2X_CLOCK_DISABLE (1<<23) |
#define | LCPLL_CD_SOURCE_FCLK (1<<21) |
#define | PIPE_WM_LINETIME_A 0x45270 |
#define | PIPE_WM_LINETIME_B 0x45274 |
#define | PIPE_WM_LINETIME(pipe) |
#define | PIPE_WM_LINETIME_MASK (0x1ff) |
#define | PIPE_WM_LINETIME_TIME(x) ((x)) |
#define | PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) |
#define | PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) |
#define | SFUSE_STRAP 0xc2014 |
#define | SFUSE_STRAP_DDIB_DETECTED (1<<2) |
#define | SFUSE_STRAP_DDIC_DETECTED (1<<1) |
#define | SFUSE_STRAP_DDID_DETECTED (1<<0) |
#define | WM_DBG 0x45280 |
#define | WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) |
#define | WM_DBG_DISALLOW_MAXFIFO (1<<1) |
#define | WM_DBG_DISALLOW_SPRITE (1<<2) |
#define | NDE_RSTWRN_OPT 0x46408 |
#define | RST_PCH_HNDSHK_EN (1<<4) |
#define _3D_CHICKEN 0x02084 |
Definition at line 487 of file i915_reg.h.
#define _3D_CHICKEN2 0x0208c |
Definition at line 489 of file i915_reg.h.
#define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) |
Definition at line 494 of file i915_reg.h.
#define _3D_CHICKEN3 0x02090 |
Definition at line 495 of file i915_reg.h.
#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) |
Definition at line 497 of file i915_reg.h.
#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) |
Definition at line 488 of file i915_reg.h.
#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) |
Definition at line 496 of file i915_reg.h.
#define _BCLRPAT_A 0x60020 |
Definition at line 1235 of file i915_reg.h.
#define _BCLRPAT_B 0x61020 |
Definition at line 1246 of file i915_reg.h.
#define _BXT_BLC_PWM_CTL1 0xC8250 |
Definition at line 1676 of file i915_reg.h.
#define _BXT_BLC_PWM_CTL2 0xC8350 |
Definition at line 1682 of file i915_reg.h.
#define _BXT_BLC_PWM_DUTY1 0xC8258 |
Definition at line 1680 of file i915_reg.h.
#define _BXT_BLC_PWM_DUTY2 0xC8358 |
Definition at line 1684 of file i915_reg.h.
#define _BXT_BLC_PWM_FREQ1 0xC8254 |
Definition at line 1679 of file i915_reg.h.
#define _BXT_BLC_PWM_FREQ2 0xC8354 |
Definition at line 1683 of file i915_reg.h.
#define _CURABASE 0x70084 |
Definition at line 2693 of file i915_reg.h.
#define _CURACNTR 0x70080 |
Definition at line 2672 of file i915_reg.h.
#define _CURAPOS 0x70088 |
Definition at line 2694 of file i915_reg.h.
#define _CURBBASE 0x700c4 |
Definition at line 2701 of file i915_reg.h.
#define _CURBBASE_IVB 0x71084 |
Definition at line 2705 of file i915_reg.h.
#define _CURBCNTR 0x700c0 |
Definition at line 2700 of file i915_reg.h.
#define _CURBCNTR_IVB 0x71080 |
Definition at line 2704 of file i915_reg.h.
#define _CURBPOS 0x700c8 |
Definition at line 2702 of file i915_reg.h.
#define _CURBPOS_IVB 0x71088 |
Definition at line 2706 of file i915_reg.h.
#define _DPIO_CORE_CLK_A 0x801c |
Definition at line 353 of file i915_reg.h.
#define _DPIO_CORE_CLK_B 0x803c |
Definition at line 354 of file i915_reg.h.
#define _DPIO_DIV_A 0x800c |
Definition at line 330 of file i915_reg.h.
#define _DPIO_DIV_B 0x802c |
Definition at line 339 of file i915_reg.h.
#define _DPIO_LFP_COEFF_A 0x8048 |
Definition at line 357 of file i915_reg.h.
#define _DPIO_LFP_COEFF_B 0x8068 |
Definition at line 358 of file i915_reg.h.
#define _DPIO_REFSFR_A 0x8014 |
Definition at line 342 of file i915_reg.h.
#define _DPIO_REFSFR_B 0x8034 |
Definition at line 350 of file i915_reg.h.
#define _DPLL_A 0x06014 |
Definition at line 887 of file i915_reg.h.
#define _DPLL_A_MD 0x0601c /* 965+ only */ |
Definition at line 969 of file i915_reg.h.
#define _DPLL_B 0x06018 |
Definition at line 888 of file i915_reg.h.
#define _DPLL_B_MD 0x06020 /* 965+ only */ |
Definition at line 1006 of file i915_reg.h.
#define _DSPAADDR 0x70184 |
Definition at line 2750 of file i915_reg.h.
#define _DSPACNTR 0x70180 |
Definition at line 2717 of file i915_reg.h.
#define _DSPAOFFSET 0x701A4 /* HSW */ |
Definition at line 2756 of file i915_reg.h.
#define _DSPAPOS 0x7018C /* reserved */ |
Definition at line 2752 of file i915_reg.h.
#define _DSPASIZE 0x70190 |
Definition at line 2753 of file i915_reg.h.
#define _DSPASTRIDE 0x70188 |
Definition at line 2751 of file i915_reg.h.
#define _DSPASURF 0x7019C /* 965+ only */ |
Definition at line 2754 of file i915_reg.h.
#define _DSPASURFLIVE 0x701AC |
Definition at line 2757 of file i915_reg.h.
#define _DSPATILEOFF 0x701A4 /* 965+ only */ |
Definition at line 2755 of file i915_reg.h.
#define _DSPBADDR 0x71184 |
Definition at line 2807 of file i915_reg.h.
#define _DSPBCNTR 0x71180 |
Definition at line 2802 of file i915_reg.h.
#define _DSPBOFFSET 0x711A4 |
Definition at line 2813 of file i915_reg.h.
#define _DSPBPOS 0x7118C |
Definition at line 2809 of file i915_reg.h.
#define _DSPBSIZE 0x71190 |
Definition at line 2810 of file i915_reg.h.
#define _DSPBSTRIDE 0x71188 |
Definition at line 2808 of file i915_reg.h.
#define _DSPBSURF 0x7119C |
Definition at line 2811 of file i915_reg.h.
#define _DSPBSURFLIVE 0x711AC |
Definition at line 2814 of file i915_reg.h.
#define _DSPBTILEOFF 0x711A4 |
Definition at line 2812 of file i915_reg.h.
#define _DVSACNTR 0x72180 |
Definition at line 2817 of file i915_reg.h.
#define _DVSAGAMC 0x72300 |
Definition at line 2853 of file i915_reg.h.
#define _DVSAKEYMAXVAL 0x721a0 |
Definition at line 2842 of file i915_reg.h.
#define _DVSAKEYMSK 0x72198 |
Definition at line 2840 of file i915_reg.h.
#define _DVSAKEYVAL 0x72194 |
Definition at line 2839 of file i915_reg.h.
#define _DVSALINOFF 0x72184 |
Definition at line 2835 of file i915_reg.h.
#define _DVSAPOS 0x7218c |
Definition at line 2837 of file i915_reg.h.
#define _DVSASCALE 0x72204 |
Definition at line 2845 of file i915_reg.h.
#define _DVSASIZE 0x72190 |
Definition at line 2838 of file i915_reg.h.
#define _DVSASTRIDE 0x72188 |
Definition at line 2836 of file i915_reg.h.
#define _DVSASURF 0x7219c |
Definition at line 2841 of file i915_reg.h.
#define _DVSASURFLIVE 0x721ac |
Definition at line 2844 of file i915_reg.h.
#define _DVSATILEOFF 0x721a4 |
Definition at line 2843 of file i915_reg.h.
#define _DVSBCNTR 0x73180 |
Definition at line 2855 of file i915_reg.h.
#define _DVSBGAMC 0x73300 |
Definition at line 2867 of file i915_reg.h.
#define _DVSBKEYMAXVAL 0x731a0 |
Definition at line 2863 of file i915_reg.h.
#define _DVSBKEYMSK 0x73198 |
Definition at line 2861 of file i915_reg.h.
#define _DVSBKEYVAL 0x73194 |
Definition at line 2860 of file i915_reg.h.
#define _DVSBLINOFF 0x73184 |
Definition at line 2856 of file i915_reg.h.
#define _DVSBPOS 0x7318c |
Definition at line 2858 of file i915_reg.h.
#define _DVSBSCALE 0x73204 |
Definition at line 2866 of file i915_reg.h.
#define _DVSBSIZE 0x73190 |
Definition at line 2859 of file i915_reg.h.
#define _DVSBSTRIDE 0x73188 |
Definition at line 2857 of file i915_reg.h.
#define _DVSBSURF 0x7319c |
Definition at line 2862 of file i915_reg.h.
#define _DVSBSURFLIVE 0x731ac |
Definition at line 2865 of file i915_reg.h.
#define _DVSBTILEOFF 0x731a4 |
Definition at line 2864 of file i915_reg.h.
#define _FDI_RXA_CHICKEN 0xc200c |
Definition at line 3568 of file i915_reg.h.
#define _FDI_RXA_CTL 0xf000c |
Definition at line 3630 of file i915_reg.h.
#define _FDI_RXA_IIR 0xf0014 |
Definition at line 3694 of file i915_reg.h.
#define _FDI_RXA_IMR 0xf0018 |
Definition at line 3695 of file i915_reg.h.
#define _FDI_RXA_MISC 0xf0010 |
Definition at line 3663 of file i915_reg.h.
#define _FDI_RXA_TUSIZE1 0xf0030 |
Definition at line 3674 of file i915_reg.h.
#define _FDI_RXA_TUSIZE2 0xf0038 |
Definition at line 3675 of file i915_reg.h.
#define _FDI_RXB_CHICKEN 0xc2010 |
Definition at line 3569 of file i915_reg.h.
#define _FDI_RXB_CTL 0xf100c |
Definition at line 3631 of file i915_reg.h.
#define _FDI_RXB_IIR 0xf1014 |
Definition at line 3696 of file i915_reg.h.
#define _FDI_RXB_IMR 0xf1018 |
Definition at line 3697 of file i915_reg.h.
#define _FDI_RXB_MISC 0xf1010 |
Definition at line 3664 of file i915_reg.h.
#define _FDI_RXB_TUSIZE1 0xf1030 |
Definition at line 3676 of file i915_reg.h.
#define _FDI_RXB_TUSIZE2 0xf1038 |
Definition at line 3677 of file i915_reg.h.
#define _FDI_TXA_CTL 0x60100 |
Definition at line 3579 of file i915_reg.h.
#define _FDI_TXB_CTL 0x61100 |
Definition at line 3580 of file i915_reg.h.
#define _FPA0 0x06040 |
Definition at line 1009 of file i915_reg.h.
#define _FPA1 0x06044 |
Definition at line 1010 of file i915_reg.h.
#define _FPB0 0x06048 |
Definition at line 1011 of file i915_reg.h.
#define _FPB1 0x0604c |
Definition at line 1012 of file i915_reg.h.
#define _HBLANK_A 0x60004 |
Definition at line 1229 of file i915_reg.h.
#define _HBLANK_B 0x61004 |
Definition at line 1240 of file i915_reg.h.
#define _HSYNC_A 0x60008 |
Definition at line 1230 of file i915_reg.h.
#define _HSYNC_B 0x61008 |
Definition at line 1241 of file i915_reg.h.
#define _HTOTAL_A 0x60000 |
Definition at line 1228 of file i915_reg.h.
#define _HTOTAL_B 0x61000 |
Definition at line 1239 of file i915_reg.h.
#define _LGC_PALETTE_A 0x4a000 |
Definition at line 3080 of file i915_reg.h.
#define _LGC_PALETTE_B 0x4a800 |
Definition at line 3081 of file i915_reg.h.
#define _MASKED_BIT_DISABLE | ( | a | ) | ((a) << 16) |
Definition at line 12 of file i915_reg.h.
#define _MASKED_BIT_ENABLE | ( | a | ) | (((a) << 16) | (a)) |
Definition at line 11 of file i915_reg.h.
#define _PALETTE_A 0x0a000 |
Definition at line 1156 of file i915_reg.h.
#define _PALETTE_B 0x0a800 |
Definition at line 1157 of file i915_reg.h.
#define _PCH_DPLL | ( | pll | ) | (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) |
Definition at line 3332 of file i915_reg.h.
#define _PCH_DPLL_A 0xc6014 |
Definition at line 3330 of file i915_reg.h.
#define _PCH_DPLL_B 0xc6018 |
Definition at line 3331 of file i915_reg.h.
Definition at line 3339 of file i915_reg.h.
Definition at line 3340 of file i915_reg.h.
#define _PCH_FPA0 0xc6040 |
Definition at line 3334 of file i915_reg.h.
#define _PCH_FPA1 0xc6044 |
Definition at line 3336 of file i915_reg.h.
#define _PCH_FPB0 0xc6048 |
Definition at line 3337 of file i915_reg.h.
#define _PCH_FPB1 0xc604c |
Definition at line 3338 of file i915_reg.h.
#define _PCH_TRANSACONF 0xf0008 |
Definition at line 3524 of file i915_reg.h.
#define _PCH_TRANSBCONF 0xf1008 |
Definition at line 3525 of file i915_reg.h.
#define _PFA_CTL_1 0x68080 |
Definition at line 3054 of file i915_reg.h.
#define _PFA_HSCALE 0x68090 |
Definition at line 3070 of file i915_reg.h.
#define _PFA_VSCALE 0x68084 |
Definition at line 3068 of file i915_reg.h.
#define _PFA_WIN_POS 0x68070 |
Definition at line 3066 of file i915_reg.h.
#define _PFA_WIN_SZ 0x68074 |
Definition at line 3064 of file i915_reg.h.
#define _PFB_CTL_1 0x68880 |
Definition at line 3055 of file i915_reg.h.
#define _PFB_HSCALE 0x68890 |
Definition at line 3071 of file i915_reg.h.
#define _PFB_VSCALE 0x68884 |
Definition at line 3069 of file i915_reg.h.
#define _PFB_WIN_POS 0x68870 |
Definition at line 3067 of file i915_reg.h.
#define _PFB_WIN_SZ 0x68874 |
Definition at line 3065 of file i915_reg.h.
Definition at line 6 of file i915_reg.h.
#define _PIPEA_DATA_M1 0x60030 |
Definition at line 3003 of file i915_reg.h.
#define _PIPEA_DATA_M2 0x60038 |
Definition at line 3014 of file i915_reg.h.
#define _PIPEA_DATA_N1 0x60034 |
Definition at line 3011 of file i915_reg.h.
#define _PIPEA_DATA_N2 0x6003c |
Definition at line 3016 of file i915_reg.h.
#define _PIPEA_DP_LINK_M 0x70060 |
Definition at line 2348 of file i915_reg.h.
#define _PIPEA_DP_LINK_N 0x70064 |
Definition at line 2352 of file i915_reg.h.
#define _PIPEA_FLIPCOUNT_GM45 0x70044 |
Definition at line 2668 of file i915_reg.h.
#define _PIPEA_FRMCOUNT_GM45 0x70040 |
Definition at line 2667 of file i915_reg.h.
#define _PIPEA_GMCH_DATA_M 0x70050 |
Definition at line 2324 of file i915_reg.h.
#define _PIPEA_GMCH_DATA_N 0x70054 |
Definition at line 2333 of file i915_reg.h.
#define _PIPEA_LINK_M1 0x60040 |
Definition at line 3019 of file i915_reg.h.
#define _PIPEA_LINK_M2 0x60048 |
Definition at line 3024 of file i915_reg.h.
#define _PIPEA_LINK_N1 0x60044 |
Definition at line 3021 of file i915_reg.h.
#define _PIPEA_LINK_N2 0x6004c |
Definition at line 3026 of file i915_reg.h.
#define _PIPEACONF 0x70008 |
Definition at line 2367 of file i915_reg.h.
#define _PIPEADSL 0x70000 |
Definition at line 2364 of file i915_reg.h.
#define _PIPEAFRAMEHIGH 0x70040 |
Definition at line 2658 of file i915_reg.h.
#define _PIPEAFRAMEPIXEL 0x70044 |
Definition at line 2661 of file i915_reg.h.
#define _PIPEASRC 0x6001c |
Definition at line 1234 of file i915_reg.h.
#define _PIPEASTAT 0x70024 |
Definition at line 2407 of file i915_reg.h.
#define _PIPEB_DATA_M1 0x61030 |
Definition at line 3031 of file i915_reg.h.
#define _PIPEB_DATA_M2 0x61038 |
Definition at line 3034 of file i915_reg.h.
#define _PIPEB_DATA_N1 0x61034 |
Definition at line 3032 of file i915_reg.h.
#define _PIPEB_DATA_N2 0x6103c |
Definition at line 3035 of file i915_reg.h.
#define _PIPEB_DP_LINK_M 0x71060 |
Definition at line 2349 of file i915_reg.h.
#define _PIPEB_DP_LINK_N 0x71064 |
Definition at line 2353 of file i915_reg.h.
#define _PIPEB_FLIPCOUNT_GM45 0x71044 |
Definition at line 2799 of file i915_reg.h.
#define _PIPEB_FRMCOUNT_GM45 0x71040 |
Definition at line 2798 of file i915_reg.h.
#define _PIPEB_GMCH_DATA_M 0x71050 |
Definition at line 2325 of file i915_reg.h.
#define _PIPEB_GMCH_DATA_N 0x71054 |
Definition at line 2334 of file i915_reg.h.
#define _PIPEB_LINK_M1 0x61040 |
Definition at line 3037 of file i915_reg.h.
#define _PIPEB_LINK_M2 0x61048 |
Definition at line 3040 of file i915_reg.h.
#define _PIPEB_LINK_N1 0x61044 |
Definition at line 3038 of file i915_reg.h.
#define _PIPEB_LINK_N2 0x6104c |
Definition at line 3041 of file i915_reg.h.
#define _PIPEBCONF 0x71008 |
Definition at line 2794 of file i915_reg.h.
#define _PIPEBDSL 0x71000 |
Definition at line 2793 of file i915_reg.h.
#define _PIPEBFRAMEHIGH 0x71040 |
Definition at line 2796 of file i915_reg.h.
#define _PIPEBFRAMEPIXEL 0x71044 |
Definition at line 2797 of file i915_reg.h.
#define _PIPEBSRC 0x6101c |
Definition at line 1245 of file i915_reg.h.
#define _PIPEBSTAT 0x71024 |
Definition at line 2795 of file i915_reg.h.
Definition at line 9 of file i915_reg.h.
#define _SPRA_CTL 0x70280 |
Definition at line 2882 of file i915_reg.h.
#define _SPRA_GAMC 0x70400 |
Definition at line 2925 of file i915_reg.h.
#define _SPRA_KEYMAX 0x702a0 |
Definition at line 2913 of file i915_reg.h.
#define _SPRA_KEYMSK 0x70298 |
Definition at line 2911 of file i915_reg.h.
#define _SPRA_KEYVAL 0x70294 |
Definition at line 2910 of file i915_reg.h.
#define _SPRA_LINOFF 0x70284 |
Definition at line 2906 of file i915_reg.h.
#define _SPRA_OFFSET 0x702a4 |
Definition at line 2915 of file i915_reg.h.
#define _SPRA_POS 0x7028c |
Definition at line 2908 of file i915_reg.h.
#define _SPRA_SCALE 0x70304 |
Definition at line 2917 of file i915_reg.h.
#define _SPRA_SIZE 0x70290 |
Definition at line 2909 of file i915_reg.h.
#define _SPRA_STRIDE 0x70288 |
Definition at line 2907 of file i915_reg.h.
#define _SPRA_SURF 0x7029c |
Definition at line 2912 of file i915_reg.h.
#define _SPRA_SURFLIVE 0x702ac |
Definition at line 2916 of file i915_reg.h.
#define _SPRA_TILEOFF 0x702a4 |
Definition at line 2914 of file i915_reg.h.
#define _SPRB_CTL 0x71280 |
Definition at line 2927 of file i915_reg.h.
#define _SPRB_GAMC 0x71400 |
Definition at line 2940 of file i915_reg.h.
#define _SPRB_KEYMAX 0x712a0 |
Definition at line 2935 of file i915_reg.h.
#define _SPRB_KEYMSK 0x71298 |
Definition at line 2933 of file i915_reg.h.
#define _SPRB_KEYVAL 0x71294 |
Definition at line 2932 of file i915_reg.h.
#define _SPRB_LINOFF 0x71284 |
Definition at line 2928 of file i915_reg.h.
#define _SPRB_OFFSET 0x712a4 |
Definition at line 2937 of file i915_reg.h.
#define _SPRB_POS 0x7128c |
Definition at line 2930 of file i915_reg.h.
#define _SPRB_SCALE 0x71304 |
Definition at line 2939 of file i915_reg.h.
#define _SPRB_SIZE 0x71290 |
Definition at line 2931 of file i915_reg.h.
#define _SPRB_STRIDE 0x71288 |
Definition at line 2929 of file i915_reg.h.
#define _SPRB_SURF 0x7129c |
Definition at line 2934 of file i915_reg.h.
#define _SPRB_SURFLIVE 0x712ac |
Definition at line 2938 of file i915_reg.h.
#define _SPRB_TILEOFF 0x712a4 |
Definition at line 2936 of file i915_reg.h.
#define _TRANS_HBLANK_A 0xe0004 |
Definition at line 3395 of file i915_reg.h.
#define _TRANS_HBLANK_B 0xe1004 |
Definition at line 3487 of file i915_reg.h.
#define _TRANS_HSYNC_A 0xe0008 |
Definition at line 3398 of file i915_reg.h.
#define _TRANS_HSYNC_B 0xe1008 |
Definition at line 3488 of file i915_reg.h.
#define _TRANS_HTOTAL_A 0xe0000 |
Definition at line 3392 of file i915_reg.h.
#define _TRANS_HTOTAL_B 0xe1000 |
Definition at line 3486 of file i915_reg.h.
#define _TRANS_VBLANK_A 0xe0010 |
Definition at line 3404 of file i915_reg.h.
#define _TRANS_VBLANK_B 0xe1010 |
Definition at line 3490 of file i915_reg.h.
#define _TRANS_VSYNC_A 0xe0014 |
Definition at line 3407 of file i915_reg.h.
#define _TRANS_VSYNC_B 0xe1014 |
Definition at line 3491 of file i915_reg.h.
#define _TRANS_VSYNCSHIFT_A 0xe0028 |
Definition at line 3410 of file i915_reg.h.
#define _TRANS_VSYNCSHIFT_B 0xe1028 |
Definition at line 3492 of file i915_reg.h.
#define _TRANS_VTOTAL_A 0xe000c |
Definition at line 3401 of file i915_reg.h.
#define _TRANS_VTOTAL_B 0xe100c |
Definition at line 3489 of file i915_reg.h.
#define _TRANSA_CHICKEN1 0xf0060 |
Definition at line 3547 of file i915_reg.h.
#define _TRANSA_CHICKEN2 0xf0064 |
Definition at line 3551 of file i915_reg.h.
#define _TRANSA_DATA_M1 0xe0030 |
Definition at line 3412 of file i915_reg.h.
#define _TRANSA_DATA_M2 0xe0038 |
Definition at line 3414 of file i915_reg.h.
#define _TRANSA_DATA_N1 0xe0034 |
Definition at line 3413 of file i915_reg.h.
#define _TRANSA_DATA_N2 0xe003c |
Definition at line 3415 of file i915_reg.h.
#define _TRANSA_DP_LINK_M1 0xe0040 |
Definition at line 3416 of file i915_reg.h.
#define _TRANSA_DP_LINK_M2 0xe0048 |
Definition at line 3418 of file i915_reg.h.
#define _TRANSA_DP_LINK_N1 0xe0044 |
Definition at line 3417 of file i915_reg.h.
#define _TRANSA_DP_LINK_N2 0xe004c |
Definition at line 3419 of file i915_reg.h.
#define _TRANSA_MSA_MISC 0x60410 |
Definition at line 4337 of file i915_reg.h.
#define _TRANSACONF 0xf0008 |
Definition at line 3521 of file i915_reg.h.
#define _TRANSB_CHICKEN1 0xf1060 |
Definition at line 3548 of file i915_reg.h.
#define _TRANSB_CHICKEN2 0xf1064 |
Definition at line 3552 of file i915_reg.h.
#define _TRANSB_DATA_M1 0xe1030 |
Definition at line 3503 of file i915_reg.h.
#define _TRANSB_DATA_M2 0xe1038 |
Definition at line 3505 of file i915_reg.h.
#define _TRANSB_DATA_N1 0xe1034 |
Definition at line 3504 of file i915_reg.h.
#define _TRANSB_DATA_N2 0xe103c |
Definition at line 3506 of file i915_reg.h.
#define _TRANSB_DP_LINK_M1 0xe1040 |
Definition at line 3507 of file i915_reg.h.
#define _TRANSB_DP_LINK_M2 0xe1048 |
Definition at line 3509 of file i915_reg.h.
#define _TRANSB_DP_LINK_N1 0xe1044 |
Definition at line 3508 of file i915_reg.h.
#define _TRANSB_DP_LINK_N2 0xe104c |
Definition at line 3510 of file i915_reg.h.
#define _TRANSB_MSA_MISC 0x61410 |
Definition at line 4338 of file i915_reg.h.
#define _TRANSBCONF 0xf1008 |
Definition at line 3522 of file i915_reg.h.
#define _TRANSCODER | ( | tran, | |
a, | |||
b | |||
) | ((a) + (tran)*((b)-(a))) |
Definition at line 7 of file i915_reg.h.
#define _VBLANK_A 0x60010 |
Definition at line 1232 of file i915_reg.h.
#define _VBLANK_B 0x61010 |
Definition at line 1243 of file i915_reg.h.
#define _VIDEO_DIP_CTL_A 0xe0200 |
Definition at line 3423 of file i915_reg.h.
#define _VIDEO_DIP_CTL_B 0xe1200 |
Definition at line 3427 of file i915_reg.h.
#define _VIDEO_DIP_DATA_A 0xe0208 |
Definition at line 3424 of file i915_reg.h.
#define _VIDEO_DIP_DATA_B 0xe1208 |
Definition at line 3428 of file i915_reg.h.
#define _VIDEO_DIP_GCP_A 0xe0210 |
Definition at line 3425 of file i915_reg.h.
#define _VIDEO_DIP_GCP_B 0xe1210 |
Definition at line 3429 of file i915_reg.h.
#define _VSYNC_A 0x60014 |
Definition at line 1233 of file i915_reg.h.
#define _VSYNC_B 0x61014 |
Definition at line 1244 of file i915_reg.h.
#define _VSYNCSHIFT_A 0x60028 |
Definition at line 1236 of file i915_reg.h.
#define _VSYNCSHIFT_B 0x61028 |
Definition at line 1247 of file i915_reg.h.
#define _VTOTAL_A 0x6000c |
Definition at line 1231 of file i915_reg.h.
#define _VTOTAL_B 0x6100c |
Definition at line 1242 of file i915_reg.h.
#define ACTHD 0x020c8 |
Definition at line 562 of file i915_reg.h.
#define ACTHD_I965 0x02074 |
Definition at line 464 of file i915_reg.h.
#define ADPA 0x61100 |
Definition at line 1259 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_ENABLE (1<<23) |
Definition at line 1275 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) |
Definition at line 1288 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ |
Definition at line 1270 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) |
Definition at line 1273 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) |
Definition at line 1272 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) |
Definition at line 1274 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) |
Definition at line 1271 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) |
Definition at line 1277 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) |
Definition at line 1276 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) |
Definition at line 1280 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) |
Definition at line 1281 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) |
Definition at line 1286 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) |
Definition at line 1287 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) |
Definition at line 1282 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) |
Definition at line 1283 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) |
Definition at line 1284 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) |
Definition at line 1285 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) |
Definition at line 1279 of file i915_reg.h.
#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) |
Definition at line 1278 of file i915_reg.h.
#define ADPA_DAC_DISABLE 0 |
Definition at line 1264 of file i915_reg.h.
#define ADPA_DAC_ENABLE (1UL<<31) |
Definition at line 1263 of file i915_reg.h.
#define ADPA_DPMS_MASK (~(3<<10)) |
Definition at line 1299 of file i915_reg.h.
#define ADPA_DPMS_OFF (3<<10) |
Definition at line 1303 of file i915_reg.h.
#define ADPA_DPMS_ON (0<<10) |
Definition at line 1300 of file i915_reg.h.
#define ADPA_DPMS_STANDBY (2<<10) |
Definition at line 1302 of file i915_reg.h.
#define ADPA_DPMS_SUSPEND (1<<10) |
Definition at line 1301 of file i915_reg.h.
#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) |
Definition at line 1297 of file i915_reg.h.
#define ADPA_HSYNC_ACTIVE_LOW 0 |
Definition at line 1298 of file i915_reg.h.
#define ADPA_HSYNC_CNTL_DISABLE (1<<10) |
Definition at line 1293 of file i915_reg.h.
#define ADPA_HSYNC_CNTL_ENABLE 0 |
Definition at line 1294 of file i915_reg.h.
#define ADPA_PIPE_A_SELECT 0 |
Definition at line 1266 of file i915_reg.h.
#define ADPA_PIPE_B_SELECT (1<<30) |
Definition at line 1267 of file i915_reg.h.
Definition at line 1268 of file i915_reg.h.
#define ADPA_PIPE_SELECT_MASK (1<<30) |
Definition at line 1265 of file i915_reg.h.
#define ADPA_SETS_HVPOLARITY 0 |
Definition at line 1290 of file i915_reg.h.
#define ADPA_USE_VGA_HVPOLARITY (1<<15) |
Definition at line 1289 of file i915_reg.h.
#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) |
Definition at line 1295 of file i915_reg.h.
#define ADPA_VSYNC_ACTIVE_LOW 0 |
Definition at line 1296 of file i915_reg.h.
#define ADPA_VSYNC_CNTL_DISABLE (1<<11) |
Definition at line 1291 of file i915_reg.h.
#define ADPA_VSYNC_CNTL_ENABLE 0 |
Definition at line 1292 of file i915_reg.h.
#define ARB_MODE 0x04030 |
Definition at line 421 of file i915_reg.h.
#define ARB_MODE_SWIZZLE_IVB (1<<5) |
Definition at line 423 of file i915_reg.h.
#define ARB_MODE_SWIZZLE_SNB (1<<4) |
Definition at line 422 of file i915_reg.h.
#define ASYNC_FLIP (1<<22) |
Definition at line 277 of file i915_reg.h.
#define ASYNC_FLIP_PERF_DISABLE (1 << 14) |
Definition at line 502 of file i915_reg.h.
#define AUD_CONFIG_DISABLE_NCTS (1 << 3) |
Definition at line 4108 of file i915_reg.h.
#define AUD_CONFIG_LOWER_N_SHIFT 4 |
Definition at line 4104 of file i915_reg.h.
#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) |
Definition at line 4105 of file i915_reg.h.
#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) |
Definition at line 4101 of file i915_reg.h.
#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) |
Definition at line 4100 of file i915_reg.h.
#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) |
Definition at line 4107 of file i915_reg.h.
#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 |
Definition at line 4106 of file i915_reg.h.
#define AUD_CONFIG_UPPER_N_SHIFT 20 |
Definition at line 4102 of file i915_reg.h.
#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) |
Definition at line 4103 of file i915_reg.h.
#define AUD_DIG_CNVT | ( | pipe | ) |
Definition at line 4132 of file i915_reg.h.
#define AUDIO_CP_READY_A (1<<1) |
Definition at line 4154 of file i915_reg.h.
#define AUDIO_CP_READY_B (1<<5) |
Definition at line 4155 of file i915_reg.h.
#define AUDIO_CP_READY_C (1<<9) |
Definition at line 4156 of file i915_reg.h.
#define AUDIO_ELD_VALID_A (1<<0) |
Definition at line 4151 of file i915_reg.h.
#define AUDIO_ELD_VALID_B (1<<4) |
Definition at line 4152 of file i915_reg.h.
#define AUDIO_ELD_VALID_C (1<<8) |
Definition at line 4153 of file i915_reg.h.
#define AUDIO_ENABLE (1 << 6) |
Definition at line 3721 of file i915_reg.h.
#define AUDIO_INACTIVE_A (1<<3) |
Definition at line 4147 of file i915_reg.h.
#define AUDIO_INACTIVE_B (1<<7) |
Definition at line 4146 of file i915_reg.h.
#define AUDIO_INACTIVE_C (1<<11) |
Definition at line 4145 of file i915_reg.h.
#define AUDIO_OUTPUT_ENABLE_A (1<<2) |
Definition at line 4148 of file i915_reg.h.
#define AUDIO_OUTPUT_ENABLE_B (1<<6) |
Definition at line 4149 of file i915_reg.h.
#define AUDIO_OUTPUT_ENABLE_C (1<<10) |
Definition at line 4150 of file i915_reg.h.
#define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ |
Definition at line 1044 of file i915_reg.h.
#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) |
Definition at line 1624 of file i915_reg.h.
#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) |
Definition at line 1625 of file i915_reg.h.
#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) |
Definition at line 1623 of file i915_reg.h.
#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) |
Definition at line 1614 of file i915_reg.h.
#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) |
Definition at line 1613 of file i915_reg.h.
#define BB_ADDR 0x02140 /* 8 bytes */ |
Definition at line 646 of file i915_reg.h.
#define BCLRPAT | ( | pipe | ) | _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) |
Definition at line 1255 of file i915_reg.h.
#define BIN_REGISTER_SET (1<<11) |
Definition at line 1647 of file i915_reg.h.
#define BLC_HIST_CTL 0x61260 |
Definition at line 1628 of file i915_reg.h.
#define BLC_PWM2_ENABLE (1UL<<31) |
Definition at line 1633 of file i915_reg.h.
#define BLC_PWM_CPU_CTL 0x48254 |
Definition at line 1634 of file i915_reg.h.
#define BLC_PWM_CPU_CTL2 0x48250 |
Definition at line 1632 of file i915_reg.h.
#define BLC_PWM_CTL 0x61254 |
Definition at line 1606 of file i915_reg.h.
#define BLC_PWM_CTL2 0x61250 /* 965+ only */ |
Definition at line 1587 of file i915_reg.h.
#define BLC_PWM_PCH_CTL1 0xc8250 |
Definition at line 1660 of file i915_reg.h.
#define BLC_PWM_PCH_CTL2 0xc8254 |
Definition at line 1664 of file i915_reg.h.
#define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ |
Definition at line 1079 of file i915_reg.h.
#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ |
Definition at line 1589 of file i915_reg.h.
#define BLM_HIST_CTL 0x48260 |
Definition at line 1636 of file i915_reg.h.
#define BLM_HIST_ENH 0x48264 |
Definition at line 1650 of file i915_reg.h.
#define BLM_HIST_EVENT_STATUS (1<<30) |
Definition at line 1654 of file i915_reg.h.
#define BLM_HIST_GUARD_BAND 0x48268 |
Definition at line 1652 of file i915_reg.h.
#define BLM_HIST_INTR_DELAY_MASK (0xFF<<22) |
Definition at line 1655 of file i915_reg.h.
#define BLM_HIST_INTR_DELAY_SHIFT 22 |
Definition at line 1656 of file i915_reg.h.
#define BLM_HIST_INTR_ENABLE (1UL<<31) |
Definition at line 1653 of file i915_reg.h.
#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ |
Definition at line 1615 of file i915_reg.h.
#define BLM_PCH_OVERRIDE_ENABLE (1 << 30) |
Definition at line 1662 of file i915_reg.h.
#define BLM_PCH_POLARITY (1 << 29) |
Definition at line 1663 of file i915_reg.h.
#define BLM_PCH_PWM_ENABLE (1UL << 31) |
Definition at line 1661 of file i915_reg.h.
#define BLM_PHASE_IN_COUNT_MASK (0xff << 8) |
Definition at line 1603 of file i915_reg.h.
#define BLM_PHASE_IN_COUNT_SHIFT (8) |
Definition at line 1602 of file i915_reg.h.
#define BLM_PHASE_IN_ENABLE (1 << 25) |
Definition at line 1598 of file i915_reg.h.
#define BLM_PHASE_IN_INCR_MASK (0xff << 0) |
Definition at line 1605 of file i915_reg.h.
#define BLM_PHASE_IN_INCR_SHIFT (0) |
Definition at line 1604 of file i915_reg.h.
#define BLM_PHASE_IN_INTERRUPT_ENABL (1 << 24) |
Definition at line 1599 of file i915_reg.h.
#define BLM_PHASE_IN_INTERRUPT_STATUS (1 << 26) |
Definition at line 1597 of file i915_reg.h.
#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) |
Definition at line 1601 of file i915_reg.h.
#define BLM_PHASE_IN_TIME_BASE_SHIFT (16) |
Definition at line 1600 of file i915_reg.h.
Definition at line 1595 of file i915_reg.h.
#define BLM_PIPE_A (0 << 29) |
Definition at line 1592 of file i915_reg.h.
#define BLM_PIPE_B (1 << 29) |
Definition at line 1593 of file i915_reg.h.
#define BLM_PIPE_C (2 << 29) /* ivb + */ |
Definition at line 1594 of file i915_reg.h.
#define BLM_PIPE_SELECT (1 << 29) |
Definition at line 1590 of file i915_reg.h.
#define BLM_PIPE_SELECT_IVB (3 << 29) |
Definition at line 1591 of file i915_reg.h.
#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ |
Definition at line 1596 of file i915_reg.h.
#define BLM_POLARITY_PNV (1 << 0) /* pnv only */ |
Definition at line 1626 of file i915_reg.h.
#define BLM_PWM_ENABLE (1UL << 31) |
Definition at line 1588 of file i915_reg.h.
#define BLT_DEPTH_16_1555 (2<<24) |
Definition at line 271 of file i915_reg.h.
#define BLT_DEPTH_16_565 (1<<24) |
Definition at line 270 of file i915_reg.h.
#define BLT_DEPTH_32 (3<<24) |
Definition at line 272 of file i915_reg.h.
#define BLT_DEPTH_8 (0<<24) |
Definition at line 269 of file i915_reg.h.
#define BLT_HWS_PGA_GEN7 (0x04280) |
Definition at line 428 of file i915_reg.h.
#define BLT_RING_BASE 0x22000 |
Definition at line 405 of file i915_reg.h.
#define BLT_ROP_GXCOPY (0xcc<<16) |
Definition at line 273 of file i915_reg.h.
#define BSD_HWS_PGA_GEN7 (0x04180) |
Definition at line 427 of file i915_reg.h.
#define BSD_RING_BASE 0x04000 |
Definition at line 403 of file i915_reg.h.
#define BXT_BLC_PWM_CTL | ( | controller | ) |
Definition at line 1686 of file i915_reg.h.
#define BXT_BLC_PWM_DUTY | ( | controller | ) |
Definition at line 1690 of file i915_reg.h.
#define BXT_BLC_PWM_ENABLE (1 << 31) |
Definition at line 1677 of file i915_reg.h.
#define BXT_BLC_PWM_FREQ | ( | controller | ) |
Definition at line 1688 of file i915_reg.h.
#define BXT_BLC_PWM_POLARITY (1 << 29) |
Definition at line 1678 of file i915_reg.h.
#define CACHE_MODE_0 0x02120 /* 915+ only */ |
Definition at line 637 of file i915_reg.h.
#define CACHE_MODE_1 0x7004 /* IVB+ */ |
Definition at line 654 of file i915_reg.h.
#define CCID 0x2180 |
Definition at line 1175 of file i915_reg.h.
#define CCID_EN (1<<0) |
Definition at line 1176 of file i915_reg.h.
#define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) |
Definition at line 3177 of file i915_reg.h.
#define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) |
Definition at line 3176 of file i915_reg.h.
#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) |
Definition at line 1145 of file i915_reg.h.
#define CM0_COLOR_EVICT_DISABLE (1<<3) |
Definition at line 643 of file i915_reg.h.
#define CM0_DEPTH_EVICT_DISABLE (1<<4) |
Definition at line 642 of file i915_reg.h.
#define CM0_DEPTH_WRITE_DISABLE (1<<1) |
Definition at line 644 of file i915_reg.h.
#define CM0_IZ_OPT_DISABLE (1<<6) |
Definition at line 639 of file i915_reg.h.
#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) |
Definition at line 638 of file i915_reg.h.
#define CM0_RC_OP_FLUSH_DISABLE (1<<0) |
Definition at line 645 of file i915_reg.h.
#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) |
Definition at line 641 of file i915_reg.h.
#define CM0_ZR_OPT_DISABLE (1<<5) |
Definition at line 640 of file i915_reg.h.
#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) |
Definition at line 276 of file i915_reg.h.
#define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) |
Definition at line 1085 of file i915_reg.h.
#define COLOR_FORMAT_12bpc (3 << 26) |
Definition at line 3712 of file i915_reg.h.
#define COLOR_FORMAT_8bpc (0) |
Definition at line 3711 of file i915_reg.h.
#define CPT_AUD_CFG | ( | pipe | ) |
Definition at line 4097 of file i915_reg.h.
#define CPT_AUD_CNTL_ST | ( | pipe | ) |
Definition at line 4079 of file i915_reg.h.
#define CPT_AUD_CNTL_ST_A 0xE50B4 |
Definition at line 4077 of file i915_reg.h.
#define CPT_AUD_CNTL_ST_B 0xE51B4 |
Definition at line 4078 of file i915_reg.h.
#define CPT_AUD_CNTRL_ST2 0xE50C0 |
Definition at line 4082 of file i915_reg.h.
#define CPT_AUD_CONFIG_A 0xe5000 |
Definition at line 4095 of file i915_reg.h.
#define CPT_AUD_CONFIG_B 0xe5100 |
Definition at line 4096 of file i915_reg.h.
#define CPT_HDMIW_HDMIEDID | ( | pipe | ) |
Definition at line 4074 of file i915_reg.h.
#define CPT_HDMIW_HDMIEDID_A 0xE5050 |
Definition at line 4072 of file i915_reg.h.
#define CPT_HDMIW_HDMIEDID_B 0xE5150 |
Definition at line 4073 of file i915_reg.h.
#define CPU_VGA_DISABLE (1UL<<31) |
Definition at line 2966 of file i915_reg.h.
#define CPU_VGACNTRL 0x41000 |
Definition at line 2965 of file i915_reg.h.
#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) |
Definition at line 1318 of file i915_reg.h.
#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) |
Definition at line 1320 of file i915_reg.h.
#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) |
Definition at line 1321 of file i915_reg.h.
#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) |
Definition at line 1322 of file i915_reg.h.
#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) |
Definition at line 1328 of file i915_reg.h.
#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) |
Definition at line 1329 of file i915_reg.h.
#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) |
Definition at line 1330 of file i915_reg.h.
#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) |
Definition at line 1331 of file i915_reg.h.
#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) |
Definition at line 1317 of file i915_reg.h.
#define CRT_HOTPLUG_INT_EN (1 << 9) |
Definition at line 1316 of file i915_reg.h.
#define CRT_HOTPLUG_INT_STATUS (1 << 11) |
Definition at line 1349 of file i915_reg.h.
#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) |
Definition at line 1352 of file i915_reg.h.
#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) |
Definition at line 1351 of file i915_reg.h.
#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) |
Definition at line 1353 of file i915_reg.h.
#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) |
Definition at line 1354 of file i915_reg.h.
#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) |
Definition at line 1323 of file i915_reg.h.
#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) |
Definition at line 1324 of file i915_reg.h.
#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) |
Definition at line 1325 of file i915_reg.h.
#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) |
Definition at line 1326 of file i915_reg.h.
#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) |
Definition at line 1327 of file i915_reg.h.
Definition at line 2709 of file i915_reg.h.
#define CURBASE_IVB | ( | pipe | ) | _PIPE(pipe, _CURABASE, _CURBBASE_IVB) |
Definition at line 2713 of file i915_reg.h.
Definition at line 2708 of file i915_reg.h.
#define CURCNTR_IVB | ( | pipe | ) | _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB) |
Definition at line 2712 of file i915_reg.h.
#define CURPOS_IVB | ( | pipe | ) | _PIPE(pipe, _CURAPOS, _CURBPOS_IVB) |
Definition at line 2714 of file i915_reg.h.
#define CURSIZE 0x700a0 |
Definition at line 2699 of file i915_reg.h.
#define CURSOR_ENABLE 0x80000000 |
Definition at line 2674 of file i915_reg.h.
#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) |
Definition at line 2679 of file i915_reg.h.
#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) |
Definition at line 2680 of file i915_reg.h.
#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) |
Definition at line 2681 of file i915_reg.h.
#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) |
Definition at line 2682 of file i915_reg.h.
#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) |
Definition at line 2678 of file i915_reg.h.
#define CURSOR_FORMAT_SHIFT 24 |
Definition at line 2677 of file i915_reg.h.
#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) |
Definition at line 2683 of file i915_reg.h.
#define CURSOR_GAMMA_ENABLE 0x40000000 |
Definition at line 2675 of file i915_reg.h.
#define CURSOR_MODE 0x27 |
Definition at line 2685 of file i915_reg.h.
#define CURSOR_MODE_64_32B_AX 0x07 |
Definition at line 2687 of file i915_reg.h.
#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) |
Definition at line 2688 of file i915_reg.h.
#define CURSOR_MODE_DISABLE 0x00 |
Definition at line 2686 of file i915_reg.h.
#define CURSOR_POS_MASK 0x007FF |
Definition at line 2695 of file i915_reg.h.
#define CURSOR_POS_SIGN 0x8000 |
Definition at line 2696 of file i915_reg.h.
#define CURSOR_STRIDE_MASK 0x30000000 |
Definition at line 2676 of file i915_reg.h.
#define CURSOR_X_SHIFT 0 |
Definition at line 2697 of file i915_reg.h.
#define CURSOR_Y_SHIFT 16 |
Definition at line 2698 of file i915_reg.h.
#define CURSORA_INVALID_GTT_INT_EN (1<<22) |
Definition at line 2473 of file i915_reg.h.
#define CURSORA_INVALID_GTT_STATUS (1<<6) |
Definition at line 2482 of file i915_reg.h.
#define CURSORB_INVALID_GTT_INT_EN (1<<23) |
Definition at line 2472 of file i915_reg.h.
#define CURSORB_INVALID_GTT_STATUS (1<<7) |
Definition at line 2481 of file i915_reg.h.
#define CXT_SIZE 0x21a0 |
Definition at line 1177 of file i915_reg.h.
#define D_STATE 0x6104 |
Definition at line 1034 of file i915_reg.h.
#define DAC_A_0_7_V (2 << 4) |
Definition at line 1795 of file i915_reg.h.
#define DAC_A_1_1_V (1 << 4) |
Definition at line 1794 of file i915_reg.h.
#define DAC_A_1_3_V (0 << 4) |
Definition at line 1793 of file i915_reg.h.
#define DAC_A_MASK (3 << 4) |
Definition at line 1796 of file i915_reg.h.
#define DAC_B_0_7_V (2 << 2) |
Definition at line 1799 of file i915_reg.h.
#define DAC_B_1_1_V (1 << 2) |
Definition at line 1798 of file i915_reg.h.
#define DAC_B_1_3_V (0 << 2) |
Definition at line 1797 of file i915_reg.h.
#define DAC_B_MASK (3 << 2) |
Definition at line 1800 of file i915_reg.h.
#define DAC_C_0_7_V (2 << 0) |
Definition at line 1803 of file i915_reg.h.
#define DAC_C_1_1_V (1 << 0) |
Definition at line 1802 of file i915_reg.h.
#define DAC_C_1_3_V (0 << 0) |
Definition at line 1801 of file i915_reg.h.
#define DAC_C_MASK (3 << 0) |
Definition at line 1804 of file i915_reg.h.
#define DAC_CTL_OVERRIDE (1 << 7) |
Overrides the ENC_ENABLE and DAC voltage levels.
Definition at line 1790 of file i915_reg.h.
#define DATA_LINK_M_N_MASK (0xffffff) |
Definition at line 3007 of file i915_reg.h.
#define DATA_LINK_N_MAX (0x800000) |
Definition at line 3008 of file i915_reg.h.
#define DCMP_CLOCK_GATE_DISABLE (1 << 3) |
Definition at line 1090 of file i915_reg.h.
#define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) |
Definition at line 1061 of file i915_reg.h.
#define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ |
Definition at line 1053 of file i915_reg.h.
#define DDI_A_4_LANES (1<<4) |
Definition at line 4246 of file i915_reg.h.
#define DDI_BUF_CTL | ( | port | ) | _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) |
Definition at line 4233 of file i915_reg.h.
#define DDI_BUF_CTL_A 0x64000 |
Definition at line 4231 of file i915_reg.h.
#define DDI_BUF_CTL_B 0x64100 |
Definition at line 4232 of file i915_reg.h.
#define DDI_BUF_CTL_ENABLE (1UL<<31) |
Definition at line 4234 of file i915_reg.h.
#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ |
Definition at line 4235 of file i915_reg.h.
#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ |
Definition at line 4236 of file i915_reg.h.
#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ |
Definition at line 4237 of file i915_reg.h.
#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ |
Definition at line 4238 of file i915_reg.h.
#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ |
Definition at line 4239 of file i915_reg.h.
#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ |
Definition at line 4240 of file i915_reg.h.
#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ |
Definition at line 4241 of file i915_reg.h.
#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ |
Definition at line 4242 of file i915_reg.h.
#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ |
Definition at line 4243 of file i915_reg.h.
#define DDI_BUF_EMP_MASK (0xf<<24) |
Definition at line 4244 of file i915_reg.h.
#define DDI_BUF_IS_IDLE (1<<7) |
Definition at line 4245 of file i915_reg.h.
#define DDI_BUF_TRANS | ( | port | ) | _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) |
Definition at line 4256 of file i915_reg.h.
#define DDI_BUF_TRANS_A 0x64E00 |
Definition at line 4254 of file i915_reg.h.
#define DDI_BUF_TRANS_B 0x64E60 |
Definition at line 4255 of file i915_reg.h.
#define DDI_INIT_DISPLAY_DETECTED (1<<0) |
Definition at line 4251 of file i915_reg.h.
Definition at line 4247 of file i915_reg.h.
#define DDI_PORT_WIDTH_X1 (0<<1) |
Definition at line 4248 of file i915_reg.h.
#define DDI_PORT_WIDTH_X2 (1<<1) |
Definition at line 4249 of file i915_reg.h.
#define DDI_PORT_WIDTH_X4 (3<<1) |
Definition at line 4250 of file i915_reg.h.
#define DDL_CURSORA_PRECISION_16 (0UL<<31) |
Definition at line 2525 of file i915_reg.h.
#define DDL_CURSORA_PRECISION_32 (1UL<<31) |
Definition at line 2524 of file i915_reg.h.
#define DDL_CURSORA_SHIFT 24 |
Definition at line 2526 of file i915_reg.h.
#define DDL_CURSORB_PRECISION_16 (0UL<<31) |
Definition at line 2531 of file i915_reg.h.
#define DDL_CURSORB_PRECISION_32 (1UL<<31) |
Definition at line 2530 of file i915_reg.h.
#define DDL_CURSORB_SHIFT 24 |
Definition at line 2532 of file i915_reg.h.
#define DDL_PLANEA_PRECISION_16 (0<<7) |
Definition at line 2528 of file i915_reg.h.
#define DDL_PLANEA_PRECISION_32 (1<<7) |
Definition at line 2527 of file i915_reg.h.
#define DDL_PLANEB_PRECISION_16 (0<<7) |
Definition at line 2534 of file i915_reg.h.
#define DDL_PLANEB_PRECISION_32 (1<<7) |
Definition at line 2533 of file i915_reg.h.
#define DE_AUX_CHANNEL_A (1 << 20) |
Definition at line 3095 of file i915_reg.h.
#define DE_AUX_CHANNEL_A_IVB (1<<26) |
Definition at line 3116 of file i915_reg.h.
#define DE_DP_A_HOTPLUG (1 << 19) |
Definition at line 3096 of file i915_reg.h.
#define DE_DP_A_HOTPLUG_IVB (1<<27) |
Definition at line 3115 of file i915_reg.h.
#define DE_ERR_DEBUG_IVB (1<<30) |
Definition at line 3112 of file i915_reg.h.
#define DE_GSE (1 << 18) |
Definition at line 3097 of file i915_reg.h.
#define DE_GSE_IVB (1<<29) |
Definition at line 3113 of file i915_reg.h.
#define DE_GTT_FAULT (1 << 24) |
Definition at line 3091 of file i915_reg.h.
#define DE_MASTER_IRQ_CONTROL (1UL << 31) |
Definition at line 3085 of file i915_reg.h.
#define DE_PCH_EVENT (1 << 21) |
Definition at line 3094 of file i915_reg.h.
#define DE_PCH_EVENT_IVB (1<<28) |
Definition at line 3114 of file i915_reg.h.
#define DE_PCU_EVENT (1 << 25) |
Definition at line 3090 of file i915_reg.h.
#define DE_PERFORM_COUNTER (1 << 22) |
Definition at line 3093 of file i915_reg.h.
#define DE_PIPEA_EVEN_FIELD (1 << 6) |
Definition at line 3105 of file i915_reg.h.
#define DE_PIPEA_FIFO_UNDERRUN (1 << 0) |
Definition at line 3109 of file i915_reg.h.
#define DE_PIPEA_LINE_COMPARE (1 << 4) |
Definition at line 3107 of file i915_reg.h.
#define DE_PIPEA_ODD_FIELD (1 << 5) |
Definition at line 3106 of file i915_reg.h.
#define DE_PIPEA_VBLANK (1 << 7) |
Definition at line 3104 of file i915_reg.h.
#define DE_PIPEA_VBLANK_IVB (1<<0) |
Definition at line 3125 of file i915_reg.h.
#define DE_PIPEA_VSYNC (1 << 3) |
Definition at line 3108 of file i915_reg.h.
#define DE_PIPEB_EVEN_FIELD (1 << 14) |
Definition at line 3099 of file i915_reg.h.
#define DE_PIPEB_FIFO_UNDERRUN (1 << 8) |
Definition at line 3103 of file i915_reg.h.
#define DE_PIPEB_LINE_COMPARE (1 << 12) |
Definition at line 3101 of file i915_reg.h.
#define DE_PIPEB_ODD_FIELD (1 << 13) |
Definition at line 3100 of file i915_reg.h.
#define DE_PIPEB_VBLANK (1 << 15) |
Definition at line 3098 of file i915_reg.h.
#define DE_PIPEB_VBLANK_IVB (1<<5) |
Definition at line 3122 of file i915_reg.h.
#define DE_PIPEB_VSYNC (1 << 11) |
Definition at line 3102 of file i915_reg.h.
#define DE_PIPEC_VBLANK_IVB (1<<10) |
Definition at line 3119 of file i915_reg.h.
#define DE_PLANEA_FLIP_DONE (1 << 26) |
Definition at line 3089 of file i915_reg.h.
#define DE_PLANEA_FLIP_DONE_IVB (1<<3) |
Definition at line 3124 of file i915_reg.h.
#define DE_PLANEB_FLIP_DONE (1 << 27) |
Definition at line 3088 of file i915_reg.h.
#define DE_PLANEB_FLIP_DONE_IVB (1<<8) |
Definition at line 3121 of file i915_reg.h.
#define DE_PLANEC_FLIP_DONE_IVB (1<<13) |
Definition at line 3118 of file i915_reg.h.
#define DE_POISON (1 << 23) |
Definition at line 3092 of file i915_reg.h.
#define DE_SPRITEA_FLIP_DONE (1 << 28) |
Definition at line 3087 of file i915_reg.h.
#define DE_SPRITEA_FLIP_DONE_IVB (1<<4) |
Definition at line 3123 of file i915_reg.h.
#define DE_SPRITEB_FLIP_DONE (1 << 29) |
Definition at line 3086 of file i915_reg.h.
#define DE_SPRITEB_FLIP_DONE_IVB (1<<9) |
Definition at line 3120 of file i915_reg.h.
#define DE_SPRITEC_FLIP_DONE_IVB (1<<14) |
Definition at line 3117 of file i915_reg.h.
#define DEBUG_RESET_DISPLAY (1<<9) |
Definition at line 304 of file i915_reg.h.
#define DEBUG_RESET_FULL (1<<7) |
Definition at line 302 of file i915_reg.h.
#define DEBUG_RESET_I830 0x6070 |
Definition at line 301 of file i915_reg.h.
#define DEBUG_RESET_RENDER (1<<8) |
Definition at line 303 of file i915_reg.h.
#define DEIER 0x4400c |
Definition at line 3133 of file i915_reg.h.
#define DEIIR 0x44008 |
Definition at line 3132 of file i915_reg.h.
#define DEIMR 0x44004 |
Definition at line 3131 of file i915_reg.h.
#define DEISR 0x44000 |
Definition at line 3130 of file i915_reg.h.
#define DERRMR 0x44050 |
Definition at line 481 of file i915_reg.h.
#define DEUC 0x6214 /* CRL only */ |
Definition at line 1147 of file i915_reg.h.
#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 |
Definition at line 2968 of file i915_reg.h.
#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) |
Definition at line 2969 of file i915_reg.h.
#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) |
Definition at line 2975 of file i915_reg.h.
#define DIGITAL_PORTA_NO_DETECT (0 << 0) |
Definition at line 2974 of file i915_reg.h.
#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) |
Definition at line 2973 of file i915_reg.h.
#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) |
Definition at line 2970 of file i915_reg.h.
#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) |
Definition at line 2971 of file i915_reg.h.
#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) |
Definition at line 2972 of file i915_reg.h.
#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) |
Definition at line 2976 of file i915_reg.h.
#define DIP_PORT_SEL_MASK 0x3 |
Definition at line 4135 of file i915_reg.h.
#define DISP_ARB_CTL 0x45000 |
Definition at line 3179 of file i915_reg.h.
#define DISP_BASEADDR_MASK (0xfffff000) |
Definition at line 2771 of file i915_reg.h.
#define DISP_FBC_WM_DIS (1<<15) |
Definition at line 3181 of file i915_reg.h.
#define DISP_TILE_SURFACE_SWIZZLING (1<<13) |
Definition at line 3180 of file i915_reg.h.
#define DISPLAY_PLANE_A (0<<20) |
Definition at line 278 of file i915_reg.h.
#define DISPLAY_PLANE_B (1<<20) |
Definition at line 279 of file i915_reg.h.
#define DISPLAY_PLANE_DISABLE 0 |
Definition at line 2719 of file i915_reg.h.
#define DISPLAY_PLANE_ENABLE (1UL<<31) |
Definition at line 2718 of file i915_reg.h.
#define DISPLAY_PORT_PLL_BIOS_0 0x4600c |
Definition at line 2987 of file i915_reg.h.
#define DISPLAY_PORT_PLL_BIOS_1 0x46010 |
Definition at line 2988 of file i915_reg.h.
#define DISPLAY_PORT_PLL_BIOS_2 0x46014 |
Definition at line 2989 of file i915_reg.h.
#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) |
Definition at line 962 of file i915_reg.h.
#define DISPPLANE_8BPP (0x2<<26) |
Definition at line 2724 of file i915_reg.h.
#define DISPPLANE_ALPHA_TRANS_DISABLE 0 |
Definition at line 2804 of file i915_reg.h.
#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) |
Definition at line 2803 of file i915_reg.h.
#define DISPPLANE_BGRA555 (0x3<<26) |
Definition at line 2725 of file i915_reg.h.
#define DISPPLANE_BGRA888 (0x7<<26) |
Definition at line 2729 of file i915_reg.h.
#define DISPPLANE_BGRX101010 (0xa<<26) |
Definition at line 2732 of file i915_reg.h.
#define DISPPLANE_BGRX555 (0x4<<26) |
Definition at line 2726 of file i915_reg.h.
#define DISPPLANE_BGRX565 (0x5<<26) |
Definition at line 2727 of file i915_reg.h.
#define DISPPLANE_BGRX888 (0x6<<26) |
Definition at line 2728 of file i915_reg.h.
#define DISPPLANE_GAMMA_DISABLE 0 |
Definition at line 2721 of file i915_reg.h.
#define DISPPLANE_GAMMA_ENABLE (1<<30) |
Definition at line 2720 of file i915_reg.h.
#define DISPPLANE_LINE_DOUBLE (1<<20) |
Definition at line 2744 of file i915_reg.h.
#define DISPPLANE_NO_LINE_DOUBLE 0 |
Definition at line 2745 of file i915_reg.h.
#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) |
Definition at line 2722 of file i915_reg.h.
#define DISPPLANE_RGBA101010 (0x9<<26) |
Definition at line 2731 of file i915_reg.h.
#define DISPPLANE_RGBA888 (0xf<<26) |
Definition at line 2735 of file i915_reg.h.
#define DISPPLANE_RGBX101010 (0x8<<26) |
Definition at line 2730 of file i915_reg.h.
#define DISPPLANE_RGBX161616 (0xc<<26) |
Definition at line 2733 of file i915_reg.h.
#define DISPPLANE_RGBX888 (0xe<<26) |
Definition at line 2734 of file i915_reg.h.
#define DISPPLANE_SEL_PIPE_A 0 |
Definition at line 2740 of file i915_reg.h.
#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) |
Definition at line 2741 of file i915_reg.h.
#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) |
Definition at line 2739 of file i915_reg.h.
#define DISPPLANE_SEL_PIPE_SHIFT 24 |
Definition at line 2738 of file i915_reg.h.
#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 |
Definition at line 2805 of file i915_reg.h.
#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) |
Definition at line 2806 of file i915_reg.h.
#define DISPPLANE_SRC_KEY_DISABLE 0 |
Definition at line 2743 of file i915_reg.h.
#define DISPPLANE_SRC_KEY_ENABLE (1<<22) |
Definition at line 2742 of file i915_reg.h.
#define DISPPLANE_STEREO_DISABLE 0 |
Definition at line 2737 of file i915_reg.h.
#define DISPPLANE_STEREO_ENABLE (1<<25) |
Definition at line 2736 of file i915_reg.h.
#define DISPPLANE_STEREO_POLARITY_FIRST 0 |
Definition at line 2746 of file i915_reg.h.
#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) |
Definition at line 2747 of file i915_reg.h.
#define DISPPLANE_TILED (1<<10) |
Definition at line 2749 of file i915_reg.h.
#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ |
Definition at line 2748 of file i915_reg.h.
#define DISPPLANE_YUV422 (0x0<<26) |
Definition at line 2723 of file i915_reg.h.
#define DMA_FADD_I8XX 0x020d0 |
Definition at line 475 of file i915_reg.h.
#define DONE_REG 0x40b0 |
Definition at line 426 of file i915_reg.h.
#define DOP_CLOCK_GATING_DISABLE (1<<0) |
Definition at line 4041 of file i915_reg.h.
#define DOVSTA 0x30008 |
Definition at line 1214 of file i915_reg.h.
#define DP_A 0x64000 /* eDP */ |
Definition at line 2174 of file i915_reg.h.
#define DP_AUDIO_OUTPUT_ENABLE (1 << 6) |
Turn on the audio link.
Definition at line 2247 of file i915_reg.h.
#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) |
Definition at line 2303 of file i915_reg.h.
#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) |
Definition at line 2308 of file i915_reg.h.
#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 |
Definition at line 2309 of file i915_reg.h.
#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) |
Definition at line 2306 of file i915_reg.h.
#define DP_AUX_CH_CTL_DONE (1 << 30) |
Definition at line 2290 of file i915_reg.h.
#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) |
Definition at line 2291 of file i915_reg.h.
#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) |
Definition at line 2304 of file i915_reg.h.
#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) |
Definition at line 2299 of file i915_reg.h.
#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 |
Definition at line 2300 of file i915_reg.h.
#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) |
Definition at line 2301 of file i915_reg.h.
#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 |
Definition at line 2302 of file i915_reg.h.
#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) |
Definition at line 2307 of file i915_reg.h.
#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) |
Definition at line 2298 of file i915_reg.h.
#define DP_AUX_CH_CTL_SEND_BUSY (1UL << 31) |
Definition at line 2289 of file i915_reg.h.
#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) |
Definition at line 2305 of file i915_reg.h.
#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) |
Definition at line 2296 of file i915_reg.h.
#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) |
Definition at line 2293 of file i915_reg.h.
#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) |
Definition at line 2294 of file i915_reg.h.
#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) |
Definition at line 2295 of file i915_reg.h.
#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) |
Definition at line 2292 of file i915_reg.h.
#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) |
Definition at line 2297 of file i915_reg.h.
#define DP_B 0x64100 |
Definition at line 2175 of file i915_reg.h.
#define DP_C 0x64200 |
Definition at line 2176 of file i915_reg.h.
#define DP_CLOCK_OUTPUT_ENABLE (1 << 13) |
sends the clock on lane 15 of the PEG for debug
Definition at line 2238 of file i915_reg.h.
#define DP_COLOR_RANGE_16_235 (1 << 8) |
limit RGB values to avoid confusing TVs
Definition at line 2244 of file i915_reg.h.
#define DP_D 0x64300 |
Definition at line 2177 of file i915_reg.h.
#define DP_DETECTED (1 << 2) |
A fantasy.
Definition at line 2254 of file i915_reg.h.
#define DP_ENHANCED_FRAMING (1 << 18) |
Definition at line 2224 of file i915_reg.h.
#define DP_LINK_TRAIN_MASK (3 << 28) |
Definition at line 2188 of file i915_reg.h.
#define DP_LINK_TRAIN_MASK_CPT (7 << 8) |
Definition at line 2196 of file i915_reg.h.
#define DP_LINK_TRAIN_OFF (3 << 28) |
Definition at line 2187 of file i915_reg.h.
#define DP_LINK_TRAIN_OFF_CPT (3 << 8) |
Definition at line 2195 of file i915_reg.h.
#define DP_LINK_TRAIN_PAT_1 (0 << 28) |
Definition at line 2184 of file i915_reg.h.
#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) |
Definition at line 2192 of file i915_reg.h.
#define DP_LINK_TRAIN_PAT_2 (1 << 28) |
Definition at line 2185 of file i915_reg.h.
#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) |
Definition at line 2193 of file i915_reg.h.
#define DP_LINK_TRAIN_PAT_IDLE (2 << 28) |
Definition at line 2186 of file i915_reg.h.
#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) |
Definition at line 2194 of file i915_reg.h.
#define DP_LINK_TRAIN_SHIFT 28 |
Definition at line 2189 of file i915_reg.h.
#define DP_LINK_TRAIN_SHIFT_CPT 8 |
Definition at line 2197 of file i915_reg.h.
#define DP_PIPE_MASK (1 << 30) |
Definition at line 2181 of file i915_reg.h.
#define DP_PIPEB_SELECT (1 << 30) |
Definition at line 2180 of file i915_reg.h.
#define DP_PLL_ENABLE (1 << 14) |
Definition at line 2235 of file i915_reg.h.
#define DP_PLL_FREQ_160MHZ (1 << 16) |
Definition at line 2228 of file i915_reg.h.
#define DP_PLL_FREQ_270MHZ (0 << 16) |
Definition at line 2227 of file i915_reg.h.
#define DP_PLL_FREQ_MASK (3 << 16) |
Definition at line 2229 of file i915_reg.h.
#define DP_PORT_EN (1UL << 31) |
Definition at line 2179 of file i915_reg.h.
#define DP_PORT_REVERSAL (1 << 15) |
locked once port is enabled
Definition at line 2232 of file i915_reg.h.
#define DP_PORT_WIDTH_1 (0 << 19) |
Definition at line 2218 of file i915_reg.h.
#define DP_PORT_WIDTH_2 (1 << 19) |
Definition at line 2219 of file i915_reg.h.
#define DP_PORT_WIDTH_4 (3 << 19) |
Definition at line 2220 of file i915_reg.h.
#define DP_PORT_WIDTH_MASK (7 << 19) |
Definition at line 2221 of file i915_reg.h.
#define DP_PRE_EMPHASIS_0 (0 << 22) |
Definition at line 2210 of file i915_reg.h.
#define DP_PRE_EMPHASIS_3_5 (1 << 22) |
Definition at line 2211 of file i915_reg.h.
#define DP_PRE_EMPHASIS_6 (2 << 22) |
Definition at line 2212 of file i915_reg.h.
#define DP_PRE_EMPHASIS_9_5 (3 << 22) |
Definition at line 2213 of file i915_reg.h.
#define DP_PRE_EMPHASIS_MASK (7 << 22) |
Definition at line 2214 of file i915_reg.h.
#define DP_PRE_EMPHASIS_SHIFT 22 |
Definition at line 2215 of file i915_reg.h.
#define DP_SCRAMBLING_DISABLE (1 << 12) |
Definition at line 2240 of file i915_reg.h.
#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) |
Definition at line 2241 of file i915_reg.h.
#define DP_SYNC_HS_HIGH (1 << 3) |
Definition at line 2251 of file i915_reg.h.
#define DP_SYNC_VS_HIGH (1 << 4) |
vs and hs sync polarity
Definition at line 2250 of file i915_reg.h.
#define DP_TP_CTL | ( | port | ) | _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) |
Definition at line 4209 of file i915_reg.h.
#define DP_TP_CTL_A 0x64040 |
Definition at line 4207 of file i915_reg.h.
#define DP_TP_CTL_B 0x64140 |
Definition at line 4208 of file i915_reg.h.
#define DP_TP_CTL_ENABLE (1UL<<31) |
Definition at line 4210 of file i915_reg.h.
#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) |
Definition at line 4213 of file i915_reg.h.
#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) |
Definition at line 4214 of file i915_reg.h.
#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) |
Definition at line 4219 of file i915_reg.h.
#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) |
Definition at line 4215 of file i915_reg.h.
#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) |
Definition at line 4220 of file i915_reg.h.
#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) |
Definition at line 4216 of file i915_reg.h.
#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) |
Definition at line 4217 of file i915_reg.h.
#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) |
Definition at line 4218 of file i915_reg.h.
#define DP_TP_CTL_MODE_MST (1<<27) |
Definition at line 4212 of file i915_reg.h.
#define DP_TP_CTL_MODE_SST (0<<27) |
Definition at line 4211 of file i915_reg.h.
#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) |
Definition at line 4221 of file i915_reg.h.
#define DP_TP_STATUS | ( | port | ) | _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) |
Definition at line 4226 of file i915_reg.h.
#define DP_TP_STATUS_A 0x64044 |
Definition at line 4224 of file i915_reg.h.
#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) |
Definition at line 4228 of file i915_reg.h.
#define DP_TP_STATUS_B 0x64144 |
Definition at line 4225 of file i915_reg.h.
#define DP_TP_STATUS_IDLE_DONE (1<<25) |
Definition at line 4227 of file i915_reg.h.
#define DP_VOLTAGE_0_4 (0 << 25) |
Definition at line 2200 of file i915_reg.h.
#define DP_VOLTAGE_0_6 (1 << 25) |
Definition at line 2201 of file i915_reg.h.
#define DP_VOLTAGE_0_8 (2 << 25) |
Definition at line 2202 of file i915_reg.h.
#define DP_VOLTAGE_1_2 (3 << 25) |
Definition at line 2203 of file i915_reg.h.
#define DP_VOLTAGE_MASK (7 << 25) |
Definition at line 2204 of file i915_reg.h.
#define DP_VOLTAGE_SHIFT 25 |
Definition at line 2205 of file i915_reg.h.
#define DPA_AUX_CH_CTL 0x64010 |
The aux channel provides a way to talk to the signal sink for DDC etc.
Max packet size supported is 20 bytes in each direction, hence the 5 fixed data registers
Definition at line 2261 of file i915_reg.h.
#define DPA_AUX_CH_DATA1 0x64014 |
Definition at line 2262 of file i915_reg.h.
#define DPA_AUX_CH_DATA2 0x64018 |
Definition at line 2263 of file i915_reg.h.
#define DPA_AUX_CH_DATA3 0x6401c |
Definition at line 2264 of file i915_reg.h.
#define DPA_AUX_CH_DATA4 0x64020 |
Definition at line 2265 of file i915_reg.h.
#define DPA_AUX_CH_DATA5 0x64024 |
Definition at line 2266 of file i915_reg.h.
#define DPB_AUX_CH_CTL 0x64110 |
Definition at line 2268 of file i915_reg.h.
#define DPB_AUX_CH_DATA1 0x64114 |
Definition at line 2269 of file i915_reg.h.
#define DPB_AUX_CH_DATA2 0x64118 |
Definition at line 2270 of file i915_reg.h.
#define DPB_AUX_CH_DATA3 0x6411c |
Definition at line 2271 of file i915_reg.h.
#define DPB_AUX_CH_DATA4 0x64120 |
Definition at line 2272 of file i915_reg.h.
#define DPB_AUX_CH_DATA5 0x64124 |
Definition at line 2273 of file i915_reg.h.
#define DPB_HOTPLUG_INT_EN (1 << 29) |
Definition at line 1308 of file i915_reg.h.
#define DPB_HOTPLUG_INT_STATUS (3 << 17) |
Definition at line 1340 of file i915_reg.h.
#define DPB_HOTPLUG_LIVE_STATUS (1 << 29) |
Definition at line 1335 of file i915_reg.h.
#define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ |
Definition at line 1056 of file i915_reg.h.
#define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) |
Definition at line 1060 of file i915_reg.h.
#define DPC_AUX_CH_CTL 0x64210 |
Definition at line 2275 of file i915_reg.h.
#define DPC_AUX_CH_DATA1 0x64214 |
Definition at line 2276 of file i915_reg.h.
#define DPC_AUX_CH_DATA2 0x64218 |
Definition at line 2277 of file i915_reg.h.
#define DPC_AUX_CH_DATA3 0x6421c |
Definition at line 2278 of file i915_reg.h.
#define DPC_AUX_CH_DATA4 0x64220 |
Definition at line 2279 of file i915_reg.h.
#define DPC_AUX_CH_DATA5 0x64224 |
Definition at line 2280 of file i915_reg.h.
#define DPC_HOTPLUG_INT_EN (1 << 28) |
Definition at line 1310 of file i915_reg.h.
#define DPC_HOTPLUG_INT_STATUS (3 << 19) |
Definition at line 1339 of file i915_reg.h.
#define DPC_HOTPLUG_LIVE_STATUS (1 << 28) |
Definition at line 1336 of file i915_reg.h.
#define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ |
Definition at line 1046 of file i915_reg.h.
#define DPD_AUX_CH_CTL 0x64310 |
Definition at line 2282 of file i915_reg.h.
#define DPD_AUX_CH_DATA1 0x64314 |
Definition at line 2283 of file i915_reg.h.
#define DPD_AUX_CH_DATA2 0x64318 |
Definition at line 2284 of file i915_reg.h.
#define DPD_AUX_CH_DATA3 0x6431c |
Definition at line 2285 of file i915_reg.h.
#define DPD_AUX_CH_DATA4 0x64320 |
Definition at line 2286 of file i915_reg.h.
#define DPD_AUX_CH_DATA5 0x64324 |
Definition at line 2287 of file i915_reg.h.
#define DPD_HOTPLUG_INT_EN (1 << 27) |
Definition at line 1312 of file i915_reg.h.
#define DPD_HOTPLUG_INT_STATUS (3 << 21) |
Definition at line 1338 of file i915_reg.h.
#define DPD_HOTPLUG_LIVE_STATUS (1 << 27) |
Definition at line 1337 of file i915_reg.h.
#define DPFC_CB_BASE 0x3200 |
Definition at line 746 of file i915_reg.h.
#define DPFC_CHICKEN 0x3224 |
Definition at line 770 of file i915_reg.h.
#define DPFC_COMP_SEG_MASK (0x000003ff) |
Definition at line 767 of file i915_reg.h.
#define DPFC_COMP_SEG_SHIFT (0) |
Definition at line 766 of file i915_reg.h.
#define DPFC_CONTROL 0x3208 |
Definition at line 747 of file i915_reg.h.
#define DPFC_CPU_FENCE_OFFSET 0x100104 |
Definition at line 796 of file i915_reg.h.
#define DPFC_CTL_EN (1UL<<31) |
Definition at line 748 of file i915_reg.h.
#define DPFC_CTL_FENCE_EN (1<<29) |
Definition at line 751 of file i915_reg.h.
#define DPFC_CTL_LIMIT_1X (0<<6) |
Definition at line 754 of file i915_reg.h.
#define DPFC_CTL_LIMIT_2X (1<<6) |
Definition at line 755 of file i915_reg.h.
#define DPFC_CTL_LIMIT_4X (2<<6) |
Definition at line 756 of file i915_reg.h.
#define DPFC_CTL_PERSISTENT_MODE (1<<25) |
Definition at line 752 of file i915_reg.h.
#define DPFC_CTL_PLANEA (0<<30) |
Definition at line 749 of file i915_reg.h.
#define DPFC_CTL_PLANEB (1<<30) |
Definition at line 750 of file i915_reg.h.
#define DPFC_FENCE_YOFF 0x3218 |
Definition at line 769 of file i915_reg.h.
#define DPFC_HT_MODIFY (1UL<<31) |
Definition at line 771 of file i915_reg.h.
#define DPFC_INVAL_SEG_MASK (0x07ff0000) |
Definition at line 765 of file i915_reg.h.
#define DPFC_INVAL_SEG_SHIFT (16) |
Definition at line 764 of file i915_reg.h.
#define DPFC_RECOMP_CTL 0x320c |
Definition at line 757 of file i915_reg.h.
#define DPFC_RECOMP_STALL_EN (1<<27) |
Definition at line 758 of file i915_reg.h.
#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) |
Definition at line 760 of file i915_reg.h.
#define DPFC_RECOMP_STALL_WM_SHIFT (16) |
Definition at line 759 of file i915_reg.h.
#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) |
Definition at line 762 of file i915_reg.h.
#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) |
Definition at line 761 of file i915_reg.h.
#define DPFC_RESERVED (0x1FFFFF00) |
Definition at line 777 of file i915_reg.h.
#define DPFC_SR_EN (1<<10) |
Definition at line 753 of file i915_reg.h.
#define DPFC_STATUS 0x3210 |
Definition at line 763 of file i915_reg.h.
#define DPFC_STATUS2 0x3214 |
Definition at line 768 of file i915_reg.h.
#define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ |
Definition at line 1055 of file i915_reg.h.
#define DPINVGTT 0x7002c /* VLV only */ |
Definition at line 2471 of file i915_reg.h.
#define DPINVGTT_EN_MASK 0xff0000 |
Definition at line 2480 of file i915_reg.h.
#define DPINVGTT_STATUS_MASK 0xff |
Definition at line 2489 of file i915_reg.h.
#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ |
Definition at line 345 of file i915_reg.h.
#define DPIO_BUSY (1<<0) /* status only */ |
Definition at line 321 of file i915_reg.h.
#define DPIO_BYTE (0xf<<4) |
Definition at line 320 of file i915_reg.h.
#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ |
Definition at line 349 of file i915_reg.h.
#define DPIO_CORE_CLK | ( | pipe | ) | _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B) |
Definition at line 355 of file i915_reg.h.
#define DPIO_CTL 0x2110 |
Definition at line 324 of file i915_reg.h.
#define DPIO_DATA 0x2104 |
Definition at line 322 of file i915_reg.h.
#define DPIO_DATA_CHANNEL1 0x8220 |
Definition at line 363 of file i915_reg.h.
#define DPIO_DATA_CHANNEL2 0x8420 |
Definition at line 364 of file i915_reg.h.
#define DPIO_DIV | ( | pipe | ) | _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B) |
Definition at line 340 of file i915_reg.h.
#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ |
Definition at line 348 of file i915_reg.h.
#define DPIO_ENABLE_CALIBRATION (1<<11) |
Definition at line 336 of file i915_reg.h.
#define DPIO_FASTCLK_DISABLE 0x8100 |
Definition at line 361 of file i915_reg.h.
#define DPIO_K_SHIFT (24) /* 4 bits */ |
Definition at line 332 of file i915_reg.h.
#define DPIO_LFP_COEFF | ( | pipe | ) | _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B) |
Definition at line 359 of file i915_reg.h.
#define DPIO_M1DIV_SHIFT (8) /* 3 bits */ |
Definition at line 337 of file i915_reg.h.
#define DPIO_M2DIV_MASK 0xff |
Definition at line 338 of file i915_reg.h.
#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ |
Definition at line 326 of file i915_reg.h.
#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ |
Definition at line 325 of file i915_reg.h.
#define DPIO_N_SHIFT (12) /* 4 bits */ |
Definition at line 335 of file i915_reg.h.
#define DPIO_OP_READ (0<<16) |
Definition at line 318 of file i915_reg.h.
#define DPIO_OP_WRITE (1<<16) |
Definition at line 317 of file i915_reg.h.
#define DPIO_P1_SHIFT (21) /* 3 bits */ |
Definition at line 333 of file i915_reg.h.
#define DPIO_P2_SHIFT (16) /* 5 bits */ |
Definition at line 334 of file i915_reg.h.
#define DPIO_PKT 0x2100 |
Definition at line 315 of file i915_reg.h.
#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ |
Definition at line 344 of file i915_reg.h.
#define DPIO_PLL_REFCLK_SEL_MASK 3 |
Definition at line 347 of file i915_reg.h.
#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ |
Definition at line 346 of file i915_reg.h.
#define DPIO_PORTID (0x12<<8) |
Definition at line 319 of file i915_reg.h.
#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ |
Definition at line 331 of file i915_reg.h.
#define DPIO_REFSEL_OVERRIDE 27 |
Definition at line 343 of file i915_reg.h.
#define DPIO_REFSFR | ( | pipe | ) | _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B) |
Definition at line 351 of file i915_reg.h.
#define DPIO_REG 0x2108 |
Definition at line 323 of file i915_reg.h.
#define DPIO_RESET (1<<0) |
Definition at line 328 of file i915_reg.h.
#define DPIO_RID (0<<24) |
Definition at line 316 of file i915_reg.h.
#define DPIO_SFR_BYPASS (1<<1) |
Definition at line 327 of file i915_reg.h.
#define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ |
Definition at line 1065 of file i915_reg.h.
#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ |
Definition at line 899 of file i915_reg.h.
#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ |
Definition at line 900 of file i915_reg.h.
#define DPLL_DVO_HIGH_SPEED (1 << 30) |
Definition at line 891 of file i915_reg.h.
#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) |
Definition at line 892 of file i915_reg.h.
#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
Definition at line 904 of file i915_reg.h.
#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 |
Definition at line 931 of file i915_reg.h.
#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 |
Definition at line 936 of file i915_reg.h.
#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
Definition at line 905 of file i915_reg.h.
#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 |
Definition at line 937 of file i915_reg.h.
#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 |
Definition at line 938 of file i915_reg.h.
#define DPLL_FPA1_P1_POST_DIV_MASK 0xff |
Definition at line 953 of file i915_reg.h.
#define DPLL_FPA1_P1_POST_DIV_SHIFT 0 |
Definition at line 952 of file i915_reg.h.
#define DPLL_INTEGRATED_CLOCK_VLV (1<<13) |
Definition at line 907 of file i915_reg.h.
#define DPLL_LOCK_VLV (1<<15) |
Definition at line 906 of file i915_reg.h.
#define DPLL_MD | ( | pipe | ) | _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) |
Definition at line 1007 of file i915_reg.h.
#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 |
Definition at line 975 of file i915_reg.h.
#define DPLL_MD_UDI_DIVIDER_SHIFT 24 |
Definition at line 976 of file i915_reg.h.
#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 |
Definition at line 997 of file i915_reg.h.
#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 |
Definition at line 998 of file i915_reg.h.
#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 |
Definition at line 978 of file i915_reg.h.
#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 |
Definition at line 979 of file i915_reg.h.
#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f |
Definition at line 1004 of file i915_reg.h.
#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 |
Definition at line 1005 of file i915_reg.h.
#define DPLL_MODE_MASK (3 << 26) |
Definition at line 898 of file i915_reg.h.
#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ |
Definition at line 903 of file i915_reg.h.
#define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) |
Definition at line 894 of file i915_reg.h.
#define DPLL_SYNCLOCK_ENABLE (1 << 29) |
Definition at line 893 of file i915_reg.h.
#define DPLL_TEST 0x606c |
Definition at line 1023 of file i915_reg.h.
#define DPLL_VCO_ENABLE (1UL << 31) |
Definition at line 890 of file i915_reg.h.
#define DPLL_VGA_MODE_DIS (1 << 28) |
Definition at line 895 of file i915_reg.h.
#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) |
Definition at line 1033 of file i915_reg.h.
#define DPLLA_TEST_M_BYPASS (1 << 2) |
Definition at line 1032 of file i915_reg.h.
#define DPLLA_TEST_N_BYPASS (1 << 3) |
Definition at line 1031 of file i915_reg.h.
#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) |
Definition at line 1030 of file i915_reg.h.
#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ |
Definition at line 901 of file i915_reg.h.
#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ |
Definition at line 902 of file i915_reg.h.
#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ |
Definition at line 896 of file i915_reg.h.
#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ |
Definition at line 897 of file i915_reg.h.
#define DPLLB_TEST_M_BYPASS (1 << 18) |
Definition at line 1029 of file i915_reg.h.
#define DPLLB_TEST_N_BYPASS (1 << 19) |
Definition at line 1028 of file i915_reg.h.
#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) |
Definition at line 1024 of file i915_reg.h.
#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) |
Definition at line 1025 of file i915_reg.h.
#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) |
Definition at line 1026 of file i915_reg.h.
#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) |
Definition at line 1027 of file i915_reg.h.
#define DPLS_EDP_PPS_FIX_DIS (1<<0) |
Definition at line 3566 of file i915_reg.h.
#define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ |
Definition at line 1057 of file i915_reg.h.
#define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ |
Definition at line 1058 of file i915_reg.h.
#define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) |
Definition at line 1059 of file i915_reg.h.
#define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ |
Definition at line 1054 of file i915_reg.h.
#define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ |
Definition at line 1045 of file i915_reg.h.
#define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ |
Definition at line 1040 of file i915_reg.h.
#define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) |
Definition at line 1062 of file i915_reg.h.
#define DRAIN_LATENCY_PRECISION_16 16 |
Definition at line 2522 of file i915_reg.h.
#define DRAIN_LATENCY_PRECISION_32 32 |
Definition at line 2521 of file i915_reg.h.
#define DREF_CONTROL_MASK 0x7fc3 |
Definition at line 3345 of file i915_reg.h.
#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) |
Definition at line 3346 of file i915_reg.h.
#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) |
Definition at line 3347 of file i915_reg.h.
#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) |
Definition at line 3349 of file i915_reg.h.
#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) |
Definition at line 3348 of file i915_reg.h.
#define DREF_NONSPREAD_CK505_ENABLE (1<<9) |
Definition at line 3354 of file i915_reg.h.
#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) |
Definition at line 3353 of file i915_reg.h.
#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) |
Definition at line 3355 of file i915_reg.h.
#define DREF_NONSPREAD_SOURCE_MASK (3<<9) |
Definition at line 3356 of file i915_reg.h.
#define DREF_SSC1_DISABLE (0<<1) |
Definition at line 3362 of file i915_reg.h.
#define DREF_SSC1_ENABLE (1<<1) |
Definition at line 3363 of file i915_reg.h.
#define DREF_SSC4_CENTERSPREAD (1<<6) |
Definition at line 3361 of file i915_reg.h.
#define DREF_SSC4_DISABLE (0) |
Definition at line 3364 of file i915_reg.h.
#define DREF_SSC4_DOWNSPREAD (0<<6) |
Definition at line 3360 of file i915_reg.h.
#define DREF_SSC4_ENABLE (1) |
Definition at line 3365 of file i915_reg.h.
#define DREF_SSC_SOURCE_DISABLE (0<<11) |
Definition at line 3350 of file i915_reg.h.
#define DREF_SSC_SOURCE_ENABLE (2<<11) |
Definition at line 3351 of file i915_reg.h.
#define DREF_SSC_SOURCE_MASK (3<<11) |
Definition at line 3352 of file i915_reg.h.
#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) |
Definition at line 3357 of file i915_reg.h.
#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) |
Definition at line 3358 of file i915_reg.h.
#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) |
Definition at line 3359 of file i915_reg.h.
#define DSL_LINEMASK_GEN2 0x00000fff |
Definition at line 2365 of file i915_reg.h.
#define DSL_LINEMASK_GEN3 0x00001fff |
Definition at line 2366 of file i915_reg.h.
Definition at line 2760 of file i915_reg.h.
#define DSPARB 0x70030 |
Definition at line 2491 of file i915_reg.h.
#define DSPARB_AEND_SHIFT 0 |
Definition at line 2497 of file i915_reg.h.
#define DSPARB_BEND_SHIFT 9 /* on 855 */ |
Definition at line 2496 of file i915_reg.h.
#define DSPARB_BSTART_MASK (0x7f) |
Definition at line 2494 of file i915_reg.h.
#define DSPARB_BSTART_SHIFT 0 |
Definition at line 2495 of file i915_reg.h.
#define DSPARB_CSTART_MASK (0x7f << 7) |
Definition at line 2492 of file i915_reg.h.
#define DSPARB_CSTART_SHIFT 7 |
Definition at line 2493 of file i915_reg.h.
#define DSPCLK_GATE_D 0x6200 |
Definition at line 1039 of file i915_reg.h.
Definition at line 2759 of file i915_reg.h.
#define DSPFW1 0x70034 |
Definition at line 2499 of file i915_reg.h.
#define DSPFW2 0x70038 |
Definition at line 2507 of file i915_reg.h.
#define DSPFW3 0x7003c |
Definition at line 2511 of file i915_reg.h.
#define DSPFW_CURSOR_SR_MASK (0x3f<<24) |
Definition at line 2515 of file i915_reg.h.
#define DSPFW_CURSOR_SR_SHIFT 24 |
Definition at line 2513 of file i915_reg.h.
#define DSPFW_CURSORA_MASK 0x00003f00 |
Definition at line 2508 of file i915_reg.h.
#define DSPFW_CURSORA_SHIFT 8 |
Definition at line 2509 of file i915_reg.h.
#define DSPFW_CURSORB_MASK (0x3f<<16) |
Definition at line 2503 of file i915_reg.h.
#define DSPFW_CURSORB_SHIFT 16 |
Definition at line 2502 of file i915_reg.h.
#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) |
Definition at line 2517 of file i915_reg.h.
#define DSPFW_HPLL_CURSOR_SHIFT 16 |
Definition at line 2516 of file i915_reg.h.
#define DSPFW_HPLL_SR_EN (1UL<<31) |
Definition at line 2512 of file i915_reg.h.
#define DSPFW_HPLL_SR_MASK (0x1ff) |
Definition at line 2518 of file i915_reg.h.
#define DSPFW_PLANEA_MASK (0x7f) |
Definition at line 2506 of file i915_reg.h.
#define DSPFW_PLANEB_MASK (0x7f<<8) |
Definition at line 2505 of file i915_reg.h.
#define DSPFW_PLANEB_SHIFT 8 |
Definition at line 2504 of file i915_reg.h.
#define DSPFW_PLANEC_MASK (0x7f) |
Definition at line 2510 of file i915_reg.h.
#define DSPFW_SR_MASK (0x1ff<<23) |
Definition at line 2501 of file i915_reg.h.
#define DSPFW_SR_SHIFT 23 |
Definition at line 2500 of file i915_reg.h.
Definition at line 2766 of file i915_reg.h.
#define DSPOFFSET | ( | plane | ) | _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET) |
Definition at line 2767 of file i915_reg.h.
Definition at line 2762 of file i915_reg.h.
Definition at line 2763 of file i915_reg.h.
#define DSPSTRIDE | ( | plane | ) | _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) |
Definition at line 2761 of file i915_reg.h.
Definition at line 2764 of file i915_reg.h.
#define DSPSURFLIVE | ( | plane | ) | _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE) |
Definition at line 2768 of file i915_reg.h.
#define DSPTILEOFF | ( | plane | ) | _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) |
Definition at line 2765 of file i915_reg.h.
#define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ |
Definition at line 1052 of file i915_reg.h.
#define DSTATE_DOT_CLOCK_GATING (1<<0) |
Definition at line 1038 of file i915_reg.h.
#define DSTATE_GFX_CLOCK_GATING (1<<1) |
Definition at line 1037 of file i915_reg.h.
#define DSTATE_GFX_RESET_I830 (1<<6) |
Definition at line 1035 of file i915_reg.h.
#define DSTATE_PLL_D3_OFF (1<<3) |
Definition at line 1036 of file i915_reg.h.
#define DVI_MODE_SELECT (0) |
Definition at line 3719 of file i915_reg.h.
#define DVO_BLANK_ACTIVE_HIGH (1 << 2) |
Definition at line 1424 of file i915_reg.h.
#define DVO_BORDER_ENABLE (1 << 7) |
Definition at line 1417 of file i915_reg.h.
#define DVO_DATA_ORDER_FP (1 << 14) |
Definition at line 1412 of file i915_reg.h.
#define DVO_DATA_ORDER_GBRG (1 << 6) |
Definition at line 1418 of file i915_reg.h.
#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) |
Definition at line 1420 of file i915_reg.h.
#define DVO_DATA_ORDER_I740 (0 << 14) |
Definition at line 1411 of file i915_reg.h.
#define DVO_DATA_ORDER_RGGB (0 << 6) |
Definition at line 1419 of file i915_reg.h.
#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) |
Definition at line 1421 of file i915_reg.h.
#define DVO_ENABLE (1UL << 31) |
Definition at line 1404 of file i915_reg.h.
#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) |
Definition at line 1423 of file i915_reg.h.
#define DVO_HSYNC_DISABLE (1 << 10) |
Definition at line 1414 of file i915_reg.h.
#define DVO_HSYNC_TRISTATE (1 << 8) |
Definition at line 1416 of file i915_reg.h.
#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ |
Definition at line 1425 of file i915_reg.h.
#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ |
Definition at line 1426 of file i915_reg.h.
#define DVO_PIPE_B_SELECT (1 << 30) |
Definition at line 1405 of file i915_reg.h.
#define DVO_PIPE_STALL (1 << 28) |
Definition at line 1407 of file i915_reg.h.
#define DVO_PIPE_STALL_MASK (3 << 28) |
Definition at line 1409 of file i915_reg.h.
#define DVO_PIPE_STALL_TV (2 << 28) |
Definition at line 1408 of file i915_reg.h.
#define DVO_PIPE_STALL_UNUSED (0 << 28) |
Definition at line 1406 of file i915_reg.h.
#define DVO_PRESERVE_MASK (0x7<<24) |
Definition at line 1427 of file i915_reg.h.
#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 |
Definition at line 1431 of file i915_reg.h.
#define DVO_SRCDIM_VERTICAL_SHIFT 0 |
Definition at line 1432 of file i915_reg.h.
#define DVO_USE_VGA_SYNC (1 << 15) |
Definition at line 1410 of file i915_reg.h.
#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) |
Definition at line 1422 of file i915_reg.h.
#define DVO_VSYNC_DISABLE (1 << 11) |
Definition at line 1413 of file i915_reg.h.
#define DVO_VSYNC_TRISTATE (1 << 9) |
Definition at line 1415 of file i915_reg.h.
#define DVOA 0x61120 |
Definition at line 1401 of file i915_reg.h.
#define DVOA_SRCDIM 0x61124 |
Definition at line 1428 of file i915_reg.h.
#define DVOB 0x61140 |
Definition at line 1402 of file i915_reg.h.
#define DVOB 0x61140 |
Definition at line 1402 of file i915_reg.h.
#define DVOB_ON (1UL<<31) |
Definition at line 918 of file i915_reg.h.
#define DVOB_SRCDIM 0x61144 |
Definition at line 1429 of file i915_reg.h.
#define DVOC 0x61160 |
Definition at line 1403 of file i915_reg.h.
#define DVOC 0x61160 |
Definition at line 1403 of file i915_reg.h.
#define DVOC_ON (1UL<<31) |
Definition at line 920 of file i915_reg.h.
#define DVOC_SRCDIM 0x61164 |
Definition at line 1430 of file i915_reg.h.
#define DVS_DEST_KEY (1<<2) |
Definition at line 2832 of file i915_reg.h.
#define DVS_ENABLE (1UL<<31) |
Definition at line 2818 of file i915_reg.h.
#define DVS_FILTER_ENHANCING (1<<29) |
Definition at line 2849 of file i915_reg.h.
#define DVS_FILTER_MASK (3<<29) |
Definition at line 2847 of file i915_reg.h.
#define DVS_FILTER_MEDIUM (0<<29) |
Definition at line 2848 of file i915_reg.h.
#define DVS_FILTER_SOFTENING (2<<29) |
Definition at line 2850 of file i915_reg.h.
#define DVS_FORMAT_RGBX101010 (1<<25) |
Definition at line 2822 of file i915_reg.h.
#define DVS_FORMAT_RGBX161616 (3<<25) |
Definition at line 2824 of file i915_reg.h.
#define DVS_FORMAT_RGBX888 (2<<25) |
Definition at line 2823 of file i915_reg.h.
#define DVS_FORMAT_YUV422 (0<<25) |
Definition at line 2821 of file i915_reg.h.
#define DVS_GAMMA_ENABLE (1<<30) |
Definition at line 2819 of file i915_reg.h.
#define DVS_PIXFORMAT_MASK (3<<25) |
Definition at line 2820 of file i915_reg.h.
#define DVS_RGB_ORDER_XBGR (1<<20) |
Definition at line 2826 of file i915_reg.h.
#define DVS_SCALE_ENABLE (1UL<<31) |
Definition at line 2846 of file i915_reg.h.
#define DVS_SOURCE_KEY (1<<22) |
Definition at line 2825 of file i915_reg.h.
#define DVS_TILED (1<<10) |
Definition at line 2834 of file i915_reg.h.
#define DVS_TRICKLE_FEED_DISABLE (1<<14) |
Definition at line 2833 of file i915_reg.h.
#define DVS_VERTICAL_OFFSET_ENABLE (1<<27) |
Definition at line 2852 of file i915_reg.h.
#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ |
Definition at line 2851 of file i915_reg.h.
#define DVS_YUV_BYTE_ORDER_MASK (3<<16) |
Definition at line 2827 of file i915_reg.h.
#define DVS_YUV_ORDER_UYVY (1<<16) |
Definition at line 2829 of file i915_reg.h.
#define DVS_YUV_ORDER_VYUY (3<<16) |
Definition at line 2831 of file i915_reg.h.
#define DVS_YUV_ORDER_YUYV (0<<16) |
Definition at line 2828 of file i915_reg.h.
#define DVS_YUV_ORDER_YVYU (2<<16) |
Definition at line 2830 of file i915_reg.h.
Definition at line 2869 of file i915_reg.h.
#define DVSKEYMAX | ( | pipe | ) | _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) |
Definition at line 2874 of file i915_reg.h.
#define DVSKEYMSK | ( | pipe | ) | _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) |
Definition at line 2879 of file i915_reg.h.
#define DVSKEYVAL | ( | pipe | ) | _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) |
Definition at line 2878 of file i915_reg.h.
#define DVSLINOFF | ( | pipe | ) | _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) |
Definition at line 2870 of file i915_reg.h.
#define DVSSCALE | ( | pipe | ) | _PIPE(pipe, _DVSASCALE, _DVSBSCALE) |
Definition at line 2876 of file i915_reg.h.
Definition at line 2875 of file i915_reg.h.
#define DVSSTRIDE | ( | pipe | ) | _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) |
Definition at line 2871 of file i915_reg.h.
Definition at line 2873 of file i915_reg.h.
#define DVSSURFLIVE | ( | pipe | ) | _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) |
Definition at line 2880 of file i915_reg.h.
#define DVSTILEOFF | ( | pipe | ) | _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) |
Definition at line 2877 of file i915_reg.h.
#define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ |
Definition at line 1051 of file i915_reg.h.
#define ECO_FLIP_DONE (1<<0) |
Definition at line 652 of file i915_reg.h.
#define ECO_GATING_CX_ONLY (1<<3) |
Definition at line 651 of file i915_reg.h.
#define ECOBITS_PPGTT_CACHE4B (0<<8) |
Definition at line 106 of file i915_reg.h.
#define ECOBITS_PPGTT_CACHE64B (3<<8) |
Definition at line 105 of file i915_reg.h.
#define ECOBUS 0xa180 |
Definition at line 3888 of file i915_reg.h.
#define ECOCHK_PPGTT_CACHE4B (0x0<<3) |
Definition at line 102 of file i915_reg.h.
#define ECOCHK_PPGTT_CACHE64B (0x3<<3) |
Definition at line 101 of file i915_reg.h.
#define ECOCHK_SNB_BIT (1<<10) |
Definition at line 100 of file i915_reg.h.
#define ECOSKPD 0x021d0 |
Definition at line 650 of file i915_reg.h.
#define EDP_BLC_ENABLE (1 << 2) |
Definition at line 3758 of file i915_reg.h.
#define EDP_FORCE_VDD (1 << 3) |
Definition at line 3757 of file i915_reg.h.
#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) |
Definition at line 3872 of file i915_reg.h.
#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) |
Definition at line 3874 of file i915_reg.h.
#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) |
Definition at line 3875 of file i915_reg.h.
#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) |
Definition at line 3854 of file i915_reg.h.
#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) |
Definition at line 3856 of file i915_reg.h.
#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) |
Definition at line 3862 of file i915_reg.h.
#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) |
Definition at line 3849 of file i915_reg.h.
#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) |
Definition at line 3863 of file i915_reg.h.
#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) |
Definition at line 3855 of file i915_reg.h.
#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) |
Definition at line 3864 of file i915_reg.h.
#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) |
Definition at line 3850 of file i915_reg.h.
#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) |
Definition at line 3871 of file i915_reg.h.
#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) |
Definition at line 3873 of file i915_reg.h.
#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) |
Definition at line 3857 of file i915_reg.h.
#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) |
Definition at line 3865 of file i915_reg.h.
#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) |
Definition at line 3866 of file i915_reg.h.
#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) |
Definition at line 3851 of file i915_reg.h.
#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) |
Definition at line 3858 of file i915_reg.h.
#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) |
Definition at line 3867 of file i915_reg.h.
#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) |
Definition at line 3852 of file i915_reg.h.
#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22) |
Definition at line 3868 of file i915_reg.h.
#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) |
Definition at line 3877 of file i915_reg.h.
#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) |
Definition at line 3859 of file i915_reg.h.
#define EDP_PANEL (1 << 30) |
Definition at line 3766 of file i915_reg.h.
#define EIR 0x020b0 |
Definition at line 550 of file i915_reg.h.
#define EMR 0x020b4 |
Definition at line 551 of file i915_reg.h.
#define ENC_TVDAC_SLEW_FAST (1 << 6) |
#define ENH_HIST_ENABLE (1UL<<31) |
Definition at line 1637 of file i915_reg.h.
#define ENH_MODE_ADDITIVE (1<<13) |
Definition at line 1645 of file i915_reg.h.
#define ENH_MODE_DIRECT (0<<13) |
Definition at line 1644 of file i915_reg.h.
#define ENH_MODE_MULTIPLICATIVE (2<<13) |
Definition at line 1646 of file i915_reg.h.
#define ENH_MODIF_TBL_ENABLE (1<<30) |
Definition at line 1638 of file i915_reg.h.
#define ENH_NUM_BINS 32 |
Definition at line 1648 of file i915_reg.h.
#define ENH_PIPE | ( | pipe | ) | _PIPE(pipe, ENH_PIPE_A_SELECT, ENH_PIPE_B_SELECT) |
Definition at line 1641 of file i915_reg.h.
#define ENH_PIPE_A_SELECT (0<<29) |
Definition at line 1639 of file i915_reg.h.
#define ENH_PIPE_B_SELECT (1<<29) |
Definition at line 1640 of file i915_reg.h.
#define ERR_INT_MMIO_UNCLAIMED (1<<13) |
Definition at line 479 of file i915_reg.h.
#define ERROR_GEN6 0x040a0 |
Definition at line 477 of file i915_reg.h.
#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ |
Definition at line 714 of file i915_reg.h.
#define FBC_CMD_COMPRESS (1<<0) |
Definition at line 725 of file i915_reg.h.
#define FBC_COMMAND 0x0320c |
Definition at line 724 of file i915_reg.h.
#define FBC_CONTROL 0x03208 |
Definition at line 716 of file i915_reg.h.
#define FBC_CONTROL2 0x03214 |
Definition at line 731 of file i915_reg.h.
#define FBC_CTL_C3_IDLE (1<<13) |
Definition at line 721 of file i915_reg.h.
#define FBC_CTL_CPU_FENCE (1<<1) |
Definition at line 737 of file i915_reg.h.
#define FBC_CTL_EN (1UL<<31) |
Definition at line 717 of file i915_reg.h.
#define FBC_CTL_FENCE_DBL (0<<4) |
Definition at line 732 of file i915_reg.h.
#define FBC_CTL_FENCENO (1<<0) |
Definition at line 723 of file i915_reg.h.
#define FBC_CTL_IDLE_DEBUG (3<<2) |
Definition at line 736 of file i915_reg.h.
#define FBC_CTL_IDLE_FULL (1<<2) |
Definition at line 734 of file i915_reg.h.
#define FBC_CTL_IDLE_IMM (0<<2) |
Definition at line 733 of file i915_reg.h.
#define FBC_CTL_IDLE_LINE (2<<2) |
Definition at line 735 of file i915_reg.h.
#define FBC_CTL_INTERVAL_SHIFT (16) |
Definition at line 719 of file i915_reg.h.
#define FBC_CTL_PERIODIC (1<<30) |
Definition at line 718 of file i915_reg.h.
#define FBC_CTL_PLANEA (0<<0) |
Definition at line 738 of file i915_reg.h.
#define FBC_CTL_PLANEB (1<<0) |
Definition at line 739 of file i915_reg.h.
#define FBC_CTL_STRIDE_SHIFT (5) |
Definition at line 722 of file i915_reg.h.
#define FBC_CTL_UNCOMPRESSIBLE (1<<14) |
Definition at line 720 of file i915_reg.h.
#define FBC_FENCE_OFF 0x0321b |
Definition at line 740 of file i915_reg.h.
#define FBC_LL_BASE 0x03204 /* 4k page aligned */ |
Definition at line 715 of file i915_reg.h.
#define FBC_LL_SIZE (1536) |
Definition at line 743 of file i915_reg.h.
#define FBC_STAT_COMPRESSED (1<<30) |
Definition at line 728 of file i915_reg.h.
#define FBC_STAT_COMPRESSING (1UL<<31) |
Definition at line 727 of file i915_reg.h.
#define FBC_STAT_CURRENT_LINE (1<<0) |
Definition at line 730 of file i915_reg.h.
#define FBC_STAT_MODIFIED (1<<29) |
Definition at line 729 of file i915_reg.h.
#define FBC_STATUS 0x03210 |
Definition at line 726 of file i915_reg.h.
#define FBC_TAG 0x03300 |
Definition at line 741 of file i915_reg.h.
#define FDI_10BPC (1<<16) |
Definition at line 3640 of file i915_reg.h.
#define FDI_12BPC (3<<16) |
Definition at line 3642 of file i915_reg.h.
#define FDI_6BPC (2<<16) |
Definition at line 3641 of file i915_reg.h.
#define FDI_8BPC (0<<16) |
Definition at line 3639 of file i915_reg.h.
#define FDI_AUTO_TRAINING (1<<10) |
Definition at line 3653 of file i915_reg.h.
#define FDI_BC_BIFURCATION_SELECT (1 << 12) |
Definition at line 3561 of file i915_reg.h.
#define FDI_COMPOSITE_SYNC (1<<11) |
Definition at line 3624 of file i915_reg.h.
#define FDI_DMI_LINK_REVERSE_MASK (1<<14) |
Definition at line 3644 of file i915_reg.h.
#define FDI_DP_PORT_WIDTH_X1 (0<<19) |
Definition at line 3609 of file i915_reg.h.
#define FDI_DP_PORT_WIDTH_X2 (1<<19) |
Definition at line 3610 of file i915_reg.h.
#define FDI_DP_PORT_WIDTH_X3 (2<<19) |
Definition at line 3611 of file i915_reg.h.
#define FDI_DP_PORT_WIDTH_X4 (3<<19) |
Definition at line 3612 of file i915_reg.h.
#define FDI_DP_PORT_WIDTH_X8 (7<<19) |
Definition at line 3637 of file i915_reg.h.
#define FDI_FE_ERR_CORRECT_ENABLE (1<<10) |
Definition at line 3647 of file i915_reg.h.
#define FDI_FE_ERR_REPORT_ENABLE (1<<8) |
Definition at line 3649 of file i915_reg.h.
#define FDI_FE_ERRC_ENABLE (1<<26) |
Definition at line 3636 of file i915_reg.h.
#define FDI_FS_ERR_CORRECT_ENABLE (1<<11) |
Definition at line 3646 of file i915_reg.h.
#define FDI_FS_ERR_REPORT_ENABLE (1<<9) |
Definition at line 3648 of file i915_reg.h.
#define FDI_FS_ERRC_ENABLE (1<<27) |
Definition at line 3635 of file i915_reg.h.
#define FDI_LINK_REVERSE_OVERWRITE (1<<15) |
Definition at line 3643 of file i915_reg.h.
#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) |
Definition at line 3599 of file i915_reg.h.
#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) |
Definition at line 3604 of file i915_reg.h.
#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) |
Definition at line 3600 of file i915_reg.h.
#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) |
Definition at line 3605 of file i915_reg.h.
#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) |
Definition at line 3601 of file i915_reg.h.
#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) |
Definition at line 3606 of file i915_reg.h.
#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) |
Definition at line 3602 of file i915_reg.h.
#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) |
Definition at line 3607 of file i915_reg.h.
#define FDI_LINK_TRAIN_AUTO (1<<10) |
Definition at line 3625 of file i915_reg.h.
#define FDI_LINK_TRAIN_NONE (3<<28) |
Definition at line 3587 of file i915_reg.h.
#define FDI_LINK_TRAIN_NONE_IVB (3<<8) |
Definition at line 3621 of file i915_reg.h.
#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) |
Definition at line 3657 of file i915_reg.h.
#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) |
Definition at line 3584 of file i915_reg.h.
#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) |
Definition at line 3654 of file i915_reg.h.
#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) |
Definition at line 3618 of file i915_reg.h.
#define FDI_LINK_TRAIN_PATTERN_2 (1<<28) |
Definition at line 3585 of file i915_reg.h.
#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) |
Definition at line 3655 of file i915_reg.h.
#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) |
Definition at line 3619 of file i915_reg.h.
#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) |
Definition at line 3586 of file i915_reg.h.
#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) |
Definition at line 3656 of file i915_reg.h.
#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) |
Definition at line 3620 of file i915_reg.h.
#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) |
Definition at line 3658 of file i915_reg.h.
#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) |
Definition at line 3593 of file i915_reg.h.
#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) |
Definition at line 3594 of file i915_reg.h.
#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) |
Definition at line 3595 of file i915_reg.h.
#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) |
Definition at line 3592 of file i915_reg.h.
#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) |
Definition at line 3608 of file i915_reg.h.
#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) |
Definition at line 3588 of file i915_reg.h.
#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) |
Definition at line 3589 of file i915_reg.h.
#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) |
Definition at line 3590 of file i915_reg.h.
#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) |
Definition at line 3591 of file i915_reg.h.
#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) |
Definition at line 3564 of file i915_reg.h.
#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) |
Definition at line 3563 of file i915_reg.h.
#define FDI_PCDCLK (1<<4) |
Definition at line 3651 of file i915_reg.h.
#define FDI_PHASE_SYNC_EN | ( | pipe | ) | (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) |
Definition at line 3560 of file i915_reg.h.
#define FDI_PHASE_SYNC_OVR | ( | pipe | ) | (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) |
Definition at line 3559 of file i915_reg.h.
#define FDI_PLL_BIOS_0 0x46000 |
Definition at line 2983 of file i915_reg.h.
#define FDI_PLL_BIOS_1 0x46004 |
Definition at line 2985 of file i915_reg.h.
#define FDI_PLL_BIOS_2 0x46008 |
Definition at line 2986 of file i915_reg.h.
#define FDI_PLL_CTL_1 0xfe000 |
Definition at line 3701 of file i915_reg.h.
#define FDI_PLL_CTL_2 0xfe004 |
Definition at line 3702 of file i915_reg.h.
#define FDI_PLL_FB_CLOCK_MASK 0xff |
Definition at line 2984 of file i915_reg.h.
#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) |
Definition at line 2999 of file i915_reg.h.
#define FDI_PLL_FREQ_CTL 0x46030 |
Definition at line 2998 of file i915_reg.h.
#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff |
Definition at line 3001 of file i915_reg.h.
#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 |
Definition at line 3000 of file i915_reg.h.
#define FDI_PORT_WIDTH_1X_LPT (0<<19) |
Definition at line 3661 of file i915_reg.h.
#define FDI_PORT_WIDTH_2X_LPT (1<<19) |
Definition at line 3660 of file i915_reg.h.
#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ |
Definition at line 3684 of file i915_reg.h.
#define FDI_RX_CHICKEN | ( | pipe | ) | _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) |
Definition at line 3572 of file i915_reg.h.
#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) |
Definition at line 3691 of file i915_reg.h.
#define FDI_RX_CTL | ( | pipe | ) | _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) |
Definition at line 3632 of file i915_reg.h.
#define FDI_RX_ENABLE (1UL<<31) |
Definition at line 3633 of file i915_reg.h.
#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) |
Definition at line 3650 of file i915_reg.h.
#define FDI_RX_FDI_DELAY_90 (0x90<<0) |
Definition at line 3671 of file i915_reg.h.
#define FDI_RX_FE_CODE_ERR (1<<5) |
Definition at line 3687 of file i915_reg.h.
#define FDI_RX_FS_CODE_ERR (1<<6) |
Definition at line 3686 of file i915_reg.h.
#define FDI_RX_HDCP_LINK_FAIL (1<<3) |
Definition at line 3689 of file i915_reg.h.
#define FDI_RX_IIR | ( | pipe | ) | _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) |
Definition at line 3698 of file i915_reg.h.
#define FDI_RX_IMR | ( | pipe | ) | _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) |
Definition at line 3699 of file i915_reg.h.
#define FDI_RX_INTER_LANE_ALIGN (1<<10) |
Definition at line 3682 of file i915_reg.h.
#define FDI_RX_MISC | ( | pipe | ) | _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) |
Definition at line 3672 of file i915_reg.h.
#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) |
Definition at line 3571 of file i915_reg.h.
#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) |
Definition at line 3570 of file i915_reg.h.
#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) |
Definition at line 3690 of file i915_reg.h.
#define FDI_RX_PLL_ENABLE (1<<13) |
Definition at line 3645 of file i915_reg.h.
#define FDI_RX_POLARITY_REVERSED_LPT (1<<16) |
Definition at line 3638 of file i915_reg.h.
#define FDI_RX_PWRDN_LANE0_MASK (3<<24) |
Definition at line 3667 of file i915_reg.h.
Definition at line 3668 of file i915_reg.h.
#define FDI_RX_PWRDN_LANE1_MASK (3<<26) |
Definition at line 3665 of file i915_reg.h.
Definition at line 3666 of file i915_reg.h.
#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) |
Definition at line 3688 of file i915_reg.h.
#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ |
Definition at line 3683 of file i915_reg.h.
#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) |
Definition at line 3692 of file i915_reg.h.
#define FDI_RX_TP1_TO_TP2_48 (2<<20) |
Definition at line 3669 of file i915_reg.h.
#define FDI_RX_TP1_TO_TP2_64 (3<<20) |
Definition at line 3670 of file i915_reg.h.
#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) |
Definition at line 3685 of file i915_reg.h.
#define FDI_RX_TUSIZE1 | ( | pipe | ) | _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) |
Definition at line 3678 of file i915_reg.h.
#define FDI_RX_TUSIZE2 | ( | pipe | ) | _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) |
Definition at line 3679 of file i915_reg.h.
#define FDI_SCRAMBLING_DISABLE (1<<7) |
Definition at line 3627 of file i915_reg.h.
#define FDI_SCRAMBLING_ENABLE (0<<7) |
Definition at line 3626 of file i915_reg.h.
#define FDI_TX_CTL | ( | pipe | ) | _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) |
Definition at line 3581 of file i915_reg.h.
#define FDI_TX_DISABLE (0UL<<31) |
Definition at line 3582 of file i915_reg.h.
#define FDI_TX_ENABLE (1UL<<31) |
Definition at line 3583 of file i915_reg.h.
#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) |
Definition at line 3613 of file i915_reg.h.
#define FDI_TX_PLL_ENABLE (1<<14) |
Definition at line 3615 of file i915_reg.h.
#define FDIA_PHASE_SYNC_SHIFT_EN 18 |
Definition at line 3558 of file i915_reg.h.
#define FDIA_PHASE_SYNC_SHIFT_OVR 19 |
Definition at line 3557 of file i915_reg.h.
#define FDL_TP1_TIMER_MASK (3<<12) |
Definition at line 3369 of file i915_reg.h.
#define FDL_TP1_TIMER_SHIFT 12 |
Definition at line 3368 of file i915_reg.h.
#define FDL_TP2_TIMER_MASK (3<<10) |
Definition at line 3371 of file i915_reg.h.
#define FDL_TP2_TIMER_SHIFT 10 |
Definition at line 3370 of file i915_reg.h.
#define FENCE_REG_830_0 0x2000 |
Definition at line 369 of file i915_reg.h.
#define FENCE_REG_945_8 0x3000 |
Definition at line 370 of file i915_reg.h.
#define FENCE_REG_965_0 0x03000 |
Definition at line 383 of file i915_reg.h.
#define FENCE_REG_SANDYBRIDGE_0 0x100000 |
Definition at line 389 of file i915_reg.h.
#define FORCEWAKE 0xA18C |
Definition at line 3879 of file i915_reg.h.
#define FORCEWAKE_ACK 0x130090 |
Definition at line 3883 of file i915_reg.h.
#define FORCEWAKE_ACK_HSW 0x130044 |
Definition at line 3882 of file i915_reg.h.
#define FORCEWAKE_ACK_VLV 0x1300b4 |
Definition at line 3881 of file i915_reg.h.
#define FORCEWAKE_KERNEL 0x1 |
Definition at line 3885 of file i915_reg.h.
#define FORCEWAKE_MT 0xa188 /* multi-threaded */ |
Definition at line 3884 of file i915_reg.h.
#define FORCEWAKE_MT_ACK 0x130040 |
Definition at line 3887 of file i915_reg.h.
#define FORCEWAKE_MT_ENABLE (1<<5) |
Definition at line 3889 of file i915_reg.h.
#define FORCEWAKE_USER 0x2 |
Definition at line 3886 of file i915_reg.h.
#define FORCEWAKE_VLV 0x1300b0 |
Definition at line 3880 of file i915_reg.h.
#define FP_CB_TUNE (0x3<<22) |
Definition at line 3335 of file i915_reg.h.
#define FP_M1_DIV_MASK 0x00003f00 |
Definition at line 1018 of file i915_reg.h.
#define FP_M1_DIV_SHIFT 8 |
Definition at line 1019 of file i915_reg.h.
#define FP_M2_DIV_MASK 0x0000003f |
Definition at line 1020 of file i915_reg.h.
#define FP_M2_DIV_SHIFT 0 |
Definition at line 1022 of file i915_reg.h.
#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff |
Definition at line 1021 of file i915_reg.h.
#define FP_N_DIV_MASK 0x003f0000 |
Definition at line 1015 of file i915_reg.h.
#define FP_N_DIV_SHIFT 16 |
Definition at line 1017 of file i915_reg.h.
#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 |
Definition at line 1016 of file i915_reg.h.
#define FW_BLC 0x020d8 |
Definition at line 563 of file i915_reg.h.
#define FW_BLC2 0x020dc |
Definition at line 564 of file i915_reg.h.
#define FW_BLC_SELF 0x020e0 /* 915+ only */ |
Definition at line 565 of file i915_reg.h.
#define FW_BLC_SELF_EN (1<<15) /* 945 only */ |
Definition at line 568 of file i915_reg.h.
#define FW_BLC_SELF_EN_MASK (1UL<<31) |
Definition at line 566 of file i915_reg.h.
#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ |
Definition at line 567 of file i915_reg.h.
#define FW_BLC_SELF_VLV 0x6500 |
Definition at line 1149 of file i915_reg.h.
#define FW_CSPWRDWNEN (1<<15) |
Definition at line 1150 of file i915_reg.h.
#define G4X_AUD_CNTL_ST 0x620B4 |
Definition at line 4048 of file i915_reg.h.
#define G4X_AUD_VID_DID 0x62020 |
Definition at line 4043 of file i915_reg.h.
#define G4X_ELD_ACK (1 << 4) |
Definition at line 4052 of file i915_reg.h.
#define G4X_ELD_ADDR (0xf << 5) |
Definition at line 4051 of file i915_reg.h.
#define G4X_ELDV_DEVCL_DEVBLC (1 << 13) |
Definition at line 4049 of file i915_reg.h.
#define G4X_ELDV_DEVCTG (1 << 14) |
Definition at line 4050 of file i915_reg.h.
#define G4X_FIFO_LINE_SIZE 64 |
Definition at line 2537 of file i915_reg.h.
#define G4X_FIFO_SIZE 127 |
Definition at line 2542 of file i915_reg.h.
#define G4X_HDMIW_HDMIEDID 0x6210C |
Definition at line 4053 of file i915_reg.h.
#define G4X_MAX_WM 0x3f |
Definition at line 2550 of file i915_reg.h.
#define GAB_CTL 0x24000 |
Definition at line 108 of file i915_reg.h.
#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) |
Definition at line 109 of file i915_reg.h.
#define GAC_ECO_BITS 0x14090 |
Definition at line 104 of file i915_reg.h.
#define GAM_ECOCHK 0x4090 |
Definition at line 99 of file i915_reg.h.
#define GC_CLOCK_100_133 (2 << 0) |
Definition at line 36 of file i915_reg.h.
#define GC_CLOCK_100_200 (1 << 0) |
Definition at line 35 of file i915_reg.h.
#define GC_CLOCK_133_200 (0 << 0) |
Definition at line 34 of file i915_reg.h.
#define GC_CLOCK_166_250 (3 << 0) |
Definition at line 37 of file i915_reg.h.
#define GC_CLOCK_CONTROL_MASK (0xf << 0) |
Definition at line 33 of file i915_reg.h.
#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) |
Definition at line 41 of file i915_reg.h.
#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) |
Definition at line 42 of file i915_reg.h.
#define GC_DISPLAY_CLOCK_MASK (7 << 4) |
Definition at line 43 of file i915_reg.h.
#define GC_LOW_FREQUENCY_ENABLE (1 << 7) |
Definition at line 40 of file i915_reg.h.
#define GCFG_DIS (1<<8) |
Definition at line 526 of file i915_reg.h.
#define GCFGC 0xf0 /* 915+ only */ |
Definition at line 39 of file i915_reg.h.
#define GCFGC2 0xda |
Definition at line 38 of file i915_reg.h.
#define GEN6_AGGRESSIVE_TURBO (0<<15) |
Definition at line 3918 of file i915_reg.h.
#define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) |
Definition at line 3901 of file i915_reg.h.
#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) |
Definition at line 675 of file i915_reg.h.
#define GEN6_BLITTER_ECOSKPD 0x221d0 |
Definition at line 679 of file i915_reg.h.
#define GEN6_BLITTER_FBC_NOTIFY (1<<3) |
Definition at line 681 of file i915_reg.h.
#define GEN6_BLITTER_HWSTAM 0x22098 |
Definition at line 672 of file i915_reg.h.
#define GEN6_BLITTER_IMR 0x220a8 |
Definition at line 673 of file i915_reg.h.
#define GEN6_BLITTER_LOCK_SHIFT 16 |
Definition at line 680 of file i915_reg.h.
#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) |
Definition at line 674 of file i915_reg.h.
#define GEN6_BLITTER_SYNC_STATUS (1 << 24) |
Definition at line 676 of file i915_reg.h.
#define GEN6_BLITTER_USER_INTERRUPT (1 << 22) |
Definition at line 677 of file i915_reg.h.
#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) |
Definition at line 416 of file i915_reg.h.
#define GEN6_BSD_GO_INDICATOR (1 << 4) |
Definition at line 687 of file i915_reg.h.
#define GEN6_BSD_HWSTAM 0x12098 |
Definition at line 689 of file i915_reg.h.
#define GEN6_BSD_IMR 0x120a8 |
Definition at line 690 of file i915_reg.h.
#define GEN6_BSD_RING_BASE 0x12000 |
Definition at line 404 of file i915_reg.h.
#define GEN6_BSD_RNCID 0x12198 |
Definition at line 693 of file i915_reg.h.
#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) |
Definition at line 685 of file i915_reg.h.
#define GEN6_BSD_SLEEP_INDICATOR (1 << 3) |
Definition at line 686 of file i915_reg.h.
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) |
Definition at line 684 of file i915_reg.h.
#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 |
Definition at line 683 of file i915_reg.h.
#define GEN6_BSD_USER_INTERRUPT (1 << 12) |
Definition at line 691 of file i915_reg.h.
#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) |
Definition at line 417 of file i915_reg.h.
#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) |
Definition at line 3932 of file i915_reg.h.
#define GEN6_CAGF_SHIFT 8 |
Definition at line 3931 of file i915_reg.h.
#define GEN6_CORE_CPD_STATE_MASK (7<<4) |
Definition at line 4007 of file i915_reg.h.
#define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) |
Definition at line 3902 of file i915_reg.h.
#define GEN6_CURBSYTAVG_MASK 0xffffff |
Definition at line 3952 of file i915_reg.h.
#define GEN6_CURIAVG_MASK 0xffffff |
Definition at line 3955 of file i915_reg.h.
#define GEN6_CURICONT_MASK 0xffffff |
Definition at line 3950 of file i915_reg.h.
#define GEN6_CXT_EXTENDED_SIZE | ( | cxt_reg | ) | ((cxt_reg >> 6) & 0x3f) |
Definition at line 1181 of file i915_reg.h.
#define GEN6_CXT_PIPELINE_SIZE | ( | cxt_reg | ) | ((cxt_reg >> 0) & 0x3f) |
Definition at line 1182 of file i915_reg.h.
#define GEN6_CXT_POWER_SIZE | ( | cxt_reg | ) | ((cxt_reg >> 24) & 0x3f) |
Definition at line 1178 of file i915_reg.h.
#define GEN6_CXT_RENDER_SIZE | ( | cxt_reg | ) | ((cxt_reg >> 12) & 0x3f) |
Definition at line 1180 of file i915_reg.h.
#define GEN6_CXT_RING_SIZE | ( | cxt_reg | ) | ((cxt_reg >> 18) & 0x3f) |
Definition at line 1179 of file i915_reg.h.
#define GEN6_CXT_TOTAL_SIZE | ( | cxt_reg | ) |
Definition at line 1183 of file i915_reg.h.
#define GEN6_DECODE_RC6_VID | ( | vids | ) | (((vids) * 5) > 0 ? ((vids) * 5) + 245 : 0) |
Definition at line 4002 of file i915_reg.h.
#define GEN6_ENCODE_RC6_VID | ( | mv | ) | (((mv) / 5) - 245) < 0 ?: 0 |
Definition at line 4001 of file i915_reg.h.
Definition at line 3916 of file i915_reg.h.
#define GEN6_GDRST 0x941c |
Definition at line 88 of file i915_reg.h.
#define GEN6_GRDOM_BLT (1 << 3) |
Definition at line 92 of file i915_reg.h.
#define GEN6_GRDOM_FULL (1 << 0) |
Definition at line 89 of file i915_reg.h.
#define GEN6_GRDOM_MEDIA (1 << 2) |
Definition at line 91 of file i915_reg.h.
#define GEN6_GRDOM_RENDER (1 << 1) |
Definition at line 90 of file i915_reg.h.
#define GEN6_GT_CORE_STATUS 0x138060 |
Definition at line 4006 of file i915_reg.h.
#define GEN6_GT_GFX_RC6 0x138108 |
Definition at line 3990 of file i915_reg.h.
#define GEN6_GT_GFX_RC6_LOCKED 0x138104 |
Definition at line 3989 of file i915_reg.h.
#define GEN6_GT_GFX_RC6p 0x13810C |
Definition at line 3991 of file i915_reg.h.
#define GEN6_GT_GFX_RC6pp 0x138110 |
Definition at line 3992 of file i915_reg.h.
#define GEN6_GT_MODE 0x20d0 |
Definition at line 504 of file i915_reg.h.
#define GEN6_GT_MODE_HI (1 << 9) |
Definition at line 505 of file i915_reg.h.
#define GEN6_MBC_SNPCR_LOW (2<<21) |
Definition at line 78 of file i915_reg.h.
#define GEN6_MBC_SNPCR_MASK (3<<21) |
Definition at line 75 of file i915_reg.h.
#define GEN6_MBC_SNPCR_MAX (0<<21) |
Definition at line 76 of file i915_reg.h.
#define GEN6_MBC_SNPCR_MED (1<<21) |
Definition at line 77 of file i915_reg.h.
#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ |
Definition at line 79 of file i915_reg.h.
#define GEN6_MBC_SNPCR_SHIFT 21 |
Definition at line 74 of file i915_reg.h.
#define GEN6_MBCTL 0x0907c |
Definition at line 81 of file i915_reg.h.
#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) |
Definition at line 84 of file i915_reg.h.
#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) |
Definition at line 86 of file i915_reg.h.
#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) |
Definition at line 83 of file i915_reg.h.
#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) |
Definition at line 82 of file i915_reg.h.
#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) |
Definition at line 85 of file i915_reg.h.
#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ |
Definition at line 73 of file i915_reg.h.
Definition at line 3917 of file i915_reg.h.
#define GEN6_PCODE_DATA 0x138128 |
Definition at line 4003 of file i915_reg.h.
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
Definition at line 4004 of file i915_reg.h.
#define GEN6_PCODE_MAILBOX 0x138124 |
Definition at line 3994 of file i915_reg.h.
#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 |
Definition at line 3998 of file i915_reg.h.
#define GEN6_PCODE_READ_RC6VIDS 0x5 |
Definition at line 4000 of file i915_reg.h.
#define GEN6_PCODE_READY (1UL<<31) |
Definition at line 3995 of file i915_reg.h.
#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
Definition at line 3997 of file i915_reg.h.
#define GEN6_PCODE_WRITE_RC6VIDS 0x4 |
Definition at line 3999 of file i915_reg.h.
#define GEN6_PM_DEFERRED_EVENTS |
Definition at line 3985 of file i915_reg.h.
#define GEN6_PM_MBOX_EVENT (1<<25) |
Definition at line 3978 of file i915_reg.h.
#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) |
Definition at line 3984 of file i915_reg.h.
#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) |
Definition at line 3982 of file i915_reg.h.
#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) |
Definition at line 3980 of file i915_reg.h.
#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) |
Definition at line 3983 of file i915_reg.h.
#define GEN6_PM_RP_UP_THRESHOLD (1<<5) |
Definition at line 3981 of file i915_reg.h.
#define GEN6_PM_THERMAL_EVENT (1<<24) |
Definition at line 3979 of file i915_reg.h.
#define GEN6_PMIER 0x4402C |
Definition at line 3977 of file i915_reg.h.
#define GEN6_PMIIR 0x44028 |
Definition at line 3976 of file i915_reg.h.
#define GEN6_PMIMR 0x44024 /* rps_lock */ |
Definition at line 3975 of file i915_reg.h.
#define GEN6_PMINTRMSK 0xA168 |
Definition at line 3972 of file i915_reg.h.
#define GEN6_PMISR 0x44020 |
Definition at line 3974 of file i915_reg.h.
#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) |
Definition at line 413 of file i915_reg.h.
#define GEN6_RC0 0 |
Definition at line 4009 of file i915_reg.h.
#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 |
Definition at line 3962 of file i915_reg.h.
#define GEN6_RC1e_THRESHOLD 0xA0B4 |
Definition at line 3968 of file i915_reg.h.
#define GEN6_RC3 2 |
Definition at line 4010 of file i915_reg.h.
#define GEN6_RC6 3 |
Definition at line 4011 of file i915_reg.h.
#define GEN6_RC6_THRESHOLD 0xA0B8 |
Definition at line 3969 of file i915_reg.h.
#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C |
Definition at line 3963 of file i915_reg.h.
#define GEN6_RC6p_THRESHOLD 0xA0BC |
Definition at line 3970 of file i915_reg.h.
#define GEN6_RC6pp_THRESHOLD 0xA0C0 |
Definition at line 3971 of file i915_reg.h.
#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 |
Definition at line 3964 of file i915_reg.h.
#define GEN6_RC7 4 |
Definition at line 4012 of file i915_reg.h.
#define GEN6_RC_CONTROL 0xA090 |
Definition at line 3920 of file i915_reg.h.
Definition at line 3926 of file i915_reg.h.
#define GEN6_RC_CTL_HW_ENABLE (1UL<<31) |
Definition at line 3927 of file i915_reg.h.
#define GEN6_RC_CTL_RC1e_ENABLE (1<<20) |
Definition at line 3924 of file i915_reg.h.
#define GEN6_RC_CTL_RC6_ENABLE (1<<18) |
Definition at line 3923 of file i915_reg.h.
#define GEN6_RC_CTL_RC6p_ENABLE (1<<17) |
Definition at line 3922 of file i915_reg.h.
#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) |
Definition at line 3921 of file i915_reg.h.
#define GEN6_RC_CTL_RC7_ENABLE (1<<22) |
Definition at line 3925 of file i915_reg.h.
#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 |
Definition at line 3965 of file i915_reg.h.
#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC |
Definition at line 3966 of file i915_reg.h.
#define GEN6_RC_SLEEP 0xA0B0 |
Definition at line 3967 of file i915_reg.h.
#define GEN6_RC_STATE 0xA094 |
Definition at line 3961 of file i915_reg.h.
#define GEN6_RC_VIDEO_FREQ 0xA00C |
Definition at line 3919 of file i915_reg.h.
#define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) |
Definition at line 3909 of file i915_reg.h.
#define GEN6_RCn_MASK 7 |
Definition at line 4008 of file i915_reg.h.
#define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) |
Definition at line 3908 of file i915_reg.h.
#define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) |
Definition at line 3907 of file i915_reg.h.
#define GEN6_READ_OC_PARAMS 0xc |
Definition at line 3996 of file i915_reg.h.
#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) |
Definition at line 667 of file i915_reg.h.
#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) |
Definition at line 662 of file i915_reg.h.
#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) |
Definition at line 669 of file i915_reg.h.
#define GEN6_RENDER_HWSTAM 0x2098 |
Definition at line 660 of file i915_reg.h.
#define GEN6_RENDER_IMR 0x20a8 |
Definition at line 661 of file i915_reg.h.
#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) |
Definition at line 665 of file i915_reg.h.
#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) |
Definition at line 666 of file i915_reg.h.
#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) |
Definition at line 663 of file i915_reg.h.
#define GEN6_RENDER_SYNC_STATUS (1 << 2) |
Definition at line 668 of file i915_reg.h.
#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) |
Definition at line 664 of file i915_reg.h.
#define GEN6_RENDER_USER_INTERRUPT (1 << 0) |
Definition at line 670 of file i915_reg.h.
#define GEN6_RP_CONTROL 0xA024 |
Definition at line 3933 of file i915_reg.h.
#define GEN6_RP_CUR_DOWN 0xA060 |
Definition at line 3956 of file i915_reg.h.
#define GEN6_RP_CUR_DOWN_EI 0xA05C |
Definition at line 3954 of file i915_reg.h.
#define GEN6_RP_CUR_UP 0xA054 |
Definition at line 3951 of file i915_reg.h.
#define GEN6_RP_CUR_UP_EI 0xA050 |
Definition at line 3949 of file i915_reg.h.
#define GEN6_RP_DOWN_EI 0xA06C |
Definition at line 3959 of file i915_reg.h.
#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) |
Definition at line 3946 of file i915_reg.h.
#define GEN6_RP_DOWN_THRESHOLD 0xA030 |
Definition at line 3948 of file i915_reg.h.
#define GEN6_RP_DOWN_TIMEOUT 0xA010 |
Definition at line 3928 of file i915_reg.h.
#define GEN6_RP_ENABLE (1<<7) |
Definition at line 3941 of file i915_reg.h.
#define GEN6_RP_IDLE_HYSTERSIS 0xA070 |
Definition at line 3960 of file i915_reg.h.
#define GEN6_RP_INTERRUPT_LIMITS 0xA014 |
Definition at line 3929 of file i915_reg.h.
#define GEN6_RP_MEDIA_HW_MODE (1<<9) |
Definition at line 3938 of file i915_reg.h.
#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) |
Definition at line 3937 of file i915_reg.h.
#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) |
Definition at line 3936 of file i915_reg.h.
#define GEN6_RP_MEDIA_IS_GFX (1<<8) |
Definition at line 3940 of file i915_reg.h.
#define GEN6_RP_MEDIA_MODE_MASK (3<<9) |
Definition at line 3935 of file i915_reg.h.
#define GEN6_RP_MEDIA_SW_MODE (0<<9) |
Definition at line 3939 of file i915_reg.h.
#define GEN6_RP_MEDIA_TURBO (1<<11) |
Definition at line 3934 of file i915_reg.h.
#define GEN6_RP_PREV_DOWN 0xA064 |
Definition at line 3957 of file i915_reg.h.
#define GEN6_RP_PREV_UP 0xA058 |
Definition at line 3953 of file i915_reg.h.
#define GEN6_RP_UP_BUSY_AVG (0x2<<3) |
Definition at line 3943 of file i915_reg.h.
#define GEN6_RP_UP_BUSY_CONT (0x4<<3) |
Definition at line 3944 of file i915_reg.h.
#define GEN6_RP_UP_EI 0xA068 |
Definition at line 3958 of file i915_reg.h.
#define GEN6_RP_UP_IDLE_MIN (0x1<<3) |
Definition at line 3942 of file i915_reg.h.
#define GEN6_RP_UP_THRESHOLD 0xA02C |
Definition at line 3947 of file i915_reg.h.
#define GEN6_RPNSWREQ 0xA008 |
Definition at line 3914 of file i915_reg.h.
#define GEN6_RPSTAT1 0xA01C |
Definition at line 3930 of file i915_reg.h.
#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) |
Definition at line 412 of file i915_reg.h.
#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) |
Definition at line 506 of file i915_reg.h.
#define GEN6_TURBO_DISABLE (1UL<<31) |
Definition at line 3915 of file i915_reg.h.
#define GEN6_UCGCTL1 0x9400 |
Definition at line 3900 of file i915_reg.h.
#define GEN6_UCGCTL2 0x9404 |
Definition at line 3904 of file i915_reg.h.
#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) |
Definition at line 415 of file i915_reg.h.
#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) |
Definition at line 414 of file i915_reg.h.
#define GEN7_COMMON_SLICE_CHICKEN1 0x7010 |
Definition at line 3184 of file i915_reg.h.
#define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) |
Definition at line 3185 of file i915_reg.h.
#define GEN7_CXT_EXTENDED_SIZE | ( | ctx_reg | ) | ((ctx_reg >> 9) & 0x7f) |
Definition at line 1192 of file i915_reg.h.
#define GEN7_CXT_GT1_SIZE | ( | ctx_reg | ) | ((ctx_reg >> 6) & 0x7) |
Definition at line 1193 of file i915_reg.h.
#define GEN7_CXT_POWER_SIZE | ( | ctx_reg | ) | ((ctx_reg >> 25) & 0x7f) |
Definition at line 1189 of file i915_reg.h.
#define GEN7_CXT_RENDER_SIZE | ( | ctx_reg | ) | ((ctx_reg >> 16) & 0x3f) |
Definition at line 1191 of file i915_reg.h.
#define GEN7_CXT_RING_SIZE | ( | ctx_reg | ) | ((ctx_reg >> 22) & 0x7) |
Definition at line 1190 of file i915_reg.h.
#define GEN7_CXT_SIZE 0x21a8 |
Definition at line 1188 of file i915_reg.h.
#define GEN7_CXT_TOTAL_SIZE | ( | ctx_reg | ) |
Definition at line 1195 of file i915_reg.h.
#define GEN7_CXT_VFSTATE_SIZE | ( | ctx_reg | ) | ((ctx_reg >> 0) & 0x3f) |
Definition at line 1194 of file i915_reg.h.
#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) |
Definition at line 4015 of file i915_reg.h.
#define GEN7_ERR_INT 0x44040 |
Definition at line 478 of file i915_reg.h.
#define GEN7_FF_DS_SCHED_HS0 (0x3<<4) |
Definition at line 706 of file i915_reg.h.
#define GEN7_FF_DS_SCHED_HS1 (0x5<<4) |
Definition at line 705 of file i915_reg.h.
#define GEN7_FF_DS_SCHED_HW (0x0<<4) |
Definition at line 708 of file i915_reg.h.
#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ |
Definition at line 707 of file i915_reg.h.
#define GEN7_FF_SCHED_MASK 0x0077070 |
Definition at line 696 of file i915_reg.h.
#define GEN7_FF_THREAD_MODE 0x20a0 |
Definition at line 695 of file i915_reg.h.
#define GEN7_FF_TS_SCHED_HS0 (0x3<<16) |
Definition at line 698 of file i915_reg.h.
#define GEN7_FF_TS_SCHED_HS1 (0x5<<16) |
Definition at line 697 of file i915_reg.h.
#define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ |
Definition at line 700 of file i915_reg.h.
#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) |
Definition at line 699 of file i915_reg.h.
#define GEN7_FF_VS_SCHED_HS0 (0x3<<12) |
Definition at line 702 of file i915_reg.h.
#define GEN7_FF_VS_SCHED_HS1 (0x5<<12) |
Definition at line 701 of file i915_reg.h.
#define GEN7_FF_VS_SCHED_HW (0x0<<12) |
Definition at line 704 of file i915_reg.h.
#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ |
Definition at line 703 of file i915_reg.h.
#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ |
Definition at line 4034 of file i915_reg.h.
#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 |
Definition at line 4035 of file i915_reg.h.
#define GEN7_INSTDONE_1 0x0206c |
Definition at line 451 of file i915_reg.h.
#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 |
Definition at line 3191 of file i915_reg.h.
#define GEN7_L3AGDIS (1<<19) |
Definition at line 3189 of file i915_reg.h.
#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) |
Definition at line 3912 of file i915_reg.h.
#define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ |
Definition at line 4018 of file i915_reg.h.
#define GEN7_L3CDERRST1_BANK_MASK (3<<11) |
Definition at line 4021 of file i915_reg.h.
#define GEN7_L3CDERRST1_ENABLE (1<<7) |
Definition at line 4029 of file i915_reg.h.
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) |
Definition at line 4019 of file i915_reg.h.
#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) |
Definition at line 4022 of file i915_reg.h.
#define GEN7_L3CNTLREG1 0xB01C |
Definition at line 3187 of file i915_reg.h.
#define GEN7_L3LOG_BASE 0xB070 |
Definition at line 4031 of file i915_reg.h.
#define GEN7_L3LOG_SIZE 0x80 |
Definition at line 4032 of file i915_reg.h.
#define GEN7_L3SQCREG4 0xb034 |
Definition at line 3194 of file i915_reg.h.
#define GEN7_MAX_PS_THREAD_DEP (8<<12) |
Definition at line 4036 of file i915_reg.h.
#define GEN7_MISCCPCTL (0x9424) |
Definition at line 4014 of file i915_reg.h.
#define GEN7_PARITY_ERROR_BANK | ( | reg | ) | ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) |
Definition at line 4025 of file i915_reg.h.
#define GEN7_PARITY_ERROR_ROW | ( | reg | ) | ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) |
Definition at line 4023 of file i915_reg.h.
#define GEN7_PARITY_ERROR_SUBBANK | ( | reg | ) | ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) |
Definition at line 4027 of file i915_reg.h.
#define GEN7_PARITY_ERROR_VALID (1<<13) |
Definition at line 4020 of file i915_reg.h.
#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) |
Definition at line 4037 of file i915_reg.h.
#define GEN7_ROW_CHICKEN2 0xe4f4 |
Definition at line 4039 of file i915_reg.h.
#define GEN7_ROW_CHICKEN2_GT2 0xf4f4 |
Definition at line 4040 of file i915_reg.h.
#define GEN7_ROW_INSTDONE 0x0e164 |
Definition at line 454 of file i915_reg.h.
#define GEN7_RP_DOWN_IDLE_AVG (0x2<<0) |
Definition at line 3945 of file i915_reg.h.
#define GEN7_SAMPLER_INSTDONE 0x0e160 |
Definition at line 453 of file i915_reg.h.
#define GEN7_SC_INSTDONE 0x07100 |
Definition at line 452 of file i915_reg.h.
#define GEN7_SO_WRITE_OFFSET | ( | n | ) | (0x5280 + (n) * 4) |
Definition at line 4088 of file i915_reg.h.
#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 |
Definition at line 3198 of file i915_reg.h.
#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) |
Definition at line 3199 of file i915_reg.h.
#define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) |
Definition at line 3906 of file i915_reg.h.
#define GEN7_UCGCTL4 0x940c |
Definition at line 3911 of file i915_reg.h.
#define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) |
Definition at line 3905 of file i915_reg.h.
#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C |
Definition at line 3188 of file i915_reg.h.
#define GEN7_WA_L3_CHICKEN_MODE 0x20000000 |
Definition at line 3192 of file i915_reg.h.
#define GFX_FLSH_CNTL 0x02170 /* 915+ only */ |
Definition at line 647 of file i915_reg.h.
#define GFX_FLSH_CNTL_EN (1<<0) |
Definition at line 649 of file i915_reg.h.
#define GFX_FLSH_CNTL_GEN6 0x101008 |
Definition at line 648 of file i915_reg.h.
#define GFX_INSTR | ( | opcode, | |
flags | |||
) | ((0x3 << 29) | ((opcode) << 24) | (flags)) |
Definition at line 242 of file i915_reg.h.
#define GFX_MODE 0x02520 |
Definition at line 508 of file i915_reg.h.
#define GFX_MODE_GEN7 0x0229c |
Definition at line 509 of file i915_reg.h.
#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) |
Definition at line 257 of file i915_reg.h.
#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) |
Definition at line 261 of file i915_reg.h.
#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) |
Definition at line 260 of file i915_reg.h.
#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) |
Definition at line 262 of file i915_reg.h.
#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) |
Definition at line 263 of file i915_reg.h.
#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) |
Definition at line 249 of file i915_reg.h.
#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) |
Definition at line 259 of file i915_reg.h.
#define GFX_OP_PIPE_CONTROL | ( | len | ) | ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) |
Definition at line 280 of file i915_reg.h.
#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) |
Definition at line 244 of file i915_reg.h.
#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
Definition at line 245 of file i915_reg.h.
#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
Definition at line 255 of file i915_reg.h.
#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) |
Definition at line 250 of file i915_reg.h.
#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) |
Definition at line 256 of file i915_reg.h.
#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) |
Definition at line 258 of file i915_reg.h.
#define GFX_PPGTT_ENABLE (1<<9) |
Definition at line 516 of file i915_reg.h.
#define GFX_PSMI_GRANULARITY (1<<10) |
Definition at line 515 of file i915_reg.h.
#define GFX_REPLAY_MODE (1<<11) |
Definition at line 514 of file i915_reg.h.
#define GFX_RUN_LIST_ENABLE (1<<15) |
Definition at line 511 of file i915_reg.h.
#define GFX_SURFACE_FAULT_ENABLE (1<<12) |
Definition at line 513 of file i915_reg.h.
#define GFX_TLB_INVALIDATE_ALWAYS (1<<13) |
Definition at line 512 of file i915_reg.h.
#define GM45_ERROR_CP_PRIV (1<<3) |
Definition at line 555 of file i915_reg.h.
#define GM45_ERROR_MEM_PRIV (1<<4) |
Definition at line 553 of file i915_reg.h.
#define GM45_ERROR_PAGE_TABLE (1<<5) |
Definition at line 552 of file i915_reg.h.
#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) |
Definition at line 45 of file i915_reg.h.
#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) |
Definition at line 46 of file i915_reg.h.
#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) |
Definition at line 47 of file i915_reg.h.
#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) |
Definition at line 48 of file i915_reg.h.
#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) |
Definition at line 44 of file i915_reg.h.
#define GMBUS0 0x5100 /* clock/port select */ |
Definition at line 824 of file i915_reg.h.
#define GMBUS1 0x5104 /* command/status */ |
Definition at line 841 of file i915_reg.h.
#define GMBUS2 0x5108 /* status */ |
Definition at line 854 of file i915_reg.h.
#define GMBUS3 0x510c /* data buffer bytes 3-0 */ |
Definition at line 862 of file i915_reg.h.
#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ |
Definition at line 863 of file i915_reg.h.
#define GMBUS5 0x5120 /* byte index */ |
Definition at line 869 of file i915_reg.h.
#define GMBUS_2BYTE_INDEX_EN (1UL<<31) |
Definition at line 870 of file i915_reg.h.
#define GMBUS_ACTIVE (1<<9) |
Definition at line 861 of file i915_reg.h.
#define GMBUS_BYTE_COUNT_SHIFT 16 |
Definition at line 849 of file i915_reg.h.
#define GMBUS_CYCLE_INDEX (2<<25) |
Definition at line 847 of file i915_reg.h.
#define GMBUS_CYCLE_NONE (0<<25) |
Definition at line 845 of file i915_reg.h.
#define GMBUS_CYCLE_STOP (4<<25) |
Definition at line 848 of file i915_reg.h.
#define GMBUS_CYCLE_WAIT (1<<25) |
Definition at line 846 of file i915_reg.h.
#define GMBUS_ENT (1<<29) /* enable timeout */ |
Definition at line 844 of file i915_reg.h.
#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ |
Definition at line 830 of file i915_reg.h.
#define GMBUS_HW_RDY (1<<11) |
Definition at line 859 of file i915_reg.h.
#define GMBUS_HW_RDY_EN (1<<0) |
Definition at line 868 of file i915_reg.h.
#define GMBUS_HW_WAIT_EN (1<<1) |
Definition at line 867 of file i915_reg.h.
#define GMBUS_HW_WAIT_PHASE (1<<14) |
Definition at line 856 of file i915_reg.h.
#define GMBUS_IDLE_EN (1<<2) |
Definition at line 866 of file i915_reg.h.
#define GMBUS_INT (1<<12) |
Definition at line 858 of file i915_reg.h.
#define GMBUS_INUSE (1<<15) |
Definition at line 855 of file i915_reg.h.
#define GMBUS_NAK_EN (1<<3) |
Definition at line 865 of file i915_reg.h.
#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) |
Definition at line 839 of file i915_reg.h.
#define GMBUS_PORT_DISABLED 0 |
Definition at line 831 of file i915_reg.h.
#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ |
Definition at line 836 of file i915_reg.h.
#define GMBUS_PORT_DPC 4 /* HDMIC */ |
Definition at line 835 of file i915_reg.h.
#define GMBUS_PORT_DPD 6 /* HDMID */ |
Definition at line 837 of file i915_reg.h.
#define GMBUS_PORT_MASK 7 |
Definition at line 840 of file i915_reg.h.
#define GMBUS_PORT_PANEL 3 |
Definition at line 834 of file i915_reg.h.
#define GMBUS_PORT_RESERVED 7 /* 7 reserved */ |
Definition at line 838 of file i915_reg.h.
#define GMBUS_PORT_SSC 1 |
Definition at line 832 of file i915_reg.h.
#define GMBUS_PORT_VGADDC 2 |
Definition at line 833 of file i915_reg.h.
#define GMBUS_RATE_100KHZ (0<<8) |
Definition at line 825 of file i915_reg.h.
#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ |
Definition at line 828 of file i915_reg.h.
#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ |
Definition at line 827 of file i915_reg.h.
#define GMBUS_RATE_50KHZ (1<<8) |
Definition at line 826 of file i915_reg.h.
#define GMBUS_RATE_MASK (3<<8) |
Definition at line 829 of file i915_reg.h.
#define GMBUS_SATOER (1<<10) |
Definition at line 860 of file i915_reg.h.
#define GMBUS_SLAVE_ADDR_SHIFT 1 |
Definition at line 851 of file i915_reg.h.
#define GMBUS_SLAVE_INDEX_SHIFT 8 |
Definition at line 850 of file i915_reg.h.
#define GMBUS_SLAVE_READ (1<<0) |
Definition at line 852 of file i915_reg.h.
#define GMBUS_SLAVE_TIMEOUT_EN (1<<4) |
Definition at line 864 of file i915_reg.h.
#define GMBUS_SLAVE_WRITE (0<<0) |
Definition at line 853 of file i915_reg.h.
#define GMBUS_STALL_TIMEOUT (1<<13) |
Definition at line 857 of file i915_reg.h.
#define GMBUS_SW_CLR_INT (1UL<<31) |
Definition at line 842 of file i915_reg.h.
#define GMBUS_SW_RDY (1<<30) |
Definition at line 843 of file i915_reg.h.
#define GPIO_CLOCK_DIR_IN (0 << 1) |
Definition at line 810 of file i915_reg.h.
#define GPIO_CLOCK_DIR_MASK (1 << 0) |
Definition at line 809 of file i915_reg.h.
#define GPIO_CLOCK_DIR_OUT (1 << 1) |
Definition at line 811 of file i915_reg.h.
#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) |
Definition at line 815 of file i915_reg.h.
#define GPIO_CLOCK_VAL_IN (1 << 4) |
Definition at line 814 of file i915_reg.h.
#define GPIO_CLOCK_VAL_MASK (1 << 2) |
Definition at line 812 of file i915_reg.h.
#define GPIO_CLOCK_VAL_OUT (1 << 3) |
Definition at line 813 of file i915_reg.h.
#define GPIO_DATA_DIR_IN (0 << 9) |
Definition at line 817 of file i915_reg.h.
#define GPIO_DATA_DIR_MASK (1 << 8) |
Definition at line 816 of file i915_reg.h.
#define GPIO_DATA_DIR_OUT (1 << 9) |
Definition at line 818 of file i915_reg.h.
#define GPIO_DATA_PULLUP_DISABLE (1 << 13) |
Definition at line 822 of file i915_reg.h.
#define GPIO_DATA_VAL_IN (1 << 12) |
Definition at line 821 of file i915_reg.h.
#define GPIO_DATA_VAL_MASK (1 << 10) |
Definition at line 819 of file i915_reg.h.
#define GPIO_DATA_VAL_OUT (1 << 11) |
Definition at line 820 of file i915_reg.h.
#define GPIOA 0x5010 |
Definition at line 801 of file i915_reg.h.
#define GPIOB 0x5014 |
Definition at line 802 of file i915_reg.h.
#define GPIOC 0x5018 |
Definition at line 803 of file i915_reg.h.
#define GPIOD 0x501c |
Definition at line 804 of file i915_reg.h.
#define GPIOE 0x5020 |
Definition at line 805 of file i915_reg.h.
#define GPIOF 0x5024 |
Definition at line 806 of file i915_reg.h.
#define GPIOG 0x5028 |
Definition at line 807 of file i915_reg.h.
#define GPIOH 0x502c |
Definition at line 808 of file i915_reg.h.
#define GRDOM_FULL (0<<2) |
Definition at line 68 of file i915_reg.h.
#define GRDOM_MEDIA (3<<2) |
Definition at line 70 of file i915_reg.h.
#define GRDOM_RENDER (1<<2) |
Definition at line 69 of file i915_reg.h.
#define GRDOM_RESET_ENABLE (1<<0) |
Definition at line 71 of file i915_reg.h.
#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) |
Definition at line 1144 of file i915_reg.h.
#define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */ |
Definition at line 3143 of file i915_reg.h.
#define GT_FIFO_CPU_ERROR_MASK 7 |
Definition at line 3892 of file i915_reg.h.
#define GT_FIFO_FREE_ENTRIES 0x120008 |
Definition at line 3897 of file i915_reg.h.
#define GT_FIFO_IARDERR (1<<0) |
Definition at line 3895 of file i915_reg.h.
#define GT_FIFO_IAWRERR (1<<1) |
Definition at line 3894 of file i915_reg.h.
#define GT_FIFO_NUM_RESERVED_ENTRIES 20 |
Definition at line 3898 of file i915_reg.h.
#define GT_FIFO_OVFERR (1<<2) |
Definition at line 3893 of file i915_reg.h.
#define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25) |
Definition at line 3139 of file i915_reg.h.
#define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) |
Definition at line 3138 of file i915_reg.h.
#define GT_GEN6_BLT_USER_INTERRUPT (1 << 22) |
Definition at line 3140 of file i915_reg.h.
#define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15) |
Definition at line 3141 of file i915_reg.h.
#define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) |
Definition at line 3142 of file i915_reg.h.
#define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5) |
Definition at line 3144 of file i915_reg.h.
#define GT_PIPE_NOTIFY (1 << 4) |
Definition at line 3145 of file i915_reg.h.
#define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3) |
Definition at line 3146 of file i915_reg.h.
#define GT_SYNC_STATUS (1 << 2) |
Definition at line 3147 of file i915_reg.h.
#define GT_USER_INTERRUPT (1 << 0) |
Definition at line 3148 of file i915_reg.h.
#define GTFIFODBG 0x120000 |
Definition at line 3891 of file i915_reg.h.
#define GTIER 0x4401c |
Definition at line 3153 of file i915_reg.h.
#define GTIIR 0x44018 |
Definition at line 3152 of file i915_reg.h.
#define GTIMR 0x44014 |
Definition at line 3151 of file i915_reg.h.
#define GTISR 0x44010 |
Definition at line 3150 of file i915_reg.h.
#define HBLANK | ( | trans | ) | _TRANSCODER(trans, _HBLANK_A, _HBLANK_B) |
Definition at line 1250 of file i915_reg.h.
#define HDMI_MODE_SELECT (1 << 9) |
Definition at line 3718 of file i915_reg.h.
#define HDMIB 0xe1140 |
Definition at line 3705 of file i915_reg.h.
#define HDMIB_HOTPLUG_INT_EN (1 << 29) |
Definition at line 1307 of file i915_reg.h.
#define HDMIB_HOTPLUG_INT_STATUS (3 << 17) |
Definition at line 1347 of file i915_reg.h.
#define HDMIB_HOTPLUG_LIVE_STATUS (1 << 29) |
Definition at line 1342 of file i915_reg.h.
#define HDMIC 0xe1150 |
Definition at line 3729 of file i915_reg.h.
#define HDMIC_HOTPLUG_INT_EN (1 << 28) |
Definition at line 1309 of file i915_reg.h.
#define HDMIC_HOTPLUG_INT_STATUS (3 << 19) |
Definition at line 1346 of file i915_reg.h.
#define HDMIC_HOTPLUG_LIVE_STATUS (1 << 28) |
Definition at line 1343 of file i915_reg.h.
#define HDMID 0xe1160 |
Definition at line 3730 of file i915_reg.h.
#define HDMID_HOTPLUG_INT_EN (1 << 27) |
Definition at line 1311 of file i915_reg.h.
#define HDMID_HOTPLUG_INT_STATUS (3 << 21) |
Definition at line 1345 of file i915_reg.h.
#define HDMID_HOTPLUG_LIVE_STATUS (1 << 27) |
Definition at line 1344 of file i915_reg.h.
#define HEAD_ADDR 0x001FFFFC |
Definition at line 436 of file i915_reg.h.
#define HEAD_WRAP_COUNT 0xFFE00000 |
Definition at line 434 of file i915_reg.h.
#define HEAD_WRAP_ONE 0x00200000 |
Definition at line 435 of file i915_reg.h.
#define HIST_MODE_HSV (1<<24) |
Definition at line 1643 of file i915_reg.h.
#define HIST_MODE_YUV (0<<24) |
Definition at line 1642 of file i915_reg.h.
#define HORIZ_AUTO_SCALE (1 << 5) |
Definition at line 1563 of file i915_reg.h.
#define HORIZ_INTERP_BILINEAR (1 << 6) |
Definition at line 1561 of file i915_reg.h.
#define HORIZ_INTERP_DISABLE (0 << 6) |
Definition at line 1560 of file i915_reg.h.
#define HORIZ_INTERP_MASK (3 << 6) |
Definition at line 1562 of file i915_reg.h.
#define HPLLCC 0xc0 /* 855 only */ |
Definition at line 32 of file i915_reg.h.
#define HSW_AUD_CFG | ( | pipe | ) |
Definition at line 4113 of file i915_reg.h.
#define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */ |
Definition at line 4111 of file i915_reg.h.
#define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */ |
Definition at line 4112 of file i915_reg.h.
#define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */ |
Definition at line 4130 of file i915_reg.h.
#define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */ |
Definition at line 4131 of file i915_reg.h.
#define HSW_AUD_DIP_ELD_CTRL | ( | pipe | ) |
Definition at line 4125 of file i915_reg.h.
#define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */ |
Definition at line 4123 of file i915_reg.h.
#define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */ |
Definition at line 4124 of file i915_reg.h.
#define HSW_AUD_EDID_DATA | ( | pipe | ) |
Definition at line 4139 of file i915_reg.h.
#define HSW_AUD_EDID_DATA_A 0x65050 |
Definition at line 4137 of file i915_reg.h.
#define HSW_AUD_EDID_DATA_B 0x65150 |
Definition at line 4138 of file i915_reg.h.
#define HSW_AUD_MISC_CTRL | ( | pipe | ) |
Definition at line 4119 of file i915_reg.h.
#define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */ |
Definition at line 4117 of file i915_reg.h.
#define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */ |
Definition at line 4118 of file i915_reg.h.
#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */ |
Definition at line 4144 of file i915_reg.h.
#define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */ |
Definition at line 4143 of file i915_reg.h.
#define HSW_CDCLK_LIMIT (1 << 24) |
Definition at line 3202 of file i915_reg.h.
#define HSW_CXT_POWER_SIZE | ( | ctx_reg | ) | ((ctx_reg >> 26) & 0x3f) |
Definition at line 1201 of file i915_reg.h.
#define HSW_CXT_RENDER_SIZE | ( | ctx_reg | ) | ((ctx_reg >> 15) & 0xff) |
Definition at line 1203 of file i915_reg.h.
#define HSW_CXT_RING_SIZE | ( | ctx_reg | ) | ((ctx_reg >> 23) & 0x7) |
Definition at line 1202 of file i915_reg.h.
#define HSW_CXT_TOTAL_SIZE | ( | ctx_reg | ) |
Definition at line 1204 of file i915_reg.h.
#define HSW_FUSE_STRAP 0x42014 |
Definition at line 3201 of file i915_reg.h.
#define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */ |
Definition at line 4159 of file i915_reg.h.
#define HSW_PWR_WELL_CTL2 0x45404 /* Driver */ |
Definition at line 4160 of file i915_reg.h.
#define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */ |
Definition at line 4161 of file i915_reg.h.
#define HSW_PWR_WELL_CTL4 0x4540C /* Debug */ |
Definition at line 4162 of file i915_reg.h.
#define HSW_PWR_WELL_CTL5 0x45410 |
Definition at line 4165 of file i915_reg.h.
#define HSW_PWR_WELL_CTL6 0x45414 |
Definition at line 4169 of file i915_reg.h.
#define HSW_PWR_WELL_ENABLE (1UL<<31) |
Definition at line 4163 of file i915_reg.h.
#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1UL<<31) |
Definition at line 4166 of file i915_reg.h.
#define HSW_PWR_WELL_FORCE_ON (1<<19) |
Definition at line 4168 of file i915_reg.h.
#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) |
Definition at line 4167 of file i915_reg.h.
#define HSW_PWR_WELL_STATE (1<<30) |
Definition at line 4164 of file i915_reg.h.
#define HSW_TVIDEO_DIP_AVI_DATA | ( | pipe | ) | _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B) |
Definition at line 3479 of file i915_reg.h.
#define HSW_TVIDEO_DIP_CTL | ( | pipe | ) | _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B) |
Definition at line 3477 of file i915_reg.h.
#define HSW_TVIDEO_DIP_GCP | ( | pipe | ) | _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B) |
Definition at line 3483 of file i915_reg.h.
#define HSW_TVIDEO_DIP_SPD_DATA | ( | pipe | ) | _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B) |
Definition at line 3481 of file i915_reg.h.
#define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 |
Definition at line 3452 of file i915_reg.h.
#define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 |
Definition at line 3465 of file i915_reg.h.
#define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 |
Definition at line 3457 of file i915_reg.h.
#define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 |
Definition at line 3470 of file i915_reg.h.
#define HSW_VIDEO_DIP_CTL_A 0x60200 |
Definition at line 3451 of file i915_reg.h.
#define HSW_VIDEO_DIP_CTL_B 0x61200 |
Definition at line 3464 of file i915_reg.h.
#define HSW_VIDEO_DIP_GCP_A 0x60210 |
Definition at line 3462 of file i915_reg.h.
#define HSW_VIDEO_DIP_GCP_B 0x61210 |
Definition at line 3475 of file i915_reg.h.
#define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 |
Definition at line 3455 of file i915_reg.h.
#define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 |
Definition at line 3468 of file i915_reg.h.
#define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 |
Definition at line 3460 of file i915_reg.h.
#define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 |
Definition at line 3473 of file i915_reg.h.
#define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 |
Definition at line 3454 of file i915_reg.h.
#define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 |
Definition at line 3467 of file i915_reg.h.
#define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 |
Definition at line 3459 of file i915_reg.h.
#define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 |
Definition at line 3472 of file i915_reg.h.
#define HSW_VIDEO_DIP_VS_DATA_A 0x60260 |
Definition at line 3453 of file i915_reg.h.
#define HSW_VIDEO_DIP_VS_DATA_B 0x61260 |
Definition at line 3466 of file i915_reg.h.
#define HSW_VIDEO_DIP_VS_ECC_A 0x60280 |
Definition at line 3458 of file i915_reg.h.
#define HSW_VIDEO_DIP_VS_ECC_B 0x61280 |
Definition at line 3471 of file i915_reg.h.
#define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 |
Definition at line 3456 of file i915_reg.h.
#define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 |
Definition at line 3469 of file i915_reg.h.
#define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 |
Definition at line 3461 of file i915_reg.h.
#define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 |
Definition at line 3474 of file i915_reg.h.
#define HSYNC | ( | trans | ) | _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) |
Definition at line 1251 of file i915_reg.h.
#define HSYNC_ACTIVE_HIGH (1 << 3) |
Definition at line 3723 of file i915_reg.h.
#define HTOTAL | ( | trans | ) | _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B) |
Definition at line 1249 of file i915_reg.h.
#define HWS_ADDRESS_MASK 0xfffff000 |
Definition at line 466 of file i915_reg.h.
#define HWS_PGA 0x02080 |
Definition at line 465 of file i915_reg.h.
#define HWS_START_ADDRESS_SHIFT 4 |
Definition at line 467 of file i915_reg.h.
#define HWSTAM 0x02098 |
Definition at line 474 of file i915_reg.h.
#define I830_FENCE_MAX_PITCH_VAL 6 |
Definition at line 377 of file i915_reg.h.
#define I830_FENCE_MAX_SIZE_VAL (1<<8) |
Definition at line 378 of file i915_reg.h.
#define I830_FENCE_PITCH_SHIFT 4 |
Definition at line 374 of file i915_reg.h.
#define I830_FENCE_REG_VALID (1<<0) |
Definition at line 375 of file i915_reg.h.
#define I830_FENCE_SIZE_BITS | ( | size | ) | ((ffs((size) >> 19) - 1) << 8) |
Definition at line 373 of file i915_reg.h.
#define I830_FENCE_START_MASK 0x07f80000 |
Definition at line 371 of file i915_reg.h.
#define I830_FENCE_TILING_Y_SHIFT 12 |
Definition at line 372 of file i915_reg.h.
#define I830_FIFO_LINE_SIZE 32 |
Definition at line 2539 of file i915_reg.h.
#define I830_FIFO_SIZE 95 |
Definition at line 2547 of file i915_reg.h.
#define I855GM_FIFO_SIZE 127 /* In cachelines */ |
Definition at line 2546 of file i915_reg.h.
#define I915_ASLE_INTERRUPT (1<<0) |
Definition at line 548 of file i915_reg.h.
#define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) |
Definition at line 1098 of file i915_reg.h.
#define I915_BSD_USER_INTERRUPT (1<<25) |
Definition at line 549 of file i915_reg.h.
#define I915_BY_CLOCK_GATE_DISABLE (1 << 0) |
Definition at line 1111 of file i915_reg.h.
#define I915_CC_CLOCK_GATE_DISABLE (1 << 1) |
Definition at line 1110 of file i915_reg.h.
#define I915_DEBUG_INTERRUPT (1<<2) |
Definition at line 546 of file i915_reg.h.
#define I915_DI_CLOCK_GATE_DISABLE (1 << 8) |
Definition at line 1103 of file i915_reg.h.
#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) |
Definition at line 543 of file i915_reg.h.
#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) |
Definition at line 542 of file i915_reg.h.
#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) |
Definition at line 545 of file i915_reg.h.
#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) |
Definition at line 544 of file i915_reg.h.
#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) |
Definition at line 538 of file i915_reg.h.
#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) |
Definition at line 539 of file i915_reg.h.
#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) |
Definition at line 541 of file i915_reg.h.
#define I915_DISPLAY_PORT_INTERRUPT (1<<17) |
Definition at line 533 of file i915_reg.h.
#define I915_DM_CLOCK_GATE_DISABLE (1 << 3) |
Definition at line 1108 of file i915_reg.h.
#define I915_ERROR_INSTRUCTION (1<<0) |
Definition at line 557 of file i915_reg.h.
#define I915_ERROR_MEMORY_REFRESH (1<<1) |
Definition at line 556 of file i915_reg.h.
#define I915_ERROR_PAGE_TABLE (1<<4) |
Definition at line 554 of file i915_reg.h.
#define I915_FENCE_MAX_PITCH_VAL 4 |
Definition at line 376 of file i915_reg.h.
#define I915_FENCE_SIZE_BITS | ( | size | ) | ((ffs((size) >> 20) - 1) << 8) |
Definition at line 381 of file i915_reg.h.
#define I915_FENCE_START_MASK 0x0ff00000 |
Definition at line 380 of file i915_reg.h.
#define I915_FIFO_LINE_SIZE 64 |
Definition at line 2538 of file i915_reg.h.
#define I915_FIFO_SIZE 95 |
Definition at line 2545 of file i915_reg.h.
#define I915_FL_CLOCK_GATE_DISABLE (1 << 4) |
Definition at line 1107 of file i915_reg.h.
#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) |
Definition at line 60 of file i915_reg.h.
#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) |
Definition at line 61 of file i915_reg.h.
#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) |
Definition at line 62 of file i915_reg.h.
#define I915_GC_RENDER_CLOCK_MASK (7 << 0) |
Definition at line 59 of file i915_reg.h.
#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ |
Definition at line 535 of file i915_reg.h.
#define I915_HI_DISPBASE | ( | val | ) | (val & DISP_BASEADDR_MASK) |
Definition at line 2773 of file i915_reg.h.
#define I915_HWB_OOM_INTERRUPT (1<<13) |
Definition at line 536 of file i915_reg.h.
#define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) |
Definition at line 1101 of file i915_reg.h.
#define I915_LO_DISPBASE | ( | val | ) | (val & ~DISP_BASEADDR_MASK) |
Definition at line 2772 of file i915_reg.h.
#define I915_MAX_WM 0x3f |
Definition at line 2551 of file i915_reg.h.
#define I915_MODIFY_DISPBASE | ( | reg, | |
gfx_addr | |||
) | (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg)))) |
Definition at line 2774 of file i915_reg.h.
#define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) |
Definition at line 1097 of file i915_reg.h.
#define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) |
Definition at line 1095 of file i915_reg.h.
#define I915_NUM_INSTDONE_REG 4 |
Definition at line 455 of file i915_reg.h.
#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) |
Definition at line 540 of file i915_reg.h.
#define I915_PI_CLOCK_GATE_DISABLE (1 << 9) |
Definition at line 1102 of file i915_reg.h.
#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
Definition at line 532 of file i915_reg.h.
#define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) |
Definition at line 1105 of file i915_reg.h.
#define I915_PS_CLOCK_GATE_DISABLE (1 << 2) |
Definition at line 1109 of file i915_reg.h.
#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) |
Definition at line 534 of file i915_reg.h.
#define I915_SC_CLOCK_GATE_DISABLE (1 << 5) |
Definition at line 1106 of file i915_reg.h.
#define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) |
Definition at line 1099 of file i915_reg.h.
#define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) |
Definition at line 1104 of file i915_reg.h.
#define I915_SYNC_STATUS_INTERRUPT (1<<12) |
Definition at line 537 of file i915_reg.h.
#define I915_USER_INTERRUPT (1<<1) |
Definition at line 547 of file i915_reg.h.
#define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) |
Definition at line 1096 of file i915_reg.h.
#define I915_WM_CLOCK_GATE_DISABLE (1 << 11) |
Definition at line 1100 of file i915_reg.h.
#define I945_FIFO_SIZE 127 |
Definition at line 2544 of file i915_reg.h.
#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) |
Definition at line 55 of file i915_reg.h.
#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) |
Definition at line 56 of file i915_reg.h.
#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) |
Definition at line 57 of file i915_reg.h.
#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) |
Definition at line 58 of file i915_reg.h.
#define I945_GC_RENDER_CLOCK_MASK (7 << 0) |
Definition at line 54 of file i915_reg.h.
#define I965_CURSOR_DFT_WM 8 |
Definition at line 2567 of file i915_reg.h.
#define I965_CURSOR_FIFO 64 |
Definition at line 2565 of file i915_reg.h.
#define I965_CURSOR_MAX_WM 32 |
Definition at line 2566 of file i915_reg.h.
#define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) |
Definition at line 1117 of file i915_reg.h.
#define I965_DG_CLOCK_GATE_DISABLE (1 << 3) |
Definition at line 1137 of file i915_reg.h.
#define I965_DM_CLOCK_GATE_DISABLE (1 << 0) |
Definition at line 1140 of file i915_reg.h.
#define I965_EM_CLOCK_GATE_DISABLE (1 << 12) |
Definition at line 1132 of file i915_reg.h.
#define I965_EU_CLOCK_GATE_DISABLE (1 << 21) |
Definition at line 1124 of file i915_reg.h.
#define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) |
Definition at line 1128 of file i915_reg.h.
#define I965_FENCE_MAX_PITCH_VAL 0x0400 |
Definition at line 387 of file i915_reg.h.
#define I965_FENCE_PITCH_SHIFT 2 |
Definition at line 384 of file i915_reg.h.
#define I965_FENCE_REG_VALID (1<<0) |
Definition at line 386 of file i915_reg.h.
#define I965_FENCE_TILING_Y_SHIFT 1 |
Definition at line 385 of file i915_reg.h.
#define I965_FIFO_SIZE 512 |
Definition at line 2543 of file i915_reg.h.
#define I965_FT_CLOCK_GATE_DISABLE (1 << 1) |
Definition at line 1139 of file i915_reg.h.
#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) |
Definition at line 50 of file i915_reg.h.
#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) |
Definition at line 51 of file i915_reg.h.
#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) |
Definition at line 52 of file i915_reg.h.
#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) |
Definition at line 53 of file i915_reg.h.
#define I965_GC_RENDER_CLOCK_MASK (0xf << 0) |
Definition at line 49 of file i915_reg.h.
#define I965_GDRST 0xc0 /* PCI config register */ |
Definition at line 66 of file i915_reg.h.
#define I965_GW_CLOCK_GATE_DISABLE (1 << 25) |
Definition at line 1119 of file i915_reg.h.
#define I965_IC_CLOCK_GATE_DISABLE (1 << 22) |
Definition at line 1123 of file i915_reg.h.
#define I965_IF_CLOCK_GATE_DISABLE (1 << 20) |
Definition at line 1125 of file i915_reg.h.
#define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) |
This bit must always be set on 965G.
Definition at line 1122 of file i915_reg.h.
#define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) |
Definition at line 1129 of file i915_reg.h.
#define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) |
Definition at line 1130 of file i915_reg.h.
#define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) |
Definition at line 1131 of file i915_reg.h.
#define I965_MT_CLOCK_GATE_DISABLE (1 << 5) |
Definition at line 1135 of file i915_reg.h.
#define I965_PIPECONF_ACTIVE (1<<30) |
Definition at line 2371 of file i915_reg.h.
#define I965_PL_CLOCK_GATE_DISABLE (1 << 4) |
Definition at line 1136 of file i915_reg.h.
#define I965_QC_CLOCK_GATE_DISABLE (1 << 2) |
Definition at line 1138 of file i915_reg.h.
#define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) |
This bit must always be set on 965G/965GM.
Definition at line 1115 of file i915_reg.h.
#define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) |
Definition at line 1116 of file i915_reg.h.
#define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) |
Definition at line 1113 of file i915_reg.h.
#define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) |
Definition at line 1118 of file i915_reg.h.
#define I965_SI_CLOCK_GATE_DISABLE (1 << 6) |
Definition at line 1134 of file i915_reg.h.
#define I965_SO_CLOCK_GATE_DISABLE (1 << 17) |
Definition at line 1127 of file i915_reg.h.
#define I965_TC_CLOCK_GATE_DISABLE (1 << 19) |
Definition at line 1126 of file i915_reg.h.
#define I965_TD_CLOCK_GATE_DISABLE (1 << 24) |
Definition at line 1120 of file i915_reg.h.
#define I965_UC_CLOCK_GATE_DISABLE (1 << 11) |
Definition at line 1133 of file i915_reg.h.
#define IBX_AUD_CFG | ( | pipe | ) |
Definition at line 4092 of file i915_reg.h.
#define IBX_AUD_CNTL_ST | ( | pipe | ) |
Definition at line 4062 of file i915_reg.h.
#define IBX_AUD_CNTL_ST2 0xE20C0 |
Definition at line 4068 of file i915_reg.h.
#define IBX_AUD_CNTL_ST_A 0xE20B4 |
Definition at line 4060 of file i915_reg.h.
#define IBX_AUD_CNTL_ST_B 0xE21B4 |
Definition at line 4061 of file i915_reg.h.
#define IBX_AUD_CONFIG_A 0xe2000 |
Definition at line 4090 of file i915_reg.h.
#define IBX_AUD_CONFIG_B 0xe2100 |
Definition at line 4091 of file i915_reg.h.
#define IBX_CP_READYB (1 << 1) |
Definition at line 4070 of file i915_reg.h.
#define IBX_ELD_ACK (1 << 4) |
Definition at line 4067 of file i915_reg.h.
#define IBX_ELD_ADDRESS (0x1f << 5) |
Definition at line 4066 of file i915_reg.h.
#define IBX_ELD_BUFFER_SIZE (0x1f << 10) |
Definition at line 4065 of file i915_reg.h.
#define IBX_ELD_VALIDB (1 << 0) |
Definition at line 4069 of file i915_reg.h.
#define IBX_HDMIW_HDMIEDID | ( | pipe | ) |
Definition at line 4057 of file i915_reg.h.
#define IBX_HDMIW_HDMIEDID_A 0xE2050 |
Definition at line 4055 of file i915_reg.h.
#define IBX_HDMIW_HDMIEDID_B 0xE2150 |
Definition at line 4056 of file i915_reg.h.
#define IER 0x020a0 |
Definition at line 521 of file i915_reg.h.
#define IIR 0x020a4 |
Definition at line 522 of file i915_reg.h.
#define ILK_CURSOR_DFT_SRWM 8 |
Definition at line 2620 of file i915_reg.h.
#define ILK_CURSOR_DFTWM 8 |
Definition at line 2613 of file i915_reg.h.
#define ILK_CURSOR_FIFO 32 |
Definition at line 2611 of file i915_reg.h.
#define ILK_CURSOR_MAX_SRWM 0x3f |
Definition at line 2619 of file i915_reg.h.
#define ILK_CURSOR_MAXWM 16 |
Definition at line 2612 of file i915_reg.h.
#define ILK_CURSOR_SR_FIFO 64 |
Definition at line 2618 of file i915_reg.h.
#define ILK_DESKTOP (1<<23) |
Definition at line 3166 of file i915_reg.h.
#define ILK_DISPLAY_CHICKEN1 0x42000 |
Definition at line 785 of file i915_reg.h.
#define ILK_DISPLAY_CHICKEN2 0x42004 |
Definition at line 3155 of file i915_reg.h.
#define ILK_DISPLAY_CHICKEN_FUSES 0x42014 |
Definition at line 3160 of file i915_reg.h.
#define ILK_DISPLAY_DEBUG_DISABLE (1<<29) |
Definition at line 3163 of file i915_reg.h.
#define ILK_DISPLAY_DFT_SRWM 0x3f |
Definition at line 2617 of file i915_reg.h.
#define ILK_DISPLAY_DFTWM 8 |
Definition at line 2610 of file i915_reg.h.
#define ILK_DISPLAY_FIFO 128 |
Definition at line 2608 of file i915_reg.h.
#define ILK_DISPLAY_MAX_SRWM 0x1ff |
Definition at line 2616 of file i915_reg.h.
#define ILK_DISPLAY_MAXWM 64 |
Definition at line 2609 of file i915_reg.h.
#define ILK_DISPLAY_SR_FIFO 512 |
Definition at line 2615 of file i915_reg.h.
#define ILK_DPARB_GATE (1<<22) |
Definition at line 3158 of file i915_reg.h.
#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) |
Definition at line 3173 of file i915_reg.h.
#define ILK_DPFC_CB_BASE 0x43200 |
Definition at line 774 of file i915_reg.h.
#define ILK_DPFC_CHICKEN 0x43224 |
Definition at line 781 of file i915_reg.h.
#define ILK_DPFC_CONTROL 0x43208 |
Definition at line 775 of file i915_reg.h.
#define ILK_DPFC_FENCE_YOFF 0x43218 |
Definition at line 780 of file i915_reg.h.
#define ILK_DPFC_RECOMP_CTL 0x4320c |
Definition at line 778 of file i915_reg.h.
#define ILK_DPFC_STATUS 0x43210 |
Definition at line 779 of file i915_reg.h.
#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) |
Definition at line 3171 of file i915_reg.h.
#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) |
Definition at line 3170 of file i915_reg.h.
#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) |
Definition at line 3172 of file i915_reg.h.
#define ILK_DSPCLK_GATE_D 0x42020 |
Definition at line 3168 of file i915_reg.h.
#define ILK_eDP_A_DISABLE (1<<24) |
Definition at line 3165 of file i915_reg.h.
#define ILK_ELPIN_409_SELECT (1 << 25) |
Definition at line 3157 of file i915_reg.h.
#define ILK_FBC_RT_BASE 0x2128 |
Definition at line 782 of file i915_reg.h.
#define ILK_FBC_RT_VALID (1<<0) |
Definition at line 783 of file i915_reg.h.
#define ILK_FBCQ_DIS (1<<22) |
Definition at line 786 of file i915_reg.h.
#define ILK_FIFO_LINE_SIZE 64 |
Definition at line 2622 of file i915_reg.h.
Definition at line 67 of file i915_reg.h.
#define ILK_HDCP_DISABLE (1<<25) |
Definition at line 3164 of file i915_reg.h.
#define ILK_INTERNAL_DISPLAY_DISABLE (1<<30) |
Definition at line 3162 of file i915_reg.h.
#define ILK_INTERNAL_GRAPHICS_DISABLE (1UL<<31) |
Definition at line 3161 of file i915_reg.h.
#define ILK_LATENCY | ( | shift | ) | (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK) |
Definition at line 2603 of file i915_reg.h.
#define ILK_PABSTRETCH_DIS (1<<21) |
Definition at line 787 of file i915_reg.h.
#define ILK_READ_WM1_LATENCY | ( | ) | ILK_LATENCY(MLTR_WM1_SHIFT) |
Definition at line 2604 of file i915_reg.h.
#define ILK_READ_WM2_LATENCY | ( | ) | ILK_LATENCY(MLTR_WM2_SHIFT) |
Definition at line 2605 of file i915_reg.h.
#define ILK_SRLT_MASK 0x3f |
Definition at line 2602 of file i915_reg.h.
#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) |
Definition at line 3169 of file i915_reg.h.
#define ILK_VSDPFD_FULL (1<<21) |
Definition at line 3159 of file i915_reg.h.
#define IMR 0x020a8 |
Definition at line 523 of file i915_reg.h.
#define INSTDONE 0x02090 |
Definition at line 472 of file i915_reg.h.
#define INSTDONE1 0x0207c /* 965+ only */ |
Definition at line 463 of file i915_reg.h.
#define INSTDONE_I965 0x0206c |
Definition at line 450 of file i915_reg.h.
#define INSTPM 0x020c0 |
Definition at line 558 of file i915_reg.h.
#define INSTPM_AGPBUSY_DIS |
Definition at line 560 of file i915_reg.h.
#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ |
Definition at line 561 of file i915_reg.h.
#define INSTPM_SELF_EN (1<<12) /* 915GM only */ |
Definition at line 559 of file i915_reg.h.
#define INSTPS 0x02070 /* 965+ only */ |
Definition at line 462 of file i915_reg.h.
#define INTEL_AUDIO_DEVBLC 0x80862801 |
Definition at line 4045 of file i915_reg.h.
#define INTEL_AUDIO_DEVCL 0x808629FB |
Definition at line 4044 of file i915_reg.h.
#define INTEL_AUDIO_DEVCTG 0x80862802 |
Definition at line 4046 of file i915_reg.h.
#define INTEL_GMCH_CTRL 0x52 |
Definition at line 20 of file i915_reg.h.
#define INTEL_GMCH_VGA_DISABLE (1 << 1) |
Definition at line 21 of file i915_reg.h.
#define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) |
Definition at line 1084 of file i915_reg.h.
#define IPEHR 0x0208c |
Definition at line 471 of file i915_reg.h.
#define IPEHR_I965 0x02068 |
Definition at line 449 of file i915_reg.h.
#define IPEIR 0x02088 |
Definition at line 470 of file i915_reg.h.
#define IPEIR_I965 0x02064 |
Definition at line 448 of file i915_reg.h.
#define ISR 0x020ac |
Definition at line 524 of file i915_reg.h.
#define IVB_CHICKEN3 0x4200c |
Definition at line 3175 of file i915_reg.h.
#define IVB_GMCH_GMS_MASK 0xf |
Definition at line 28 of file i915_reg.h.
#define IVB_GMCH_GMS_SHIFT 4 |
Definition at line 27 of file i915_reg.h.
#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) |
Definition at line 3195 of file i915_reg.h.
#define LBB 0xf4 |
Definition at line 63 of file i915_reg.h.
#define LCPLL_CD2X_CLOCK_DISABLE (1<<23) |
Definition at line 4355 of file i915_reg.h.
#define LCPLL_CD_CLOCK_DISABLE (1<<25) |
Definition at line 4354 of file i915_reg.h.
#define LCPLL_CD_SOURCE_FCLK (1<<21) |
Definition at line 4356 of file i915_reg.h.
#define LCPLL_CLK_FREQ_450 (0<<26) |
Definition at line 4353 of file i915_reg.h.
#define LCPLL_CLK_FREQ_MASK (3<<26) |
Definition at line 4352 of file i915_reg.h.
#define LCPLL_CTL 0x130040 |
Definition at line 4349 of file i915_reg.h.
#define LCPLL_PLL_DISABLE (1UL<<31) |
Definition at line 4350 of file i915_reg.h.
#define LCPLL_PLL_LOCK (1<<30) |
Definition at line 4351 of file i915_reg.h.
#define LGC_PALETTE | ( | pipe | ) | _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) |
Definition at line 3082 of file i915_reg.h.
#define LM_BURST_LENGTH 0x00000700 |
Definition at line 571 of file i915_reg.h.
#define LM_FIFO_WATERMARK 0x0000001F |
Definition at line 572 of file i915_reg.h.
#define LPT_PWM_GRANULARITY (1<<5) |
Definition at line 3565 of file i915_reg.h.
#define LVDS 0x61180 |
Definition at line 1435 of file i915_reg.h.
#define LVDS 0x61180 |
Definition at line 1435 of file i915_reg.h.
#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) |
Definition at line 1458 of file i915_reg.h.
#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) |
Definition at line 1457 of file i915_reg.h.
#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) |
Definition at line 1459 of file i915_reg.h.
#define LVDS_A3_POWER_DOWN (0 << 6) |
Definition at line 1466 of file i915_reg.h.
#define LVDS_A3_POWER_MASK (3 << 6) |
Definition at line 1465 of file i915_reg.h.
#define LVDS_A3_POWER_UP (3 << 6) |
Definition at line 1467 of file i915_reg.h.
#define LVDS_B0B3_POWER_DOWN (0 << 2) |
Definition at line 1481 of file i915_reg.h.
#define LVDS_B0B3_POWER_MASK (3 << 2) |
Definition at line 1480 of file i915_reg.h.
#define LVDS_B0B3_POWER_UP (3 << 2) |
Definition at line 1482 of file i915_reg.h.
#define LVDS_BORDER_ENABLE (1 << 15) |
Definition at line 3734 of file i915_reg.h.
#define LVDS_BORDER_ENABLE (1 << 15) |
Definition at line 3734 of file i915_reg.h.
#define LVDS_BORDER_ENABLE (1 << 15) |
Definition at line 3734 of file i915_reg.h.
#define LVDS_CLKB_POWER_DOWN (0 << 4) |
Definition at line 1473 of file i915_reg.h.
#define LVDS_CLKB_POWER_MASK (3 << 4) |
Definition at line 1472 of file i915_reg.h.
#define LVDS_CLKB_POWER_UP (3 << 4) |
Definition at line 1474 of file i915_reg.h.
#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) |
Definition at line 3736 of file i915_reg.h.
#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) |
Definition at line 3736 of file i915_reg.h.
#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) |
Definition at line 3737 of file i915_reg.h.
#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) |
Definition at line 3737 of file i915_reg.h.
#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) |
Definition at line 3738 of file i915_reg.h.
#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) |
Definition at line 3738 of file i915_reg.h.
#define LVDS_DETECTED (1 << 1) |
Definition at line 3733 of file i915_reg.h.
#define LVDS_DETECTED (1 << 1) |
Definition at line 3733 of file i915_reg.h.
#define LVDS_ENABLE_DITHER (1 << 25) |
Definition at line 1446 of file i915_reg.h.
#define LVDS_HSYNC_POLARITY (1 << 20) |
Definition at line 1449 of file i915_reg.h.
#define LVDS_ON (1UL<<31) |
Definition at line 922 of file i915_reg.h.
Definition at line 1444 of file i915_reg.h.
#define LVDS_PIPE_MASK (1 << 30) |
Definition at line 1443 of file i915_reg.h.
#define LVDS_PIPEB_SELECT (1 << 30) |
Definition at line 1442 of file i915_reg.h.
#define LVDS_PORT_EN (1UL << 31) |
Definition at line 1440 of file i915_reg.h.
#define LVDS_PORT_ENABLE (1UL << 31) |
Definition at line 3735 of file i915_reg.h.
#define LVDS_VSYNC_POLARITY (1 << 21) |
Definition at line 1448 of file i915_reg.h.
#define MAG_CLOCK_GATE_DISABLE (1 << 5) |
Definition at line 1087 of file i915_reg.h.
#define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) |
Definition at line 2992 of file i915_reg.h.
#define MASTER_INTERRUPT_ENABLE (1UL<<31) |
Definition at line 3128 of file i915_reg.h.
#define MCHBAR_MIRROR_BASE 0x10000 |
Definition at line 1170 of file i915_reg.h.
#define MCURSOR_GAMMA_ENABLE (1 << 26) |
Definition at line 2692 of file i915_reg.h.
#define MCURSOR_PIPE_A 0x00 |
Definition at line 2690 of file i915_reg.h.
#define MCURSOR_PIPE_B (1 << 28) |
Definition at line 2691 of file i915_reg.h.
#define MCURSOR_PIPE_SELECT (1 << 28) |
Definition at line 2689 of file i915_reg.h.
#define MEC_CLOCK_GATE_DISABLE (1 << 2) |
Definition at line 1091 of file i915_reg.h.
#define MECI_CLOCK_GATE_DISABLE (1 << 4) |
This bit must be unset on 855,865.
Definition at line 1089 of file i915_reg.h.
#define MECO_CLOCK_GATE_DISABLE (1 << 1) |
Definition at line 1092 of file i915_reg.h.
#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) |
Definition at line 604 of file i915_reg.h.
#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ |
Definition at line 593 of file i915_reg.h.
Definition at line 592 of file i915_reg.h.
#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ |
Definition at line 591 of file i915_reg.h.
#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ |
Definition at line 590 of file i915_reg.h.
#define MI_ARB_BLOCK_GRANT_MASK (3 << 12) |
Definition at line 589 of file i915_reg.h.
#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) |
Definition at line 599 of file i915_reg.h.
#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) |
Definition at line 613 of file i915_reg.h.
#define MI_ARB_DISABLE (0<<0) |
Definition at line 192 of file i915_reg.h.
Definition at line 634 of file i915_reg.h.
Definition at line 635 of file i915_reg.h.
#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) |
Definition at line 631 of file i915_reg.h.
#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) |
Definition at line 608 of file i915_reg.h.
#define MI_ARB_ENABLE (1<<0) |
Definition at line 191 of file i915_reg.h.
#define MI_ARB_ISOCH_WAIT_GTT (1 << 14) |
Definition at line 584 of file i915_reg.h.
#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ |
Definition at line 627 of file i915_reg.h.
#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) |
Definition at line 628 of file i915_reg.h.
#define MI_ARB_ON_OFF MI_INSTR(0x08, 0) |
Definition at line 190 of file i915_reg.h.
#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) |
Definition at line 578 of file i915_reg.h.
#define MI_ARB_STATE 0x020e4 /* 915+ only */ |
Definition at line 573 of file i915_reg.h.
#define MI_ARB_TIME_SLICE_1 (0 << 5) |
Definition at line 617 of file i915_reg.h.
#define MI_ARB_TIME_SLICE_10 (5 << 5) |
Definition at line 622 of file i915_reg.h.
#define MI_ARB_TIME_SLICE_14 (6 << 5) |
Definition at line 623 of file i915_reg.h.
#define MI_ARB_TIME_SLICE_16 (7 << 5) |
Definition at line 624 of file i915_reg.h.
#define MI_ARB_TIME_SLICE_2 (1 << 5) |
Definition at line 618 of file i915_reg.h.
#define MI_ARB_TIME_SLICE_4 (2 << 5) |
Definition at line 619 of file i915_reg.h.
#define MI_ARB_TIME_SLICE_6 (3 << 5) |
Definition at line 620 of file i915_reg.h.
#define MI_ARB_TIME_SLICE_8 (4 << 5) |
Definition at line 621 of file i915_reg.h.
#define MI_ARB_TIME_SLICE_MASK (7 << 5) |
Definition at line 616 of file i915_reg.h.
#define MI_BATCH_BUFFER MI_INSTR(0x30, 1) |
Definition at line 219 of file i915_reg.h.
#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) |
Definition at line 171 of file i915_reg.h.
#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
Definition at line 225 of file i915_reg.h.
#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ |
Definition at line 226 of file i915_reg.h.
#define MI_BATCH_NON_SECURE (1) |
Definition at line 220 of file i915_reg.h.
#define MI_BATCH_NON_SECURE_HSW (1<<13) |
Definition at line 224 of file i915_reg.h.
#define MI_BATCH_NON_SECURE_I965 (1<<8) |
Definition at line 222 of file i915_reg.h.
#define MI_BATCH_PPGTT_HSW (1<<8) |
Definition at line 223 of file i915_reg.h.
#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) |
Definition at line 180 of file i915_reg.h.
#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) |
Definition at line 181 of file i915_reg.h.
#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) |
Definition at line 184 of file i915_reg.h.
#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) |
Definition at line 185 of file i915_reg.h.
#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) |
Definition at line 188 of file i915_reg.h.
#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) |
Definition at line 186 of file i915_reg.h.
#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) |
Definition at line 187 of file i915_reg.h.
#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) |
Definition at line 189 of file i915_reg.h.
#define MI_DISPLAY_FLIP_PLANE | ( | n | ) | ((n) << 20) |
Definition at line 182 of file i915_reg.h.
#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ |
Definition at line 169 of file i915_reg.h.
#define MI_EXE_FLUSH (1 << 1) |
Definition at line 166 of file i915_reg.h.
#define MI_FLUSH MI_INSTR(0x04, 0) |
Definition at line 164 of file i915_reg.h.
#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ |
Definition at line 212 of file i915_reg.h.
#define MI_FLUSH_DW_OP_STOREDW (1<<14) |
Definition at line 215 of file i915_reg.h.
#define MI_FLUSH_DW_STORE_INDEX (1<<21) |
Definition at line 213 of file i915_reg.h.
#define MI_FLUSH_DW_USE_GTT (1<<2) |
Definition at line 217 of file i915_reg.h.
#define MI_FLUSH_DW_USE_PPGTT (0<<2) |
Definition at line 218 of file i915_reg.h.
#define MI_FLUSH_ENABLE (1 << 12) |
Definition at line 501 of file i915_reg.h.
#define MI_FORCE_RESTORE (1<<1) |
Definition at line 199 of file i915_reg.h.
#define MI_INSTR | ( | opcode, | |
flags | |||
) | (((opcode) << 23) | (flags)) |
Definition at line 155 of file i915_reg.h.
#define MI_INVALIDATE_BSD (1<<7) |
Definition at line 216 of file i915_reg.h.
#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ |
Definition at line 170 of file i915_reg.h.
#define MI_INVALIDATE_TLB (1<<18) |
Definition at line 214 of file i915_reg.h.
Definition at line 211 of file i915_reg.h.
#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) |
Definition at line 179 of file i915_reg.h.
#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ |
Definition at line 202 of file i915_reg.h.
#define MI_MM_SPACE_GTT (1<<8) |
Definition at line 195 of file i915_reg.h.
#define MI_MM_SPACE_PHYSICAL (0<<8) |
Definition at line 196 of file i915_reg.h.
#define MI_MODE 0x0209c |
Definition at line 499 of file i915_reg.h.
#define MI_NO_WRITE_FLUSH (1 << 2) |
Definition at line 167 of file i915_reg.h.
#define MI_NOOP MI_INSTR(0, 0) |
Definition at line 157 of file i915_reg.h.
#define MI_OVERLAY_CONTINUE (0x0<<21) |
Definition at line 176 of file i915_reg.h.
#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) |
Definition at line 175 of file i915_reg.h.
#define MI_OVERLAY_OFF (0x2<<21) |
Definition at line 178 of file i915_reg.h.
#define MI_OVERLAY_ON (0x1<<21) |
Definition at line 177 of file i915_reg.h.
#define MI_READ_FLUSH (1 << 0) |
Definition at line 165 of file i915_reg.h.
#define MI_REPORT_HEAD MI_INSTR(0x07, 0) |
Definition at line 174 of file i915_reg.h.
#define MI_RESTORE_EXT_STATE_EN (1<<2) |
Definition at line 198 of file i915_reg.h.
#define MI_RESTORE_INHIBIT (1<<0) |
Definition at line 200 of file i915_reg.h.
#define MI_SAVE_EXT_STATE_EN (1<<3) |
Definition at line 197 of file i915_reg.h.
#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ |
Definition at line 168 of file i915_reg.h.
#define MI_SEMAPHORE_COMPARE (1<<20) |
Definition at line 230 of file i915_reg.h.
#define MI_SEMAPHORE_GLOBAL_GTT (1<<22) |
Definition at line 228 of file i915_reg.h.
#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ |
Definition at line 227 of file i915_reg.h.
#define MI_SEMAPHORE_REGISTER (1<<18) |
Definition at line 231 of file i915_reg.h.
#define MI_SEMAPHORE_SYNC_BR (2<<16) |
Definition at line 236 of file i915_reg.h.
#define MI_SEMAPHORE_SYNC_BV (0<<16) |
Definition at line 237 of file i915_reg.h.
#define MI_SEMAPHORE_SYNC_INVALID (1<<0) |
Definition at line 238 of file i915_reg.h.
#define MI_SEMAPHORE_SYNC_RB (0<<16) |
Definition at line 233 of file i915_reg.h.
#define MI_SEMAPHORE_SYNC_RV (2<<16) |
Definition at line 232 of file i915_reg.h.
#define MI_SEMAPHORE_SYNC_VB (2<<16) |
Definition at line 235 of file i915_reg.h.
#define MI_SEMAPHORE_SYNC_VR (0<<16) |
Definition at line 234 of file i915_reg.h.
#define MI_SEMAPHORE_UPDATE (1<<21) |
Definition at line 229 of file i915_reg.h.
#define MI_SET_CONTEXT MI_INSTR(0x18, 0) |
Definition at line 194 of file i915_reg.h.
#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) |
Definition at line 201 of file i915_reg.h.
#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) |
Definition at line 203 of file i915_reg.h.
#define MI_STORE_DWORD_INDEX_SHIFT 2 |
Definition at line 204 of file i915_reg.h.
#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) |
Definition at line 172 of file i915_reg.h.
#define MI_SUSPEND_FLUSH_EN (1<<0) |
Definition at line 173 of file i915_reg.h.
#define MI_USER_INTERRUPT MI_INSTR(0x02, 0) |
Definition at line 158 of file i915_reg.h.
#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) |
Definition at line 159 of file i915_reg.h.
#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) |
Definition at line 160 of file i915_reg.h.
#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) |
Definition at line 162 of file i915_reg.h.
#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) |
Definition at line 163 of file i915_reg.h.
#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) |
Definition at line 161 of file i915_reg.h.
#define MLTR_ILK 0x11222 |
Definition at line 2598 of file i915_reg.h.
#define MLTR_WM1_SHIFT 0 |
Definition at line 2599 of file i915_reg.h.
#define MLTR_WM2_SHIFT 8 |
Definition at line 2600 of file i915_reg.h.
#define MM_BURST_LENGTH 0x00700000 |
Definition at line 569 of file i915_reg.h.
#define MM_FIFO_WATERMARK 0x0001F000 |
Definition at line 570 of file i915_reg.h.
#define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) |
Definition at line 1086 of file i915_reg.h.
#define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ |
Definition at line 1080 of file i915_reg.h.
#define NDE_RSTWRN_OPT 0x46408 |
Definition at line 4380 of file i915_reg.h.
#define NOPID 0x02094 |
Definition at line 473 of file i915_reg.h.
#define NULL_PACKET_VSYNC_ENABLE (1 << 9) |
Definition at line 3716 of file i915_reg.h.
#define OC_BUF (0x3<<20) |
Definition at line 1215 of file i915_reg.h.
#define OGAMC0 0x30024 |
Definition at line 1221 of file i915_reg.h.
#define OGAMC1 0x30020 |
Definition at line 1220 of file i915_reg.h.
#define OGAMC2 0x3001c |
Definition at line 1219 of file i915_reg.h.
#define OGAMC3 0x30018 |
Definition at line 1218 of file i915_reg.h.
#define OGAMC4 0x30014 |
Definition at line 1217 of file i915_reg.h.
#define OGAMC5 0x30010 |
Definition at line 1216 of file i915_reg.h.
#define OVADD 0x30000 |
Definition at line 1213 of file i915_reg.h.
#define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) |
Definition at line 1067 of file i915_reg.h.
#define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) |
Definition at line 1073 of file i915_reg.h.
#define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) |
Definition at line 1066 of file i915_reg.h.
#define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ |
Definition at line 1064 of file i915_reg.h.
#define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ |
Definition at line 1076 of file i915_reg.h.
#define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) |
This bit must be set on the 830 to prevent hangs when turning off the overlay scaler.
Definition at line 1072 of file i915_reg.h.
#define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) |
Definition at line 1074 of file i915_reg.h.
#define PALETTE | ( | pipe | ) | _PIPE(pipe, _PALETTE_A, _PALETTE_B) |
Definition at line 1158 of file i915_reg.h.
#define PANEL_8TO6_DITHER_ENABLE (1 << 3) |
Definition at line 1564 of file i915_reg.h.
#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) |
Definition at line 3782 of file i915_reg.h.
#define PANEL_LIGHT_OFF_DELAY_SHIFT 0 |
Definition at line 3783 of file i915_reg.h.
#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) |
Definition at line 3771 of file i915_reg.h.
#define PANEL_LIGHT_ON_DELAY_SHIFT 0 |
Definition at line 3772 of file i915_reg.h.
#define PANEL_PORT_SELECT_DPA (1 << 30) |
Definition at line 3765 of file i915_reg.h.
#define PANEL_PORT_SELECT_DPC (2 << 30) |
Definition at line 3767 of file i915_reg.h.
#define PANEL_PORT_SELECT_DPD (3 << 30) |
Definition at line 3768 of file i915_reg.h.
#define PANEL_PORT_SELECT_LVDS (0 << 30) |
Definition at line 3764 of file i915_reg.h.
#define PANEL_PORT_SELECT_MASK (3 << 30) |
Definition at line 3763 of file i915_reg.h.
#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) |
Definition at line 3788 of file i915_reg.h.
#define PANEL_POWER_CYCLE_DELAY_SHIFT 0 |
Definition at line 3789 of file i915_reg.h.
#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) |
Definition at line 3780 of file i915_reg.h.
#define PANEL_POWER_DOWN_DELAY_SHIFT 16 |
Definition at line 3781 of file i915_reg.h.
#define PANEL_POWER_OFF (0 << 0) |
Definition at line 3760 of file i915_reg.h.
#define PANEL_POWER_ON (1 << 0) |
Definition at line 3761 of file i915_reg.h.
#define PANEL_POWER_PORT_DP_A (1 << 30) |
Definition at line 3777 of file i915_reg.h.
#define PANEL_POWER_PORT_DP_C (2 << 30) |
Definition at line 3778 of file i915_reg.h.
#define PANEL_POWER_PORT_DP_D (3 << 30) |
Definition at line 3779 of file i915_reg.h.
#define PANEL_POWER_PORT_LVDS (0 << 30) |
Definition at line 3776 of file i915_reg.h.
#define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30) |
Definition at line 3775 of file i915_reg.h.
#define PANEL_POWER_RESET (1 << 1) |
Definition at line 3759 of file i915_reg.h.
#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) |
Definition at line 3769 of file i915_reg.h.
#define PANEL_POWER_UP_DELAY_SHIFT 16 |
Definition at line 3770 of file i915_reg.h.
#define PANEL_UNLOCK_MASK (0xffff << 16) |
Definition at line 3756 of file i915_reg.h.
#define PANEL_UNLOCK_REGS (0xabcd << 16) |
Definition at line 3755 of file i915_reg.h.
#define PC_BE_CLOCK_GATE_DISABLE (1 << 10) |
Definition at line 1082 of file i915_reg.h.
#define PC_FE_CLOCK_GATE_DISABLE (1 << 11) |
Definition at line 1081 of file i915_reg.h.
#define PCH_3DCGDIS0 0x46020 |
Definition at line 2991 of file i915_reg.h.
#define PCH_3DCGDIS1 0x46024 |
Definition at line 2995 of file i915_reg.h.
#define PCH_ADPA 0xe1100 |
Definition at line 1260 of file i915_reg.h.
#define PCH_DP_B 0xe4100 |
Definition at line 3791 of file i915_reg.h.
#define PCH_DP_C 0xe4200 |
Definition at line 3799 of file i915_reg.h.
#define PCH_DP_D 0xe4300 |
Definition at line 3807 of file i915_reg.h.
#define PCH_DPB_AUX_CH_CTL 0xe4110 |
Definition at line 3792 of file i915_reg.h.
#define PCH_DPB_AUX_CH_DATA1 0xe4114 |
Definition at line 3793 of file i915_reg.h.
#define PCH_DPB_AUX_CH_DATA2 0xe4118 |
Definition at line 3794 of file i915_reg.h.
#define PCH_DPB_AUX_CH_DATA3 0xe411c |
Definition at line 3795 of file i915_reg.h.
#define PCH_DPB_AUX_CH_DATA4 0xe4120 |
Definition at line 3796 of file i915_reg.h.
#define PCH_DPB_AUX_CH_DATA5 0xe4124 |
Definition at line 3797 of file i915_reg.h.
#define PCH_DPC_AUX_CH_CTL 0xe4210 |
Definition at line 3800 of file i915_reg.h.
#define PCH_DPC_AUX_CH_DATA1 0xe4214 |
Definition at line 3801 of file i915_reg.h.
#define PCH_DPC_AUX_CH_DATA2 0xe4218 |
Definition at line 3802 of file i915_reg.h.
#define PCH_DPC_AUX_CH_DATA3 0xe421c |
Definition at line 3803 of file i915_reg.h.
#define PCH_DPC_AUX_CH_DATA4 0xe4220 |
Definition at line 3804 of file i915_reg.h.
#define PCH_DPC_AUX_CH_DATA5 0xe4224 |
Definition at line 3805 of file i915_reg.h.
#define PCH_DPD_AUX_CH_CTL 0xe4310 |
Definition at line 3808 of file i915_reg.h.
#define PCH_DPD_AUX_CH_DATA1 0xe4314 |
Definition at line 3809 of file i915_reg.h.
#define PCH_DPD_AUX_CH_DATA2 0xe4318 |
Definition at line 3810 of file i915_reg.h.
#define PCH_DPD_AUX_CH_DATA3 0xe431c |
Definition at line 3811 of file i915_reg.h.
#define PCH_DPD_AUX_CH_DATA4 0xe4320 |
Definition at line 3812 of file i915_reg.h.
#define PCH_DPD_AUX_CH_DATA5 0xe4324 |
Definition at line 3813 of file i915_reg.h.
#define PCH_DPLL_SEL 0xc7000 |
Definition at line 3379 of file i915_reg.h.
#define PCH_DPLL_TEST 0xc606c |
Definition at line 3342 of file i915_reg.h.
#define PCH_DPLL_TMR_CFG 0xc6208 |
Definition at line 3374 of file i915_reg.h.
#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) |
Definition at line 3575 of file i915_reg.h.
#define PCH_DREF_CONTROL 0xC6200 |
Definition at line 3344 of file i915_reg.h.
#define PCH_GMBUS0 0xc5100 |
Definition at line 3323 of file i915_reg.h.
#define PCH_GMBUS1 0xc5104 |
Definition at line 3324 of file i915_reg.h.
#define PCH_GMBUS2 0xc5108 |
Definition at line 3325 of file i915_reg.h.
#define PCH_GMBUS3 0xc510c |
Definition at line 3326 of file i915_reg.h.
#define PCH_GMBUS4 0xc5110 |
Definition at line 3327 of file i915_reg.h.
#define PCH_GMBUS5 0xc5120 |
Definition at line 3328 of file i915_reg.h.
#define PCH_GPIOA 0xc5010 |
Definition at line 3316 of file i915_reg.h.
#define PCH_GPIOB 0xc5014 |
Definition at line 3317 of file i915_reg.h.
#define PCH_GPIOC 0xc5018 |
Definition at line 3318 of file i915_reg.h.
#define PCH_GPIOD 0xc501c |
Definition at line 3319 of file i915_reg.h.
#define PCH_GPIOE 0xc5020 |
Definition at line 3320 of file i915_reg.h.
#define PCH_GPIOF 0xc5024 |
Definition at line 3321 of file i915_reg.h.
#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) |
Definition at line 3576 of file i915_reg.h.
#define PCH_LVDS 0xe1180 |
Definition at line 3732 of file i915_reg.h.
#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ |
Definition at line 3287 of file i915_reg.h.
#define PCH_PP_CONTROL 0xc7204 |
Definition at line 3754 of file i915_reg.h.
#define PCH_PP_DIVISOR 0xc7210 |
Definition at line 3785 of file i915_reg.h.
#define PCH_PP_OFF_DELAYS 0xc720c |
Definition at line 3774 of file i915_reg.h.
#define PCH_PP_ON_DELAYS 0xc7208 |
Definition at line 3762 of file i915_reg.h.
#define PCH_PP_STATUS 0xc7200 |
Definition at line 3753 of file i915_reg.h.
#define PCH_RAWCLK_FREQ 0xc6204 |
Definition at line 3367 of file i915_reg.h.
#define PCH_SDVOB HDMIB |
Definition at line 3727 of file i915_reg.h.
#define PCH_SSC4_AUX_PARMS 0xc6214 |
Definition at line 3377 of file i915_reg.h.
#define PCH_SSC4_PARMS 0xc6210 |
Definition at line 3376 of file i915_reg.h.
#define PCH_TRANSCONF | ( | plane | ) | _PIPE(plane, _PCH_TRANSACONF, _PCH_TRANSBCONF) |
Definition at line 3526 of file i915_reg.h.
#define PF_CTL | ( | pipe | ) | _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) |
Definition at line 3073 of file i915_reg.h.
#define PF_ENABLE (1UL<<31) |
Definition at line 3056 of file i915_reg.h.
#define PF_FILTER_EDGE_ENHANCE (2<<23) |
Definition at line 3062 of file i915_reg.h.
#define PF_FILTER_EDGE_SOFTEN (3<<23) |
Definition at line 3063 of file i915_reg.h.
#define PF_FILTER_MASK (3<<23) |
Definition at line 3059 of file i915_reg.h.
#define PF_FILTER_MED_3x3 (1<<23) |
Definition at line 3061 of file i915_reg.h.
#define PF_FILTER_PROGRAMMED (0<<23) |
Definition at line 3060 of file i915_reg.h.
#define PF_HSCALE | ( | pipe | ) | _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) |
Definition at line 3077 of file i915_reg.h.
Definition at line 3058 of file i915_reg.h.
#define PF_PIPE_SEL_MASK_IVB (3<<29) |
Definition at line 3057 of file i915_reg.h.
#define PF_VSCALE | ( | pipe | ) | _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) |
Definition at line 3076 of file i915_reg.h.
#define PF_WIN_POS | ( | pipe | ) | _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) |
Definition at line 3075 of file i915_reg.h.
#define PF_WIN_SZ | ( | pipe | ) | _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) |
Definition at line 3074 of file i915_reg.h.
#define PFIT_AUTO_RATIOS 0x61238 |
Definition at line 1584 of file i915_reg.h.
#define PFIT_CONTROL 0x61230 |
Definition at line 1552 of file i915_reg.h.
#define PFIT_ENABLE (1UL << 31) |
Definition at line 1553 of file i915_reg.h.
#define PFIT_FILTER_FUZZY (0 << 24) |
Definition at line 1565 of file i915_reg.h.
#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 |
Definition at line 1577 of file i915_reg.h.
#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 |
Definition at line 1577 of file i915_reg.h.
#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff |
Definition at line 1582 of file i915_reg.h.
#define PFIT_HORIZ_SCALE_SHIFT 4 |
Definition at line 1576 of file i915_reg.h.
#define PFIT_HORIZ_SCALE_SHIFT_965 0 |
Definition at line 1581 of file i915_reg.h.
#define PFIT_PGM_RATIOS 0x61234 |
Definition at line 1570 of file i915_reg.h.
#define PFIT_PIPE_MASK (3 << 29) |
Definition at line 1554 of file i915_reg.h.
#define PFIT_PIPE_SHIFT 29 |
Definition at line 1555 of file i915_reg.h.
#define PFIT_SCALING_AUTO (0 << 26) |
Definition at line 1566 of file i915_reg.h.
#define PFIT_SCALING_LETTER (3 << 26) |
Definition at line 1569 of file i915_reg.h.
#define PFIT_SCALING_PILLAR (2 << 26) |
Definition at line 1568 of file i915_reg.h.
#define PFIT_SCALING_PROGRAMMED (1 << 26) |
Definition at line 1567 of file i915_reg.h.
#define PFIT_VERT_SCALE_MASK 0xfff00000 |
Definition at line 1575 of file i915_reg.h.
#define PFIT_VERT_SCALE_MASK 0xfff00000 |
Definition at line 1575 of file i915_reg.h.
#define PFIT_VERT_SCALE_MASK_965 0x1fff0000 |
Definition at line 1580 of file i915_reg.h.
#define PFIT_VERT_SCALE_SHIFT 20 |
Definition at line 1574 of file i915_reg.h.
#define PFIT_VERT_SCALE_SHIFT_965 16 |
Definition at line 1579 of file i915_reg.h.
#define PGTBL_ER 0x02024 |
Definition at line 401 of file i915_reg.h.
#define PINEVIEW_CURSOR_DFT_WM 0 |
Definition at line 2561 of file i915_reg.h.
#define PINEVIEW_CURSOR_FIFO 64 |
Definition at line 2559 of file i915_reg.h.
#define PINEVIEW_CURSOR_GUARD_WM 5 |
Definition at line 2562 of file i915_reg.h.
#define PINEVIEW_CURSOR_MAX_WM 0x3f |
Definition at line 2560 of file i915_reg.h.
#define PINEVIEW_DFT_HPLLOFF_WM 0 |
Definition at line 2557 of file i915_reg.h.
#define PINEVIEW_DFT_WM 0x3f |
Definition at line 2556 of file i915_reg.h.
#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ |
Definition at line 2553 of file i915_reg.h.
#define PINEVIEW_FIFO_LINE_SIZE 64 |
Definition at line 2554 of file i915_reg.h.
#define PINEVIEW_GUARD_WM 10 |
Definition at line 2558 of file i915_reg.h.
#define PINEVIEW_MAX_WM 0x1ff |
Definition at line 2555 of file i915_reg.h.
#define PINEVIEW_SELF_REFRESH_EN (1<<30) |
Definition at line 2514 of file i915_reg.h.
#define PIPE_10BPC (1 << 5) |
Definition at line 2446 of file i915_reg.h.
#define PIPE_12BPC (3 << 5) |
Definition at line 2448 of file i915_reg.h.
#define PIPE_6BPC (2 << 5) |
Definition at line 2447 of file i915_reg.h.
#define PIPE_8BPC (0 << 5) |
Definition at line 2445 of file i915_reg.h.
#define PIPE_BPC_MASK (7 << 5) /* Ironlake */ |
Definition at line 2444 of file i915_reg.h.
#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) |
Definition at line 292 of file i915_reg.h.
#define PIPE_CONTROL_CS_STALL (1<<20) |
Definition at line 281 of file i915_reg.h.
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) |
Definition at line 295 of file i915_reg.h.
#define PIPE_CONTROL_DEPTH_STALL (1<<13) |
Definition at line 284 of file i915_reg.h.
Definition at line 296 of file i915_reg.h.
#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) |
Definition at line 289 of file i915_reg.h.
#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ |
Definition at line 287 of file i915_reg.h.
#define PIPE_CONTROL_NOTIFY (1<<8) |
Definition at line 290 of file i915_reg.h.
#define PIPE_CONTROL_QW_WRITE (1<<14) |
Definition at line 283 of file i915_reg.h.
#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ |
Definition at line 286 of file i915_reg.h.
#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) |
Definition at line 294 of file i915_reg.h.
#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) |
Definition at line 293 of file i915_reg.h.
#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ |
Definition at line 288 of file i915_reg.h.
#define PIPE_CONTROL_TLB_INVALIDATE (1<<18) |
Definition at line 282 of file i915_reg.h.
#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) |
Definition at line 291 of file i915_reg.h.
#define PIPE_CONTROL_WRITE_FLUSH (1<<12) |
Definition at line 285 of file i915_reg.h.
#define PIPE_CRC_DONE_ENABLE (1UL<<28) |
Definition at line 2411 of file i915_reg.h.
#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) |
Definition at line 2430 of file i915_reg.h.
#define PIPE_CRC_ERROR_ENABLE (1UL<<29) |
Definition at line 2410 of file i915_reg.h.
#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) |
Definition at line 2429 of file i915_reg.h.
#define PIPE_DATA_M1 | ( | tran | ) | _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1) |
Definition at line 3043 of file i915_reg.h.
#define PIPE_DATA_M1_OFFSET 0 |
Definition at line 3010 of file i915_reg.h.
#define PIPE_DATA_M2 | ( | tran | ) | _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2) |
Definition at line 3045 of file i915_reg.h.
#define PIPE_DATA_M2_OFFSET 0 |
Definition at line 3015 of file i915_reg.h.
#define PIPE_DATA_N1 | ( | tran | ) | _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1) |
Definition at line 3044 of file i915_reg.h.
#define PIPE_DATA_N1_OFFSET 0 |
Definition at line 3012 of file i915_reg.h.
#define PIPE_DATA_N2 | ( | tran | ) | _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2) |
Definition at line 3046 of file i915_reg.h.
#define PIPE_DATA_N2_OFFSET 0 |
Definition at line 3017 of file i915_reg.h.
#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) |
Definition at line 2416 of file i915_reg.h.
#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) |
Definition at line 2435 of file i915_reg.h.
#define PIPE_DP_LINK_M | ( | pipe | ) | _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M) |
Definition at line 2358 of file i915_reg.h.
#define PIPE_DP_LINK_N | ( | pipe | ) | _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N) |
Definition at line 2359 of file i915_reg.h.
#define PIPE_DPST_EVENT_ENABLE (1UL<<23) |
Definition at line 2417 of file i915_reg.h.
#define PIPE_DPST_EVENT_STATUS (1UL<<7) |
Definition at line 2436 of file i915_reg.h.
#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) |
Definition at line 2421 of file i915_reg.h.
#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) |
Definition at line 2439 of file i915_reg.h.
#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) |
Definition at line 2408 of file i915_reg.h.
#define PIPE_FRAME_HIGH_MASK 0x0000ffff |
Definition at line 2659 of file i915_reg.h.
#define PIPE_FRAME_HIGH_SHIFT 0 |
Definition at line 2660 of file i915_reg.h.
#define PIPE_FRAME_LOW_MASK 0xff000000 |
Definition at line 2662 of file i915_reg.h.
#define PIPE_FRAME_LOW_SHIFT 24 |
Definition at line 2663 of file i915_reg.h.
#define PIPE_FRMCOUNT_GM45 | ( | pipe | ) | _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45) |
Definition at line 2669 of file i915_reg.h.
#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) |
Definition at line 2412 of file i915_reg.h.
#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) |
Definition at line 2431 of file i915_reg.h.
#define PIPE_GMCH_DATA_M | ( | pipe | ) | _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) |
Definition at line 2356 of file i915_reg.h.
#define PIPE_GMCH_DATA_M_MASK (0xffffff) |
Definition at line 2331 of file i915_reg.h.
#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) |
Definition at line 2328 of file i915_reg.h.
#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 |
Definition at line 2329 of file i915_reg.h.
#define PIPE_GMCH_DATA_N | ( | pipe | ) | _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) |
Definition at line 2357 of file i915_reg.h.
#define PIPE_GMCH_DATA_N_MASK (0xffffff) |
Definition at line 2335 of file i915_reg.h.
#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) |
Definition at line 2414 of file i915_reg.h.
#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) |
Definition at line 2433 of file i915_reg.h.
#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ |
Definition at line 2422 of file i915_reg.h.
#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ |
Definition at line 2440 of file i915_reg.h.
#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) |
Definition at line 2419 of file i915_reg.h.
#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) |
Definition at line 2437 of file i915_reg.h.
#define PIPE_LINK_M1 | ( | tran | ) | _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1) |
Definition at line 3047 of file i915_reg.h.
#define PIPE_LINK_M1_OFFSET 0 |
Definition at line 3020 of file i915_reg.h.
#define PIPE_LINK_M2 | ( | tran | ) | _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2) |
Definition at line 3049 of file i915_reg.h.
#define PIPE_LINK_M2_OFFSET 0 |
Definition at line 3025 of file i915_reg.h.
#define PIPE_LINK_N1 | ( | tran | ) | _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1) |
Definition at line 3048 of file i915_reg.h.
#define PIPE_LINK_N1_OFFSET 0 |
Definition at line 3022 of file i915_reg.h.
#define PIPE_LINK_N2 | ( | tran | ) | _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2) |
Definition at line 3050 of file i915_reg.h.
#define PIPE_LINK_N2_OFFSET 0 |
Definition at line 3027 of file i915_reg.h.
#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) |
Definition at line 2420 of file i915_reg.h.
#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) |
Definition at line 2438 of file i915_reg.h.
#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) |
Definition at line 2426 of file i915_reg.h.
#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) |
Definition at line 2443 of file i915_reg.h.
#define PIPE_PIXEL_MASK 0x00ffffff |
Definition at line 2664 of file i915_reg.h.
#define PIPE_PIXEL_SHIFT 0 |
Definition at line 2665 of file i915_reg.h.
#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ |
Definition at line 2423 of file i915_reg.h.
#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ |
Definition at line 2441 of file i915_reg.h.
#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) |
Definition at line 2424 of file i915_reg.h.
#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) |
Definition at line 2442 of file i915_reg.h.
#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) |
Definition at line 2415 of file i915_reg.h.
#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) |
Definition at line 2434 of file i915_reg.h.
#define PIPE_WM_LINETIME | ( | pipe | ) |
Definition at line 4361 of file i915_reg.h.
#define PIPE_WM_LINETIME_A 0x45270 |
Definition at line 4359 of file i915_reg.h.
#define PIPE_WM_LINETIME_B 0x45274 |
Definition at line 4360 of file i915_reg.h.
Definition at line 4366 of file i915_reg.h.
#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) |
Definition at line 4365 of file i915_reg.h.
#define PIPE_WM_LINETIME_MASK (0x1ff) |
Definition at line 4363 of file i915_reg.h.
Definition at line 4364 of file i915_reg.h.
#define PIPEA_DP_LINK_M_MASK (0xffffff) |
Definition at line 2350 of file i915_reg.h.
#define PIPEA_DP_LINK_N_MASK (0xffffff) |
Definition at line 2354 of file i915_reg.h.
#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) |
Definition at line 2425 of file i915_reg.h.
#define PIPEA_HLINE_INT_EN (1<<20) |
Definition at line 2465 of file i915_reg.h.
#define PIPEA_LINE_COMPARE_INT_EN (1<<21) |
Definition at line 2464 of file i915_reg.h.
#define PIPEA_PP_CONTROL 0x61204 |
Definition at line 3742 of file i915_reg.h.
#define PIPEA_PP_DIVISOR 0x61210 |
Definition at line 3745 of file i915_reg.h.
#define PIPEA_PP_OFF_DELAYS 0x6120c |
Definition at line 3744 of file i915_reg.h.
#define PIPEA_PP_ON_DELAYS 0x61208 |
Definition at line 3743 of file i915_reg.h.
#define PIPEA_PP_STATUS 0x61200 |
Definition at line 3741 of file i915_reg.h.
#define PIPEA_VBLANK_INT_EN (1<<19) |
Definition at line 2466 of file i915_reg.h.
#define PIPEB_HLINE_INT_EN (1<<28) |
Definition at line 2459 of file i915_reg.h.
#define PIPEB_LINE_COMPARE_INT_EN (1<<29) |
Definition at line 2458 of file i915_reg.h.
#define PIPEB_PP_CONTROL 0x61304 |
Definition at line 3748 of file i915_reg.h.
#define PIPEB_PP_DIVISOR 0x61310 |
Definition at line 3751 of file i915_reg.h.
#define PIPEB_PP_OFF_DELAYS 0x6130c |
Definition at line 3750 of file i915_reg.h.
#define PIPEB_PP_ON_DELAYS 0x61308 |
Definition at line 3749 of file i915_reg.h.
#define PIPEB_PP_STATUS 0x61300 |
Definition at line 3747 of file i915_reg.h.
#define PIPEB_VBLANK_INT_EN (1<<27) |
Definition at line 2460 of file i915_reg.h.
#define PIPECONF | ( | tran | ) | _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF) |
Definition at line 2451 of file i915_reg.h.
#define PIPECONF_BPP_10 (1<<5) |
Definition at line 2398 of file i915_reg.h.
#define PIPECONF_BPP_12 (3<<5) |
Definition at line 2400 of file i915_reg.h.
#define PIPECONF_BPP_6 (2<<5) |
Definition at line 2399 of file i915_reg.h.
#define PIPECONF_BPP_8 (0<<5) |
Definition at line 2397 of file i915_reg.h.
#define PIPECONF_BPP_MASK (0x000000e0) |
Definition at line 2396 of file i915_reg.h.
#define PIPECONF_CXSR_DOWNCLOCK (1<<16) |
Definition at line 2395 of file i915_reg.h.
#define PIPECONF_DISABLE 0 |
Definition at line 2369 of file i915_reg.h.
#define PIPECONF_DITHER_EN (1<<4) |
Definition at line 2401 of file i915_reg.h.
#define PIPECONF_DITHER_TYPE_MASK (0x0000000c) |
Definition at line 2402 of file i915_reg.h.
#define PIPECONF_DITHER_TYPE_SP (0<<2) |
Definition at line 2403 of file i915_reg.h.
#define PIPECONF_DITHER_TYPE_ST1 (1<<2) |
Definition at line 2404 of file i915_reg.h.
#define PIPECONF_DITHER_TYPE_ST2 (2<<2) |
Definition at line 2405 of file i915_reg.h.
#define PIPECONF_DITHER_TYPE_TEMP (3<<2) |
Definition at line 2406 of file i915_reg.h.
#define PIPECONF_DOUBLE_WIDE (1<<30) |
Definition at line 2370 of file i915_reg.h.
#define PIPECONF_ENABLE (1UL<<31) |
Definition at line 2368 of file i915_reg.h.
#define PIPECONF_FORCE_BORDER (1<<25) |
Definition at line 2378 of file i915_reg.h.
#define PIPECONF_FRAME_START_DELAY_MASK (3<<27) |
Definition at line 2372 of file i915_reg.h.
#define PIPECONF_GAMMA (1<<24) |
Definition at line 2377 of file i915_reg.h.
#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ |
Definition at line 2387 of file i915_reg.h.
#define PIPECONF_INTERLACE_MASK (7 << 21) |
Definition at line 2379 of file i915_reg.h.
#define PIPECONF_INTERLACE_MASK_HSW (3 << 21) |
Definition at line 2380 of file i915_reg.h.
#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) |
Definition at line 2386 of file i915_reg.h.
#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ |
Definition at line 2385 of file i915_reg.h.
#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ |
Definition at line 2384 of file i915_reg.h.
#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ |
Definition at line 2393 of file i915_reg.h.
#define PIPECONF_INTERLACED_ILK (3 << 21) |
Definition at line 2392 of file i915_reg.h.
#define PIPECONF_PALETTE 0 |
Definition at line 2376 of file i915_reg.h.
#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ |
Definition at line 2394 of file i915_reg.h.
#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) |
Definition at line 2391 of file i915_reg.h.
#define PIPECONF_PIPE_LOCKED (1<<25) |
Definition at line 2375 of file i915_reg.h.
#define PIPECONF_PIPE_UNLOCKED 0 |
Definition at line 2374 of file i915_reg.h.
#define PIPECONF_PROGRESSIVE (0 << 21) |
Definition at line 2383 of file i915_reg.h.
#define PIPECONF_SINGLE_WIDE 0 |
Definition at line 2373 of file i915_reg.h.
Definition at line 2452 of file i915_reg.h.
#define PIPEFRAME | ( | pipe | ) | _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) |
Definition at line 2453 of file i915_reg.h.
#define PIPEFRAMEPIXEL | ( | pipe | ) | _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) |
Definition at line 2454 of file i915_reg.h.
Definition at line 2450 of file i915_reg.h.
#define PIPESTAT | ( | pipe | ) | _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) |
Definition at line 2455 of file i915_reg.h.
#define PIXCLK_GATE 0xC6020 |
Definition at line 4293 of file i915_reg.h.
#define PIXCLK_GATE_GATE (0<<0) |
Definition at line 4295 of file i915_reg.h.
#define PIXCLK_GATE_UNGATE (1<<0) |
Definition at line 4294 of file i915_reg.h.
#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) |
Definition at line 655 of file i915_reg.h.
#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) |
Definition at line 2413 of file i915_reg.h.
#define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10) |
Definition at line 2432 of file i915_reg.h.
#define PLANEA_FLIPDONE_INT_EN (1<<16) |
Definition at line 2469 of file i915_reg.h.
#define PLANEA_INVALID_GTT_INT_EN (1<<16) |
Definition at line 2479 of file i915_reg.h.
#define PLANEA_INVALID_GTT_STATUS (1<<0) |
Definition at line 2488 of file i915_reg.h.
#define PLANEB_FLIPDONE_INT_EN (1<<24) |
Definition at line 2463 of file i915_reg.h.
#define PLANEB_INVALID_GTT_INT_EN (1<<19) |
Definition at line 2476 of file i915_reg.h.
#define PLANEB_INVALID_GTT_STATUS (1<<3) |
Definition at line 2485 of file i915_reg.h.
#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) |
Definition at line 961 of file i915_reg.h.
#define PLL_LOAD_PULSE_PHASE_SHIFT 9 |
Definition at line 947 of file i915_reg.h.
#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ |
Definition at line 941 of file i915_reg.h.
#define PLL_P2_DIVIDE_BY_4 (1 << 23) |
Definition at line 940 of file i915_reg.h.
#define PLL_REF_INPUT_DREFCLK (0 << 13) |
Definition at line 942 of file i915_reg.h.
#define PLL_REF_INPUT_MASK (3 << 13) |
Definition at line 946 of file i915_reg.h.
#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ |
Definition at line 943 of file i915_reg.h.
#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ |
Definition at line 944 of file i915_reg.h.
Definition at line 951 of file i915_reg.h.
#define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) |
Definition at line 950 of file i915_reg.h.
#define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 |
Definition at line 949 of file i915_reg.h.
#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) |
Definition at line 945 of file i915_reg.h.
#define PORT_CLK_SEL | ( | port | ) | _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B) |
Definition at line 4320 of file i915_reg.h.
#define PORT_CLK_SEL_A 0x46100 |
Definition at line 4318 of file i915_reg.h.
#define PORT_CLK_SEL_B 0x46104 |
Definition at line 4319 of file i915_reg.h.
#define PORT_CLK_SEL_LCPLL_1350 (1<<29) |
Definition at line 4322 of file i915_reg.h.
#define PORT_CLK_SEL_LCPLL_2700 (0<<29) |
Definition at line 4321 of file i915_reg.h.
#define PORT_CLK_SEL_LCPLL_810 (2<<29) |
Definition at line 4323 of file i915_reg.h.
#define PORT_CLK_SEL_NONE (7<<29) |
Definition at line 4327 of file i915_reg.h.
#define PORT_CLK_SEL_SPLL (3<<29) |
Definition at line 4324 of file i915_reg.h.
#define PORT_CLK_SEL_WRPLL1 (4<<29) |
Definition at line 4325 of file i915_reg.h.
#define PORT_CLK_SEL_WRPLL2 (5<<29) |
Definition at line 4326 of file i915_reg.h.
#define PORT_DETECTED (1 << 2) |
Definition at line 3724 of file i915_reg.h.
#define PORT_ENABLE (1UL << 31) |
Definition at line 3706 of file i915_reg.h.
#define PORT_HOTPLUG_EN 0x61110 |
Definition at line 1306 of file i915_reg.h.
#define PORT_HOTPLUG_STAT 0x61114 |
Definition at line 1333 of file i915_reg.h.
Definition at line 3821 of file i915_reg.h.
#define PORT_TO_PIPE_CPT | ( | val | ) | (((val) & PORT_TRANS_SEL_MASK) >> 29) |
Definition at line 3822 of file i915_reg.h.
#define PORT_TRANS_A_SEL_CPT 0 |
Definition at line 3816 of file i915_reg.h.
#define PORT_TRANS_B_SEL_CPT (1<<29) |
Definition at line 3817 of file i915_reg.h.
#define PORT_TRANS_C_SEL_CPT (2<<29) |
Definition at line 3818 of file i915_reg.h.
Definition at line 3820 of file i915_reg.h.
#define PORT_TRANS_SEL_MASK (3<<29) |
Definition at line 3819 of file i915_reg.h.
#define PORTB_HOTPLUG_ENABLE (1 << 4) |
Definition at line 3306 of file i915_reg.h.
#define PORTB_HOTPLUG_LONG_DETECT (1 << 1) |
Definition at line 3314 of file i915_reg.h.
#define PORTB_HOTPLUG_NO_DETECT (0) |
Definition at line 3312 of file i915_reg.h.
#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) |
Definition at line 3313 of file i915_reg.h.
#define PORTB_PULSE_DURATION_100ms (3 << 2) |
Definition at line 3310 of file i915_reg.h.
#define PORTB_PULSE_DURATION_2ms (0) |
Definition at line 3307 of file i915_reg.h.
#define PORTB_PULSE_DURATION_4_5ms (1 << 2) |
Definition at line 3308 of file i915_reg.h.
#define PORTB_PULSE_DURATION_6ms (2 << 2) |
Definition at line 3309 of file i915_reg.h.
#define PORTB_PULSE_DURATION_MASK (3 << 2) |
Definition at line 3311 of file i915_reg.h.
#define PORTC_HOTPLUG_ENABLE (1 << 12) |
Definition at line 3297 of file i915_reg.h.
#define PORTC_HOTPLUG_LONG_DETECT (1 << 9) |
Definition at line 3305 of file i915_reg.h.
#define PORTC_HOTPLUG_NO_DETECT (0) |
Definition at line 3303 of file i915_reg.h.
#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) |
Definition at line 3304 of file i915_reg.h.
#define PORTC_PULSE_DURATION_100ms (3 << 10) |
Definition at line 3301 of file i915_reg.h.
#define PORTC_PULSE_DURATION_2ms (0) |
Definition at line 3298 of file i915_reg.h.
#define PORTC_PULSE_DURATION_4_5ms (1 << 10) |
Definition at line 3299 of file i915_reg.h.
#define PORTC_PULSE_DURATION_6ms (2 << 10) |
Definition at line 3300 of file i915_reg.h.
#define PORTC_PULSE_DURATION_MASK (3 << 10) |
Definition at line 3302 of file i915_reg.h.
#define PORTD_HOTPLUG_ENABLE (1 << 20) |
Definition at line 3288 of file i915_reg.h.
#define PORTD_HOTPLUG_LONG_DETECT (1 << 17) |
Definition at line 3296 of file i915_reg.h.
#define PORTD_HOTPLUG_NO_DETECT (0) |
Definition at line 3294 of file i915_reg.h.
#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) |
Definition at line 3295 of file i915_reg.h.
#define PORTD_PULSE_DURATION_100ms (3 << 18) |
Definition at line 3292 of file i915_reg.h.
#define PORTD_PULSE_DURATION_2ms (0) |
Definition at line 3289 of file i915_reg.h.
#define PORTD_PULSE_DURATION_4_5ms (1 << 18) |
Definition at line 3290 of file i915_reg.h.
#define PORTD_PULSE_DURATION_6ms (2 << 18) |
Definition at line 3291 of file i915_reg.h.
#define PORTD_PULSE_DURATION_MASK (3 << 18) |
Definition at line 3293 of file i915_reg.h.
#define POWER_TARGET_ON (1 << 0) |
Definition at line 1546 of file i915_reg.h.
#define PP_CONTROL 0x61204 |
Definition at line 1545 of file i915_reg.h.
#define PP_CYCLE_DELAY_ACTIVE (1 << 27) |
Definition at line 1534 of file i915_reg.h.
#define PP_DIR_DCLV_2G 0xffffffff |
Definition at line 97 of file i915_reg.h.
#define PP_DIVISOR 0x61210 |
Definition at line 1549 of file i915_reg.h.
#define PP_OFF_DELAYS 0x6120c |
Definition at line 1548 of file i915_reg.h.
#define PP_ON (1UL << 31) |
Definition at line 1520 of file i915_reg.h.
#define PP_ON_DELAYS 0x61208 |
Definition at line 1547 of file i915_reg.h.
#define PP_READY (1 << 30) |
Definition at line 1528 of file i915_reg.h.
#define PP_REFERENCE_DIVIDER_MASK (0xffffff00) |
Definition at line 3786 of file i915_reg.h.
#define PP_REFERENCE_DIVIDER_SHIFT 8 |
Definition at line 3787 of file i915_reg.h.
#define PP_SEQUENCE_MASK (3 << 28) |
Definition at line 1532 of file i915_reg.h.
#define PP_SEQUENCE_NONE (0 << 28) |
Definition at line 1529 of file i915_reg.h.
#define PP_SEQUENCE_POWER_DOWN (2 << 28) |
Definition at line 1531 of file i915_reg.h.
#define PP_SEQUENCE_POWER_UP (1 << 28) |
Definition at line 1530 of file i915_reg.h.
#define PP_SEQUENCE_SHIFT 28 |
Definition at line 1533 of file i915_reg.h.
#define PP_SEQUENCE_STATE_MASK 0x0000000f |
Definition at line 1535 of file i915_reg.h.
#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) |
Definition at line 1536 of file i915_reg.h.
#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) |
Definition at line 1537 of file i915_reg.h.
#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) |
Definition at line 1538 of file i915_reg.h.
#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) |
Definition at line 1539 of file i915_reg.h.
#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) |
Definition at line 1540 of file i915_reg.h.
#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) |
Definition at line 1541 of file i915_reg.h.
#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) |
Definition at line 1542 of file i915_reg.h.
#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) |
Definition at line 1543 of file i915_reg.h.
#define PP_SEQUENCE_STATE_RESET (0xf << 0) |
Definition at line 1544 of file i915_reg.h.
#define PP_STATUS 0x61200 |
Definition at line 1519 of file i915_reg.h.
#define PPCR 0x61204 |
Definition at line 914 of file i915_reg.h.
#define PPCR_ON (1<<0) |
Definition at line 915 of file i915_reg.h.
#define PWRCTX_EN (1<<0) |
Definition at line 469 of file i915_reg.h.
#define PWRCTXA 0x2088 /* 965GM+ only */ |
Definition at line 468 of file i915_reg.h.
#define RAMCLK_GATE_D 0x6210 /* CRL only */ |
Definition at line 1146 of file i915_reg.h.
#define RAWCLK_FREQ_MASK 0x3ff |
Definition at line 3372 of file i915_reg.h.
#define RENCLK_GATE_D1 0x6204 |
Definition at line 1078 of file i915_reg.h.
#define RENCLK_GATE_D2 0x6208 |
Definition at line 1142 of file i915_reg.h.
#define RENDER_HWS_PGA_GEN7 (0x04080) |
Definition at line 424 of file i915_reg.h.
#define RENDER_RING_BASE 0x02000 |
Definition at line 402 of file i915_reg.h.
Definition at line 429 of file i915_reg.h.
Definition at line 409 of file i915_reg.h.
Definition at line 460 of file i915_reg.h.
#define RING_FAULT_REG | ( | ring | ) | (0x4094 + 0x100*(ring)->id) |
Definition at line 425 of file i915_reg.h.
Definition at line 407 of file i915_reg.h.
Definition at line 419 of file i915_reg.h.
Definition at line 420 of file i915_reg.h.
Definition at line 431 of file i915_reg.h.
Definition at line 458 of file i915_reg.h.
Definition at line 461 of file i915_reg.h.
Definition at line 459 of file i915_reg.h.
#define RING_INVALID 0x00000000 |
Definition at line 444 of file i915_reg.h.
Definition at line 457 of file i915_reg.h.
Definition at line 456 of file i915_reg.h.
Definition at line 418 of file i915_reg.h.
#define RING_MODE_GEN7 | ( | ring | ) | ((ring)->mmio_base+0x29c) |
Definition at line 510 of file i915_reg.h.
#define RING_NO_REPORT 0x00000000 |
Definition at line 441 of file i915_reg.h.
Definition at line 430 of file i915_reg.h.
#define RING_NR_PAGES 0x001FF000 |
Definition at line 437 of file i915_reg.h.
#define RING_PP_DIR_BASE | ( | ring | ) | ((ring)->mmio_base+0x228) |
Definition at line 94 of file i915_reg.h.
#define RING_PP_DIR_BASE_READ | ( | ring | ) | ((ring)->mmio_base+0x518) |
Definition at line 95 of file i915_reg.h.
#define RING_PP_DIR_DCLV | ( | ring | ) | ((ring)->mmio_base+0x220) |
Definition at line 96 of file i915_reg.h.
#define RING_REPORT_128K 0x00000004 |
Definition at line 440 of file i915_reg.h.
#define RING_REPORT_64K 0x00000002 |
Definition at line 439 of file i915_reg.h.
#define RING_REPORT_MASK 0x00000006 |
Definition at line 438 of file i915_reg.h.
Definition at line 408 of file i915_reg.h.
Definition at line 410 of file i915_reg.h.
Definition at line 411 of file i915_reg.h.
Definition at line 406 of file i915_reg.h.
Definition at line 432 of file i915_reg.h.
#define RING_VALID 0x00000001 |
Definition at line 443 of file i915_reg.h.
#define RING_VALID_MASK 0x00000001 |
Definition at line 442 of file i915_reg.h.
#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ |
Definition at line 446 of file i915_reg.h.
#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ |
Definition at line 445 of file i915_reg.h.
#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ |
Definition at line 447 of file i915_reg.h.
#define RR_HW_CTL 0x45300 |
Definition at line 2979 of file i915_reg.h.
#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 |
Definition at line 2981 of file i915_reg.h.
#define RR_HW_LOW_POWER_FRAMES_MASK 0xff |
Definition at line 2980 of file i915_reg.h.
#define RST_PCH_HNDSHK_EN (1<<4) |
Definition at line 4381 of file i915_reg.h.
#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 |
Definition at line 390 of file i915_reg.h.
#define SBI_ADDR 0xC6000 |
Definition at line 4261 of file i915_reg.h.
#define SBI_BUSY (0x1<<0) |
Definition at line 4272 of file i915_reg.h.
#define SBI_CTL_DEST_ICLK (0x0<<16) |
Definition at line 4264 of file i915_reg.h.
#define SBI_CTL_DEST_MPHY (0x1<<16) |
Definition at line 4265 of file i915_reg.h.
#define SBI_CTL_OP_CRRD (0x6<<8) |
Definition at line 4268 of file i915_reg.h.
#define SBI_CTL_OP_CRWR (0x7<<8) |
Definition at line 4269 of file i915_reg.h.
#define SBI_CTL_OP_IORD (0x2<<8) |
Definition at line 4266 of file i915_reg.h.
#define SBI_CTL_OP_IOWR (0x3<<8) |
Definition at line 4267 of file i915_reg.h.
#define SBI_CTL_STAT 0xC6008 |
Definition at line 4263 of file i915_reg.h.
#define SBI_DATA 0xC6004 |
Definition at line 4262 of file i915_reg.h.
#define SBI_DBUFF0 0x2a00 |
Definition at line 4289 of file i915_reg.h.
#define SBI_DBUFF0_ENABLE (1<<0) |
Definition at line 4290 of file i915_reg.h.
#define SBI_READY (0x0<<0) |
Definition at line 4273 of file i915_reg.h.
#define SBI_RESPONSE_FAIL (0x1<<1) |
Definition at line 4270 of file i915_reg.h.
#define SBI_RESPONSE_SUCCESS (0x0<<1) |
Definition at line 4271 of file i915_reg.h.
#define SBI_SSCAUXDIV6 0x0610 |
Definition at line 4287 of file i915_reg.h.
Definition at line 4288 of file i915_reg.h.
#define SBI_SSCCTL 0x020c |
Definition at line 4283 of file i915_reg.h.
#define SBI_SSCCTL6 0x060C |
Definition at line 4284 of file i915_reg.h.
#define SBI_SSCCTL_DISABLE (1<<0) |
Definition at line 4286 of file i915_reg.h.
#define SBI_SSCCTL_PATHALT (1<<3) |
Definition at line 4285 of file i915_reg.h.
#define SBI_SSCDIVINTPHASE6 0x0600 |
Definition at line 4276 of file i915_reg.h.
Definition at line 4281 of file i915_reg.h.
Definition at line 4278 of file i915_reg.h.
#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) |
Definition at line 4277 of file i915_reg.h.
Definition at line 4280 of file i915_reg.h.
#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) |
Definition at line 4279 of file i915_reg.h.
#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) |
Definition at line 4282 of file i915_reg.h.
#define SC_ENABLE (0x1<<0) |
Definition at line 248 of file i915_reg.h.
#define SC_ENABLE_MASK (0x1<<0) |
Definition at line 247 of file i915_reg.h.
#define SC_UPDATE_SCISSOR (0x1<<1) |
Definition at line 246 of file i915_reg.h.
#define SCI_XMAX_MASK (0xffff<<0) |
Definition at line 254 of file i915_reg.h.
#define SCI_XMIN_MASK (0xffff<<0) |
Definition at line 252 of file i915_reg.h.
#define SCI_YMAX_MASK (0xffff<<16) |
Definition at line 253 of file i915_reg.h.
#define SCI_YMIN_MASK (0xffff<<16) |
Definition at line 251 of file i915_reg.h.
#define SCPD0 0x0209c /* 915+ only */ |
Definition at line 520 of file i915_reg.h.
#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) |
Definition at line 3269 of file i915_reg.h.
#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) |
Definition at line 3266 of file i915_reg.h.
#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) |
Definition at line 3263 of file i915_reg.h.
#define SDE_AUDIO_CP_CHG_CPT |
Definition at line 3274 of file i915_reg.h.
#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) |
Definition at line 3268 of file i915_reg.h.
#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) |
Definition at line 3265 of file i915_reg.h.
#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) |
Definition at line 3262 of file i915_reg.h.
#define SDE_AUDIO_CP_REQ_CPT |
Definition at line 3271 of file i915_reg.h.
#define SDE_AUDIO_HDCP_MASK (3 << 22) |
Definition at line 3215 of file i915_reg.h.
#define SDE_AUDIO_HDCP_TRANSA (1 << 22) |
Definition at line 3214 of file i915_reg.h.
#define SDE_AUDIO_HDCP_TRANSB (1 << 23) |
Definition at line 3213 of file i915_reg.h.
#define SDE_AUDIO_POWER_B (1 << 25) |
Definition at line 3209 of file i915_reg.h.
#define SDE_AUDIO_POWER_B_CPT (1 << 29) |
Definition at line 3246 of file i915_reg.h.
#define SDE_AUDIO_POWER_C (1 << 26) |
Definition at line 3208 of file i915_reg.h.
#define SDE_AUDIO_POWER_C_CPT (1 << 30) |
Definition at line 3245 of file i915_reg.h.
#define SDE_AUDIO_POWER_D (1 << 27) |
Definition at line 3207 of file i915_reg.h.
#define SDE_AUDIO_POWER_D_CPT (1UL << 31) |
Definition at line 3244 of file i915_reg.h.
#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) |
Definition at line 3211 of file i915_reg.h.
#define SDE_AUDIO_POWER_MASK_CPT (7 << 29) |
Definition at line 3248 of file i915_reg.h.
#define SDE_AUDIO_POWER_SHIFT (25) |
Definition at line 3210 of file i915_reg.h.
#define SDE_AUDIO_POWER_SHIFT_CPT 29 |
Definition at line 3247 of file i915_reg.h.
#define SDE_AUDIO_TRANS_MASK (3 << 20) |
Definition at line 3218 of file i915_reg.h.
#define SDE_AUDIO_TRANSA (1 << 20) |
Definition at line 3217 of file i915_reg.h.
#define SDE_AUDIO_TRANSB (1 << 21) |
Definition at line 3216 of file i915_reg.h.
#define SDE_AUX_MASK (7 << 13) |
Definition at line 3227 of file i915_reg.h.
#define SDE_AUX_MASK_CPT (7 << 25) |
Definition at line 3252 of file i915_reg.h.
#define SDE_AUXB (1 << 13) |
Definition at line 3226 of file i915_reg.h.
#define SDE_AUXB_CPT (1 << 25) |
Definition at line 3251 of file i915_reg.h.
#define SDE_AUXC (1 << 14) |
Definition at line 3225 of file i915_reg.h.
#define SDE_AUXC_CPT (1 << 26) |
Definition at line 3250 of file i915_reg.h.
#define SDE_AUXD (1 << 15) |
Definition at line 3224 of file i915_reg.h.
#define SDE_AUXD_CPT (1 << 27) |
Definition at line 3249 of file i915_reg.h.
#define SDE_CRT_HOTPLUG (1 << 11) |
Definition at line 3229 of file i915_reg.h.
#define SDE_CRT_HOTPLUG_CPT (1 << 19) |
Definition at line 3256 of file i915_reg.h.
#define SDE_FDI_MASK (3 << 16) |
Definition at line 3223 of file i915_reg.h.
#define SDE_FDI_MASK_CPT |
Definition at line 3277 of file i915_reg.h.
#define SDE_FDI_RXA (1 << 16) |
Definition at line 3222 of file i915_reg.h.
#define SDE_FDI_RXA_CPT (1 << 0) |
Definition at line 3270 of file i915_reg.h.
#define SDE_FDI_RXB (1 << 17) |
Definition at line 3221 of file i915_reg.h.
#define SDE_FDI_RXB_CPT (1 << 4) |
Definition at line 3267 of file i915_reg.h.
#define SDE_FDI_RXC_CPT (1 << 8) |
Definition at line 3264 of file i915_reg.h.
#define SDE_GMBUS (1 << 24) |
Definition at line 3212 of file i915_reg.h.
#define SDE_GMBUS_CPT (1 << 17) |
Definition at line 3261 of file i915_reg.h.
#define SDE_HOTPLUG_MASK (0xf << 8) |
Definition at line 3234 of file i915_reg.h.
#define SDE_HOTPLUG_MASK_CPT |
Definition at line 3257 of file i915_reg.h.
#define SDE_POISON (1 << 19) |
Definition at line 3219 of file i915_reg.h.
#define SDE_PORTB_HOTPLUG (1 << 8) |
Definition at line 3232 of file i915_reg.h.
#define SDE_PORTB_HOTPLUG_CPT (1 << 21) |
Definition at line 3255 of file i915_reg.h.
#define SDE_PORTC_HOTPLUG (1 << 9) |
Definition at line 3231 of file i915_reg.h.
#define SDE_PORTC_HOTPLUG_CPT (1 << 22) |
Definition at line 3254 of file i915_reg.h.
#define SDE_PORTD_HOTPLUG (1 << 10) |
Definition at line 3230 of file i915_reg.h.
#define SDE_PORTD_HOTPLUG_CPT (1 << 23) |
Definition at line 3253 of file i915_reg.h.
#define SDE_SDVOB_HOTPLUG (1 << 6) |
Definition at line 3233 of file i915_reg.h.
#define SDE_TRANS_MASK (0x3f) |
Definition at line 3241 of file i915_reg.h.
#define SDE_TRANSA_CRC_DONE (1 << 2) |
Definition at line 3238 of file i915_reg.h.
#define SDE_TRANSA_CRC_ERR (1 << 1) |
Definition at line 3239 of file i915_reg.h.
#define SDE_TRANSA_FIFO_UNDER (1 << 0) |
Definition at line 3240 of file i915_reg.h.
#define SDE_TRANSB_CRC_DONE (1 << 5) |
Definition at line 3235 of file i915_reg.h.
#define SDE_TRANSB_CRC_ERR (1 << 4) |
Definition at line 3236 of file i915_reg.h.
#define SDE_TRANSB_FIFO_UNDER (1 << 3) |
Definition at line 3237 of file i915_reg.h.
#define SDEIER 0xc400c |
Definition at line 3284 of file i915_reg.h.
#define SDEIIR 0xc4008 |
Definition at line 3283 of file i915_reg.h.
#define SDEIMR 0xc4004 |
Definition at line 3282 of file i915_reg.h.
#define SDEISR 0xc4000 |
Definition at line 3281 of file i915_reg.h.
#define SDVO_AUDIO_ENABLE (1 << 6) |
Definition at line 1389 of file i915_reg.h.
#define SDVO_BORDER_ENABLE (1 << 7) |
Definition at line 1388 of file i915_reg.h.
#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) |
Definition at line 1381 of file i915_reg.h.
#define SDVO_COLOR_RANGE_16_235 (1 << 8) |
Definition at line 1387 of file i915_reg.h.
#define SDVO_DETECTED (1 << 2) |
Definition at line 1395 of file i915_reg.h.
#define SDVO_ENABLE (1UL << 31) |
Definition at line 1366 of file i915_reg.h.
#define SDVO_ENCODING (0) |
Definition at line 3714 of file i915_reg.h.
#define SDVO_ENCODING_HDMI (0x2 << 10) |
Definition at line 1384 of file i915_reg.h.
#define SDVO_ENCODING_SDVO (0x0 << 10) |
Definition at line 1383 of file i915_reg.h.
#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) |
New with 965, default is to be set.
Definition at line 1393 of file i915_reg.h.
#define SDVO_INTERRUPT_ENABLE (1 << 26) |
Definition at line 1369 of file i915_reg.h.
#define SDVO_MULTIPLIER_MASK 0x000000ff |
Definition at line 966 of file i915_reg.h.
#define SDVO_MULTIPLIER_SHIFT_HIRES 4 |
Definition at line 967 of file i915_reg.h.
#define SDVO_MULTIPLIER_SHIFT_VGA 0 |
Definition at line 968 of file i915_reg.h.
#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) |
Requird for HDMI operation.
Definition at line 1386 of file i915_reg.h.
#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) |
Definition at line 1380 of file i915_reg.h.
#define SDVO_PHASE_SELECT_MASK (15 << 19) |
Definition at line 1379 of file i915_reg.h.
#define SDVO_PIPE_B_SELECT (1 << 30) |
Definition at line 1367 of file i915_reg.h.
#define SDVO_PORT_MULTIPLY_MASK (7 << 23) |
915G/GM SDVO pixel multiplier.
Programmed value is multiplier - 1, up to 5x.
Definition at line 1377 of file i915_reg.h.
#define SDVO_PORT_MULTIPLY_SHIFT 23 |
Definition at line 1378 of file i915_reg.h.
#define SDVO_STALL_SELECT (1 << 29) |
Definition at line 1368 of file i915_reg.h.
#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) |
New with 965, default is to be set.
Definition at line 1391 of file i915_reg.h.
#define SDVOB 0x61140 |
Definition at line 1364 of file i915_reg.h.
#define SDVOB_BORDER_ENABLE (1 << 7) |
Definition at line 3720 of file i915_reg.h.
#define SDVOB_HOTPLUG_ENABLE (1 << 23) |
Definition at line 3713 of file i915_reg.h.
#define SDVOB_HOTPLUG_INT_EN (1 << 26) |
Definition at line 1313 of file i915_reg.h.
#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) |
Definition at line 1357 of file i915_reg.h.
#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) |
Definition at line 1361 of file i915_reg.h.
#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) |
Definition at line 1359 of file i915_reg.h.
#define SDVOB_PCIE_CONCURRENCY (1 << 3) |
Definition at line 1394 of file i915_reg.h.
#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) |
Definition at line 1397 of file i915_reg.h.
#define SDVOC 0x61160 |
Definition at line 1365 of file i915_reg.h.
#define SDVOC_GANG_MODE (1 << 16) |
Definition at line 1382 of file i915_reg.h.
#define SDVOC_HOTPLUG_INT_EN (1 << 25) |
Definition at line 1314 of file i915_reg.h.
#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) |
Definition at line 1356 of file i915_reg.h.
#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) |
Definition at line 1360 of file i915_reg.h.
#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) |
Definition at line 1358 of file i915_reg.h.
#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) |
Definition at line 1398 of file i915_reg.h.
#define SFUSE_STRAP 0xc2014 |
Definition at line 4369 of file i915_reg.h.
#define SFUSE_STRAP_DDIB_DETECTED (1<<2) |
Definition at line 4370 of file i915_reg.h.
#define SFUSE_STRAP_DDIC_DETECTED (1<<1) |
Definition at line 4371 of file i915_reg.h.
#define SFUSE_STRAP_DDID_DETECTED (1<<0) |
Definition at line 4372 of file i915_reg.h.
#define SNB_CPU_FENCE_ENABLE (1<<29) |
Definition at line 795 of file i915_reg.h.
#define SNB_CURSOR_DFT_SRWM 8 |
Definition at line 2637 of file i915_reg.h.
#define SNB_CURSOR_DFTWM 8 |
Definition at line 2630 of file i915_reg.h.
#define SNB_CURSOR_FIFO 32 |
Definition at line 2628 of file i915_reg.h.
#define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */ |
Definition at line 2636 of file i915_reg.h.
#define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */ |
Definition at line 2629 of file i915_reg.h.
#define SNB_CURSOR_SR_FIFO 64 |
Definition at line 2635 of file i915_reg.h.
#define SNB_DISPLAY_DFT_SRWM 0x3f |
Definition at line 2634 of file i915_reg.h.
#define SNB_DISPLAY_DFTWM 8 |
Definition at line 2627 of file i915_reg.h.
#define SNB_DISPLAY_FIFO 128 |
Definition at line 2625 of file i915_reg.h.
#define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */ |
Definition at line 2633 of file i915_reg.h.
#define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */ |
Definition at line 2626 of file i915_reg.h.
#define SNB_DISPLAY_SR_FIFO 512 |
Definition at line 2632 of file i915_reg.h.
#define SNB_DPFC_CTL_SA 0x100100 |
Definition at line 794 of file i915_reg.h.
#define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */ |
Definition at line 2639 of file i915_reg.h.
#define SNB_FIFO_LINE_SIZE 64 |
Definition at line 2641 of file i915_reg.h.
#define SNB_GMCH_CTRL 0x50 |
Definition at line 22 of file i915_reg.h.
#define SNB_GMCH_GGMS_MASK 0x3 |
Definition at line 24 of file i915_reg.h.
#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */ |
Definition at line 23 of file i915_reg.h.
#define SNB_GMCH_GMS_MASK 0x1f |
Definition at line 26 of file i915_reg.h.
#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */ |
Definition at line 25 of file i915_reg.h.
#define SOUTH_CHICKEN1 0xc2000 |
Definition at line 3556 of file i915_reg.h.
#define SOUTH_CHICKEN2 0xc2004 |
Definition at line 3562 of file i915_reg.h.
#define SOUTH_DSPCLK_GATE_D 0xc2020 |
Definition at line 3574 of file i915_reg.h.
#define SPLL_CTL 0x46020 |
Definition at line 4298 of file i915_reg.h.
#define SPLL_PLL_ENABLE (1UL<<31) |
Definition at line 4299 of file i915_reg.h.
#define SPLL_PLL_FREQ_1350MHz (1<<26) |
Definition at line 4303 of file i915_reg.h.
#define SPLL_PLL_FREQ_810MHz (0<<26) |
Definition at line 4302 of file i915_reg.h.
#define SPLL_PLL_NON_SSC (2<<28) |
Definition at line 4301 of file i915_reg.h.
#define SPLL_PLL_SSC (1<<28) |
Definition at line 4300 of file i915_reg.h.
Definition at line 2942 of file i915_reg.h.
#define SPRGAMC | ( | pipe | ) | _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) |
Definition at line 2954 of file i915_reg.h.
#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<26) |
Definition at line 2418 of file i915_reg.h.
#define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<15) |
Definition at line 2428 of file i915_reg.h.
#define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30) |
Definition at line 2409 of file i915_reg.h.
#define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15) |
Definition at line 2427 of file i915_reg.h.
#define SPRITE_CSC_ENABLE (1<<24) |
Definition at line 2892 of file i915_reg.h.
#define SPRITE_DEST_KEY (1<<2) |
Definition at line 2905 of file i915_reg.h.
#define SPRITE_ENABLE (1UL<<31) |
Definition at line 2883 of file i915_reg.h.
#define SPRITE_FILTER_ENHANCING (1<<29) |
Definition at line 2921 of file i915_reg.h.
#define SPRITE_FILTER_MASK (3<<29) |
Definition at line 2919 of file i915_reg.h.
#define SPRITE_FILTER_MEDIUM (0<<29) |
Definition at line 2920 of file i915_reg.h.
#define SPRITE_FILTER_SOFTENING (2<<29) |
Definition at line 2922 of file i915_reg.h.
#define SPRITE_FORMAT_RGBX101010 (1<<25) |
Definition at line 2887 of file i915_reg.h.
#define SPRITE_FORMAT_RGBX161616 (3<<25) |
Definition at line 2889 of file i915_reg.h.
#define SPRITE_FORMAT_RGBX888 (2<<25) |
Definition at line 2888 of file i915_reg.h.
#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ |
Definition at line 2891 of file i915_reg.h.
#define SPRITE_FORMAT_YUV422 (0<<25) |
Definition at line 2886 of file i915_reg.h.
#define SPRITE_FORMAT_YUV444 (4<<25) |
Definition at line 2890 of file i915_reg.h.
#define SPRITE_GAMMA_ENABLE (1<<30) |
Definition at line 2884 of file i915_reg.h.
#define SPRITE_INT_GAMMA_ENABLE (1<<13) |
Definition at line 2903 of file i915_reg.h.
#define SPRITE_PIXFORMAT_MASK (7<<25) |
Definition at line 2885 of file i915_reg.h.
#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ |
Definition at line 2894 of file i915_reg.h.
#define SPRITE_SCALE_ENABLE (1UL<<31) |
Definition at line 2918 of file i915_reg.h.
#define SPRITE_SOURCE_KEY (1<<22) |
Definition at line 2893 of file i915_reg.h.
#define SPRITE_TILED (1<<10) |
Definition at line 2904 of file i915_reg.h.
#define SPRITE_TRICKLE_FEED_DISABLE (1<<14) |
Definition at line 2902 of file i915_reg.h.
#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) |
Definition at line 2924 of file i915_reg.h.
#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ |
Definition at line 2923 of file i915_reg.h.
#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) |
Definition at line 2897 of file i915_reg.h.
#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ |
Definition at line 2896 of file i915_reg.h.
#define SPRITE_YUV_ORDER_UYVY (1<<16) |
Definition at line 2899 of file i915_reg.h.
#define SPRITE_YUV_ORDER_VYUY (3<<16) |
Definition at line 2901 of file i915_reg.h.
#define SPRITE_YUV_ORDER_YUYV (0<<16) |
Definition at line 2898 of file i915_reg.h.
#define SPRITE_YUV_ORDER_YVYU (2<<16) |
Definition at line 2900 of file i915_reg.h.
#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) |
Definition at line 2895 of file i915_reg.h.
#define SPRITEA_FLIPDONE_INT_EN (1<<17) |
Definition at line 2468 of file i915_reg.h.
#define SPRITEA_INVALID_GTT_INT_EN (1<<17) |
Definition at line 2478 of file i915_reg.h.
#define SPRITEA_INVALID_GTT_STATUS (1<<1) |
Definition at line 2487 of file i915_reg.h.
#define SPRITEB_FLIPDONE_INT_EN (1<<18) |
Definition at line 2467 of file i915_reg.h.
#define SPRITEB_INVALID_GTT_INT_EN (1<<18) |
Definition at line 2477 of file i915_reg.h.
#define SPRITEB_INVALID_GTT_STATUS (1<<2) |
Definition at line 2486 of file i915_reg.h.
#define SPRITEC_FLIPDONE_INT_EN (1<<25) |
Definition at line 2462 of file i915_reg.h.
#define SPRITEC_INVALID_GTT_INT_EN (1<<20) |
Definition at line 2475 of file i915_reg.h.
#define SPRITEC_INVALID_GTT_STATUS (1<<4) |
Definition at line 2484 of file i915_reg.h.
#define SPRITED_FLIPDONE_INT_EN (1<<26) |
Definition at line 2461 of file i915_reg.h.
#define SPRITED_INVALID_GTT_INT_EN (1<<21) |
Definition at line 2474 of file i915_reg.h.
#define SPRITED_INVALID_GTT_STATUS (1<<5) |
Definition at line 2483 of file i915_reg.h.
#define SPRKEYMAX | ( | pipe | ) | _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) |
Definition at line 2950 of file i915_reg.h.
#define SPRKEYMSK | ( | pipe | ) | _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) |
Definition at line 2948 of file i915_reg.h.
#define SPRKEYVAL | ( | pipe | ) | _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) |
Definition at line 2947 of file i915_reg.h.
#define SPRLINOFF | ( | pipe | ) | _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) |
Definition at line 2943 of file i915_reg.h.
#define SPROFFSET | ( | pipe | ) | _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) |
Definition at line 2952 of file i915_reg.h.
Definition at line 2945 of file i915_reg.h.
#define SPRSCALE | ( | pipe | ) | _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) |
Definition at line 2953 of file i915_reg.h.
#define SPRSIZE | ( | pipe | ) | _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) |
Definition at line 2946 of file i915_reg.h.
#define SPRSTRIDE | ( | pipe | ) | _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) |
Definition at line 2944 of file i915_reg.h.
#define SPRSURF | ( | pipe | ) | _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) |
Definition at line 2949 of file i915_reg.h.
#define SPRSURFLIVE | ( | pipe | ) | _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) |
Definition at line 2955 of file i915_reg.h.
#define SPRTILEOFF | ( | pipe | ) | _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) |
Definition at line 2951 of file i915_reg.h.
#define SR01 1 |
Definition at line 911 of file i915_reg.h.
#define SR01_SCREEN_OFF (1<<5) |
Definition at line 912 of file i915_reg.h.
#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) |
Definition at line 264 of file i915_reg.h.
#define SRX_DATA 0x3c5 |
Definition at line 910 of file i915_reg.h.
#define SRX_INDEX 0x3c4 |
Definition at line 909 of file i915_reg.h.
#define SV_CLOCK_GATE_DISABLE (1 << 0) |
This bit must be set on 855,865.
Definition at line 1094 of file i915_reg.h.
#define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) |
Definition at line 2993 of file i915_reg.h.
#define SWF00 0x71410 |
Definition at line 2778 of file i915_reg.h.
#define SWF01 0x71414 |
Definition at line 2779 of file i915_reg.h.
#define SWF02 0x71418 |
Definition at line 2780 of file i915_reg.h.
#define SWF03 0x7141c |
Definition at line 2781 of file i915_reg.h.
#define SWF04 0x71420 |
Definition at line 2782 of file i915_reg.h.
#define SWF05 0x71424 |
Definition at line 2783 of file i915_reg.h.
#define SWF06 0x71428 |
Definition at line 2784 of file i915_reg.h.
#define SWF10 0x70410 |
Definition at line 2785 of file i915_reg.h.
#define SWF11 0x70414 |
Definition at line 2786 of file i915_reg.h.
#define SWF14 0x71420 |
Definition at line 2787 of file i915_reg.h.
#define SWF30 0x72414 |
Definition at line 2788 of file i915_reg.h.
#define SWF31 0x72418 |
Definition at line 2789 of file i915_reg.h.
#define SWF32 0x7241c |
Definition at line 2790 of file i915_reg.h.
#define TAIL_ADDR 0x001FFFF8 |
Definition at line 433 of file i915_reg.h.
#define TILECTL 0x101000 |
Definition at line 393 of file i915_reg.h.
#define TILECTL_BACKSNOOP_DIS (1 << 3) |
Definition at line 396 of file i915_reg.h.
#define TILECTL_SWZCTL (1 << 0) |
Definition at line 394 of file i915_reg.h.
#define TILECTL_TLB_PREFETCH_DIS (1 << 2) |
Definition at line 395 of file i915_reg.h.
#define TMDS_ENCODING (2 << 10) |
Definition at line 3715 of file i915_reg.h.
#define TRANS_10BPC (1<<5) |
Definition at line 3543 of file i915_reg.h.
#define TRANS_12BPC (3<<5) |
Definition at line 3545 of file i915_reg.h.
#define TRANS_6BPC (2<<5) |
Definition at line 3544 of file i915_reg.h.
#define TRANS_8BPC (0<<5) |
Definition at line 3542 of file i915_reg.h.
#define TRANS_CHICKEN1 | ( | pipe | ) | _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) |
Definition at line 3549 of file i915_reg.h.
#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) |
Definition at line 3550 of file i915_reg.h.
#define TRANS_CHICKEN2 | ( | pipe | ) | _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) |
Definition at line 3553 of file i915_reg.h.
#define TRANS_CHICKEN2_TIMING_OVERRIDE (1UL<<31) |
Definition at line 3554 of file i915_reg.h.
#define TRANS_CLK_SEL | ( | tran | ) | _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) |
Definition at line 4332 of file i915_reg.h.
#define TRANS_CLK_SEL_A 0x46140 |
Definition at line 4330 of file i915_reg.h.
#define TRANS_CLK_SEL_B 0x46144 |
Definition at line 4331 of file i915_reg.h.
#define TRANS_CLK_SEL_DISABLED (0x0<<29) |
Definition at line 4334 of file i915_reg.h.
Definition at line 4335 of file i915_reg.h.
#define TRANS_DDI_BFI_ENABLE (1<<4) |
Definition at line 4201 of file i915_reg.h.
#define TRANS_DDI_BPC_10 (1<<20) |
Definition at line 4191 of file i915_reg.h.
#define TRANS_DDI_BPC_12 (3<<20) |
Definition at line 4193 of file i915_reg.h.
#define TRANS_DDI_BPC_6 (2<<20) |
Definition at line 4192 of file i915_reg.h.
#define TRANS_DDI_BPC_8 (0<<20) |
Definition at line 4190 of file i915_reg.h.
#define TRANS_DDI_BPC_MASK (7<<20) |
Definition at line 4189 of file i915_reg.h.
#define TRANS_DDI_EDP_INPUT_A_ON (0<<12) |
Definition at line 4197 of file i915_reg.h.
#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) |
Definition at line 4198 of file i915_reg.h.
#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) |
Definition at line 4199 of file i915_reg.h.
#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) |
Definition at line 4200 of file i915_reg.h.
#define TRANS_DDI_EDP_INPUT_MASK (7<<12) |
Definition at line 4196 of file i915_reg.h.
#define TRANS_DDI_FUNC_CTL | ( | tran | ) |
Definition at line 4176 of file i915_reg.h.
#define TRANS_DDI_FUNC_CTL_A 0x60400 |
Definition at line 4172 of file i915_reg.h.
#define TRANS_DDI_FUNC_CTL_B 0x61400 |
Definition at line 4173 of file i915_reg.h.
#define TRANS_DDI_FUNC_CTL_C 0x62400 |
Definition at line 4174 of file i915_reg.h.
#define TRANS_DDI_FUNC_CTL_EDP 0x6F400 |
Definition at line 4175 of file i915_reg.h.
#define TRANS_DDI_FUNC_ENABLE (1UL<<31) |
Definition at line 4178 of file i915_reg.h.
#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) |
Definition at line 4187 of file i915_reg.h.
#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) |
Definition at line 4186 of file i915_reg.h.
#define TRANS_DDI_MODE_SELECT_DVI (1<<24) |
Definition at line 4185 of file i915_reg.h.
#define TRANS_DDI_MODE_SELECT_FDI (4<<24) |
Definition at line 4188 of file i915_reg.h.
#define TRANS_DDI_MODE_SELECT_HDMI (0<<24) |
Definition at line 4184 of file i915_reg.h.
#define TRANS_DDI_MODE_SELECT_MASK (7<<24) |
Definition at line 4183 of file i915_reg.h.
#define TRANS_DDI_PHSYNC (1<<16) |
Definition at line 4195 of file i915_reg.h.
#define TRANS_DDI_PORT_MASK (7<<28) |
Definition at line 4180 of file i915_reg.h.
#define TRANS_DDI_PORT_NONE (0<<28) |
Definition at line 4182 of file i915_reg.h.
#define TRANS_DDI_PORT_WIDTH_X1 (0<<1) |
Definition at line 4202 of file i915_reg.h.
#define TRANS_DDI_PORT_WIDTH_X2 (1<<1) |
Definition at line 4203 of file i915_reg.h.
#define TRANS_DDI_PORT_WIDTH_X4 (3<<1) |
Definition at line 4204 of file i915_reg.h.
#define TRANS_DDI_PVSYNC (1<<17) |
Definition at line 4194 of file i915_reg.h.
Definition at line 4181 of file i915_reg.h.
#define TRANS_DISABLE (0UL<<31) |
Definition at line 3527 of file i915_reg.h.
#define TRANS_DP_10BPC (1<<9) |
Definition at line 3837 of file i915_reg.h.
#define TRANS_DP_12BPC (3<<9) |
Definition at line 3839 of file i915_reg.h.
#define TRANS_DP_6BPC (2<<9) |
Definition at line 3838 of file i915_reg.h.
#define TRANS_DP_8BPC (0<<9) |
Definition at line 3836 of file i915_reg.h.
#define TRANS_DP_AUDIO_ONLY (1<<26) |
Definition at line 3834 of file i915_reg.h.
#define TRANS_DP_AUDIO_ONLY (1<<26) |
Definition at line 3834 of file i915_reg.h.
#define TRANS_DP_BPC_MASK (3<<9) |
Definition at line 3840 of file i915_reg.h.
#define TRANS_DP_CTL | ( | pipe | ) | _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B) |
Definition at line 3827 of file i915_reg.h.
#define TRANS_DP_CTL_A 0xe0300 |
Definition at line 3824 of file i915_reg.h.
#define TRANS_DP_CTL_B 0xe1300 |
Definition at line 3825 of file i915_reg.h.
#define TRANS_DP_CTL_C 0xe2300 |
Definition at line 3826 of file i915_reg.h.
#define TRANS_DP_ENH_FRAMING (1<<18) |
Definition at line 3835 of file i915_reg.h.
#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) |
Definition at line 3843 of file i915_reg.h.
#define TRANS_DP_HSYNC_ACTIVE_LOW 0 |
Definition at line 3844 of file i915_reg.h.
#define TRANS_DP_OUTPUT_ENABLE (1UL<<31) |
Definition at line 3828 of file i915_reg.h.
#define TRANS_DP_PORT_SEL_B (0<<29) |
Definition at line 3829 of file i915_reg.h.
#define TRANS_DP_PORT_SEL_C (1<<29) |
Definition at line 3830 of file i915_reg.h.
#define TRANS_DP_PORT_SEL_D (2<<29) |
Definition at line 3831 of file i915_reg.h.
#define TRANS_DP_PORT_SEL_MASK (3<<29) |
Definition at line 3833 of file i915_reg.h.
#define TRANS_DP_PORT_SEL_NONE (3<<29) |
Definition at line 3832 of file i915_reg.h.
#define TRANS_DP_SYNC_MASK (3<<3) |
Definition at line 3845 of file i915_reg.h.
#define TRANS_DP_VIDEO_AUDIO (0<<26) |
Definition at line 3537 of file i915_reg.h.
#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) |
Definition at line 3841 of file i915_reg.h.
#define TRANS_DP_VSYNC_ACTIVE_LOW 0 |
Definition at line 3842 of file i915_reg.h.
#define TRANS_ENABLE (1UL<<31) |
Definition at line 3528 of file i915_reg.h.
#define TRANS_FSYNC_DELAY_HB1 (0<<27) |
Definition at line 3532 of file i915_reg.h.
#define TRANS_FSYNC_DELAY_HB2 (1<<27) |
Definition at line 3533 of file i915_reg.h.
#define TRANS_FSYNC_DELAY_HB3 (2<<27) |
Definition at line 3534 of file i915_reg.h.
#define TRANS_FSYNC_DELAY_HB4 (3<<27) |
Definition at line 3535 of file i915_reg.h.
#define TRANS_HACTIVE_SHIFT 0 |
Definition at line 3394 of file i915_reg.h.
#define TRANS_HBLANK | ( | pipe | ) | _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B) |
Definition at line 3495 of file i915_reg.h.
#define TRANS_HBLANK_END_SHIFT 16 |
Definition at line 3396 of file i915_reg.h.
#define TRANS_HBLANK_START_SHIFT 0 |
Definition at line 3397 of file i915_reg.h.
#define TRANS_HSYNC | ( | pipe | ) | _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B) |
Definition at line 3496 of file i915_reg.h.
#define TRANS_HSYNC_END_SHIFT 16 |
Definition at line 3399 of file i915_reg.h.
#define TRANS_HSYNC_START_SHIFT 0 |
Definition at line 3400 of file i915_reg.h.
#define TRANS_HTOTAL | ( | pipe | ) | _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) |
Definition at line 3494 of file i915_reg.h.
#define TRANS_HTOTAL_SHIFT 16 |
Definition at line 3393 of file i915_reg.h.
#define TRANS_INTERLACE_MASK (7<<21) |
Definition at line 3538 of file i915_reg.h.
#define TRANS_INTERLACED (3<<21) |
Definition at line 3540 of file i915_reg.h.
#define TRANS_LEGACY_INTERLACED_ILK (2<<21) |
Definition at line 3541 of file i915_reg.h.
#define TRANS_MSA_10_BPC (2<<5) |
Definition at line 4344 of file i915_reg.h.
#define TRANS_MSA_12_BPC (3<<5) |
Definition at line 4345 of file i915_reg.h.
#define TRANS_MSA_16_BPC (4<<5) |
Definition at line 4346 of file i915_reg.h.
#define TRANS_MSA_6_BPC (0<<5) |
Definition at line 4342 of file i915_reg.h.
#define TRANS_MSA_8_BPC (1<<5) |
Definition at line 4343 of file i915_reg.h.
#define TRANS_MSA_MISC | ( | tran | ) |
Definition at line 4339 of file i915_reg.h.
#define TRANS_MSA_SYNC_CLK (1<<0) |
Definition at line 4341 of file i915_reg.h.
#define TRANS_PROGRESSIVE (0<<21) |
Definition at line 3539 of file i915_reg.h.
#define TRANS_STATE_DISABLE (0<<30) |
Definition at line 3530 of file i915_reg.h.
#define TRANS_STATE_ENABLE (1<<30) |
Definition at line 3531 of file i915_reg.h.
#define TRANS_STATE_MASK (1<<30) |
Definition at line 3529 of file i915_reg.h.
#define TRANS_VACTIVE_SHIFT 0 |
Definition at line 3403 of file i915_reg.h.
#define TRANS_VBLANK | ( | pipe | ) | _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) |
Definition at line 3498 of file i915_reg.h.
#define TRANS_VBLANK_END_SHIFT 16 |
Definition at line 3405 of file i915_reg.h.
#define TRANS_VBLANK_START_SHIFT 0 |
Definition at line 3406 of file i915_reg.h.
#define TRANS_VSYNC | ( | pipe | ) | _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) |
Definition at line 3499 of file i915_reg.h.
#define TRANS_VSYNC_END_SHIFT 16 |
Definition at line 3408 of file i915_reg.h.
#define TRANS_VSYNC_START_SHIFT 0 |
Definition at line 3409 of file i915_reg.h.
#define TRANS_VSYNCSHIFT | ( | pipe | ) |
Definition at line 3500 of file i915_reg.h.
#define TRANS_VTOTAL | ( | pipe | ) | _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B) |
Definition at line 3497 of file i915_reg.h.
#define TRANS_VTOTAL_SHIFT 16 |
Definition at line 3402 of file i915_reg.h.
#define TRANSA_DPLL_ENABLE (1<<3) |
Definition at line 3380 of file i915_reg.h.
#define TRANSA_DPLLA_SEL 0 |
Definition at line 3382 of file i915_reg.h.
#define TRANSA_DPLLB_SEL (1<<0) |
Definition at line 3381 of file i915_reg.h.
#define TRANSB_DPLL_ENABLE (1<<7) |
Definition at line 3383 of file i915_reg.h.
#define TRANSB_DPLLA_SEL (0) |
Definition at line 3385 of file i915_reg.h.
#define TRANSB_DPLLB_SEL (1<<4) |
Definition at line 3384 of file i915_reg.h.
#define TRANSC_DPLL_ENABLE (1<<11) |
Definition at line 3386 of file i915_reg.h.
#define TRANSC_DPLLA_SEL (0) |
Definition at line 3388 of file i915_reg.h.
#define TRANSC_DPLLB_SEL (1<<8) |
Definition at line 3387 of file i915_reg.h.
Definition at line 3707 of file i915_reg.h.
Definition at line 3708 of file i915_reg.h.
#define TRANSCODER_MASK (1 << 30) |
Definition at line 3709 of file i915_reg.h.
#define TRANSCODER_MASK_CPT (3 << 29) |
Definition at line 3710 of file i915_reg.h.
#define TRANSCONF | ( | plane | ) | _PIPE(plane, _TRANSACONF, _TRANSBCONF) |
Definition at line 3523 of file i915_reg.h.
#define TRANSDATA_M1 | ( | pipe | ) | _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1) |
Definition at line 3512 of file i915_reg.h.
#define TRANSDATA_M2 | ( | pipe | ) | _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2) |
Definition at line 3514 of file i915_reg.h.
#define TRANSDATA_N1 | ( | pipe | ) | _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1) |
Definition at line 3513 of file i915_reg.h.
#define TRANSDATA_N2 | ( | pipe | ) | _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2) |
Definition at line 3515 of file i915_reg.h.
#define TRANSDPLINK_M1 | ( | pipe | ) | _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1) |
Definition at line 3516 of file i915_reg.h.
#define TRANSDPLINK_M2 | ( | pipe | ) | _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2) |
Definition at line 3518 of file i915_reg.h.
#define TRANSDPLINK_N1 | ( | pipe | ) | _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1) |
Definition at line 3517 of file i915_reg.h.
#define TRANSDPLINK_N2 | ( | pipe | ) | _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2) |
Definition at line 3519 of file i915_reg.h.
Definition at line 3004 of file i915_reg.h.
#define TU_SIZE_MASK 0x7e000000 |
Definition at line 3005 of file i915_reg.h.
#define TV_AU_MASK 0x000003ff |
U attenuation for component video.
Stored in 1.9 fixed point.
Definition at line 1843 of file i915_reg.h.
#define TV_AU_SHIFT 0 |
Definition at line 1844 of file i915_reg.h.
#define TV_AUTO_SCALE (1UL << 31) |
Enables automatic scaling calculation.
If set, the rest of the registers are ignored, and the calculated values can be read back from the register.
Definition at line 2077 of file i915_reg.h.
#define TV_AV_MASK 0x000007ff |
V attenuation for component video.
Stored in 1.9 fixed point.
Definition at line 1860 of file i915_reg.h.
#define TV_AV_SHIFT 0 |
Definition at line 1861 of file i915_reg.h.
#define TV_AY_MASK 0x000003ff |
Y attenuation for component video.
Stored in 1.9 fixed point.
Definition at line 1826 of file i915_reg.h.
#define TV_AY_SHIFT 0 |
Definition at line 1827 of file i915_reg.h.
#define TV_BLACK_LEVEL_MASK 0x01ff0000 |
Controls the DAC level for black.
Definition at line 1879 of file i915_reg.h.
#define TV_BLACK_LEVEL_SHIFT 16 |
Definition at line 1880 of file i915_reg.h.
#define TV_BLANK_LEVEL_MASK 0x000001ff |
Controls the DAC level for blanking.
Definition at line 1882 of file i915_reg.h.
#define TV_BLANK_LEVEL_SHIFT 0 |
Definition at line 1883 of file i915_reg.h.
#define TV_BRIGHTNESS_MASK 0xff000000 |
2s-complement brightness adjustment
Definition at line 1865 of file i915_reg.h.
#define TV_BRIGHTNESS_SHIFT 24 |
Definition at line 1866 of file i915_reg.h.
#define TV_BU_MASK 0x07ff0000 |
Definition at line 1836 of file i915_reg.h.
#define TV_BU_SHIFT 16 |
Definition at line 1837 of file i915_reg.h.
#define TV_BURST_ENA (1UL << 31) |
Enables the colorburst (needed for non-component color)
Definition at line 1895 of file i915_reg.h.
#define TV_BURST_LEVEL_MASK 0x00ff0000 |
Sets the peak amplitude of the colorburst.
Definition at line 2028 of file i915_reg.h.
#define TV_BURST_LEVEL_SHIFT 16 |
Definition at line 2029 of file i915_reg.h.
#define TV_BV_MASK 0x07ff0000 |
Definition at line 1853 of file i915_reg.h.
#define TV_BV_SHIFT 16 |
Definition at line 1854 of file i915_reg.h.
#define TV_BY_MASK 0x07ff0000 |
Definition at line 1819 of file i915_reg.h.
#define TV_BY_SHIFT 16 |
Definition at line 1820 of file i915_reg.h.
#define TV_CC_CONTROL 0x68090 |
Definition at line 2139 of file i915_reg.h.
#define TV_CC_DATA 0x68094 |
Definition at line 2155 of file i915_reg.h.
#define TV_CC_DATA_1_MASK 0x0000007f |
First word of CC data to be transmitted.
Definition at line 2161 of file i915_reg.h.
#define TV_CC_DATA_1_SHIFT 0 |
Definition at line 2162 of file i915_reg.h.
#define TV_CC_DATA_2_MASK 0x007f0000 |
Second word of CC data to be transmitted.
Definition at line 2158 of file i915_reg.h.
#define TV_CC_DATA_2_SHIFT 16 |
Definition at line 2159 of file i915_reg.h.
#define TV_CC_ENABLE (1UL << 31) |
Definition at line 2140 of file i915_reg.h.
#define TV_CC_FID_MASK (1 << 27) |
Specifies which field to send the CC data in.
CC data is usually sent in field 0.
Definition at line 2146 of file i915_reg.h.
#define TV_CC_FID_SHIFT 27 |
Definition at line 2147 of file i915_reg.h.
#define TV_CC_HOFF_MASK 0x03ff0000 |
Sets the horizontal position of the CC data.
Usually 135.
Definition at line 2149 of file i915_reg.h.
#define TV_CC_HOFF_SHIFT 16 |
Definition at line 2150 of file i915_reg.h.
#define TV_CC_LINE_MASK 0x0000003f |
#define TV_CC_LINE_SHIFT 0 |
Definition at line 2153 of file i915_reg.h.
#define TV_CC_RDY (1UL << 31) |
Definition at line 2156 of file i915_reg.h.
#define TV_CLR_KNOBS 0x68028 |
Definition at line 1863 of file i915_reg.h.
#define TV_CLR_LEVEL 0x6802c |
Definition at line 1877 of file i915_reg.h.
#define TV_CONTRAST_MASK 0x00ff0000 |
Contrast adjustment, as a 2.6 unsigned floating point number.
Definition at line 1868 of file i915_reg.h.
#define TV_CONTRAST_SHIFT 16 |
Definition at line 1869 of file i915_reg.h.
#define TV_CSC_U 0x68018 |
Definition at line 1829 of file i915_reg.h.
#define TV_CSC_U2 0x6801c |
Definition at line 1835 of file i915_reg.h.
#define TV_CSC_V 0x68020 |
Definition at line 1846 of file i915_reg.h.
#define TV_CSC_V2 0x68024 |
Definition at line 1852 of file i915_reg.h.
#define TV_CSC_Y 0x68010 |
CSC coefficients are stored in a floating point format with 9 bits of mantissa and 2 or 3 bits of exponent.
The exponent is represented as 2**-n, where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with -1 (0x3) being the only legal negative value.
Definition at line 1812 of file i915_reg.h.
#define TV_CSC_Y2 0x68014 |
Definition at line 1818 of file i915_reg.h.
#define TV_CTL 0x68000 |
Definition at line 1694 of file i915_reg.h.
#define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) |
Bits that must be preserved by software.
Definition at line 1733 of file i915_reg.h.
#define TV_DAC 0x68004 |
Definition at line 1761 of file i915_reg.h.
#define TV_DAC_SAVE 0x00ffff00 |
Definition at line 1762 of file i915_reg.h.
#define TV_ENC_C0_FIX (1 << 10) |
Enables a fix for the 915GM only.
Not sure what it does.
Definition at line 1731 of file i915_reg.h.
#define TV_ENC_ENABLE (1UL << 31) |
Enables the TV encoder.
Definition at line 1696 of file i915_reg.h.
#define TV_ENC_OUTPUT_COMPONENT (2 << 28) |
Outputs Component video (DAC A/B/C)
Definition at line 1704 of file i915_reg.h.
#define TV_ENC_OUTPUT_COMPOSITE (0 << 28) |
Outputs composite video (DAC A only)
Definition at line 1700 of file i915_reg.h.
#define TV_ENC_OUTPUT_SVIDEO (1 << 28) |
Outputs SVideo video (DAC B/C)
Definition at line 1702 of file i915_reg.h.
#define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) |
Outputs Composite and SVideo (DAC A/B/C)
Definition at line 1706 of file i915_reg.h.
#define TV_ENC_PIPEB_SELECT (1 << 30) |
Sources the TV encoder input from pipe B instead of A.
Definition at line 1698 of file i915_reg.h.
#define TV_ENC_SDP_FIX (1 << 11) |
Enables a fix for 480p/576p standard definition modes on the 915GM only.
Definition at line 1725 of file i915_reg.h.
#define TV_EQUAL_ENA (1UL << 31) |
Enables generation of the equalization signal.
Definition at line 1940 of file i915_reg.h.
#define TV_FILTER_CTL_1 0x68080 |
Definition at line 2070 of file i915_reg.h.
#define TV_FILTER_CTL_2 0x68084 |
Definition at line 2103 of file i915_reg.h.
#define TV_FILTER_CTL_3 0x68088 |
Definition at line 2119 of file i915_reg.h.
#define TV_FUSE_STATE_DISABLED (2 << 4) |
Read-only state that reports that TV-out is disabled in hardware.
Definition at line 1740 of file i915_reg.h.
#define TV_FUSE_STATE_ENABLED (0 << 4) |
Read-only state that reports all features enabled.
Definition at line 1736 of file i915_reg.h.
#define TV_FUSE_STATE_MASK (3 << 4) |
Definition at line 1734 of file i915_reg.h.
#define TV_FUSE_STATE_NO_MACROVISION (1 << 4) |
Read-only state that reports that Macrovision is disabled in hardware.
Definition at line 1738 of file i915_reg.h.
#define TV_GU_MASK 0x000007ff |
Definition at line 1832 of file i915_reg.h.
#define TV_GU_SHIFT 0 |
Definition at line 1833 of file i915_reg.h.
#define TV_GV_MASK 0x000007ff |
Definition at line 1849 of file i915_reg.h.
#define TV_GV_SHIFT 0 |
Definition at line 1850 of file i915_reg.h.
#define TV_GY_MASK 0x00000fff |
Definition at line 1815 of file i915_reg.h.
#define TV_GY_SHIFT 0 |
Definition at line 1816 of file i915_reg.h.
#define TV_H_CHROMA_0 0x68200 |
Definition at line 2166 of file i915_reg.h.
#define TV_H_CHROMA_59 0x682ec |
Definition at line 2167 of file i915_reg.h.
#define TV_H_CTL_1 0x68030 |
Definition at line 1885 of file i915_reg.h.
#define TV_H_CTL_2 0x68034 |
Definition at line 1893 of file i915_reg.h.
#define TV_H_CTL_3 0x68038 |
Definition at line 1903 of file i915_reg.h.
#define TV_H_LUMA_0 0x68100 |
Definition at line 2164 of file i915_reg.h.
#define TV_H_LUMA_59 0x681ec |
Definition at line 2165 of file i915_reg.h.
#define TV_HBLANK_END_MASK 0x1fff0000 |
Definition at line 1906 of file i915_reg.h.
#define TV_HBLANK_END_SHIFT 16 |
End of hblank, measured in pixels minus one from start of hsync.
Definition at line 1905 of file i915_reg.h.
#define TV_HBLANK_START_MASK 0x0001fff |
Definition at line 1909 of file i915_reg.h.
#define TV_HBLANK_START_SHIFT 0 |
Start of hblank, measured in pixels minus one from start of hsync.
Definition at line 1908 of file i915_reg.h.
#define TV_HBURST_LEN_MASK 0x0001fff |
Definition at line 1901 of file i915_reg.h.
#define TV_HBURST_LEN_SHIFT 0 |
Length of the colorburst.
Definition at line 1900 of file i915_reg.h.
#define TV_HBURST_START_MASK 0x1fff0000 |
Definition at line 1898 of file i915_reg.h.
#define TV_HBURST_START_SHIFT 16 |
Offset of the colorburst from the start of hsync, in pixels minus one.
Definition at line 1897 of file i915_reg.h.
#define TV_HOTPLUG_INT_EN (1 << 18) |
Definition at line 1315 of file i915_reg.h.
#define TV_HOTPLUG_INT_STATUS (1 << 10) |
Definition at line 1350 of file i915_reg.h.
#define TV_HSCALE_FRAC_MASK 0x00003fff |
Sets the horizontal scaling factor.
This should be the fractional part of the horizontal scaling factor divided by the oversampling rate. TV_HSCALE should be less than 1, and set to:
(src width - 1) / ((oversample * dest width) - 1)
Definition at line 2100 of file i915_reg.h.
#define TV_HSCALE_FRAC_SHIFT 0 |
Definition at line 2101 of file i915_reg.h.
#define TV_HSYNC_END_MASK 0x1fff0000 |
Number of pixels in the hsync.
Definition at line 1887 of file i915_reg.h.
#define TV_HSYNC_END_SHIFT 16 |
Definition at line 1888 of file i915_reg.h.
#define TV_HTOTAL_MASK 0x00001fff |
Total number of pixels minus one in the line (display and blanking).
Definition at line 1890 of file i915_reg.h.
#define TV_HTOTAL_SHIFT 0 |
Definition at line 1891 of file i915_reg.h.
#define TV_HUE_MASK 0x000000ff |
Hue adjustment, as an integer phase angle in degrees.
Definition at line 1874 of file i915_reg.h.
#define TV_HUE_SHIFT 0 |
Definition at line 1875 of file i915_reg.h.
#define TV_NBR_END_MASK 0x07ff0000 |
Definition at line 1914 of file i915_reg.h.
#define TV_NBR_END_SHIFT 16 |
XXX.
Definition at line 1913 of file i915_reg.h.
#define TV_OVERSAMPLE_2X (1 << 18) |
Selects 2x oversampling for 720p and 1080i.
Definition at line 1713 of file i915_reg.h.
#define TV_OVERSAMPLE_4X (0 << 18) |
Selects 4x oversampling for 480i and 576p.
Definition at line 1711 of file i915_reg.h.
#define TV_OVERSAMPLE_8X (3 << 18) |
Selects 8x oversampling.
Definition at line 1717 of file i915_reg.h.
#define TV_OVERSAMPLE_NONE (2 << 18) |
Selects no oversampling for 1080p.
Definition at line 1715 of file i915_reg.h.
#define TV_PAL_BURST (1 << 16) |
Sets the colorburst to PAL mode.
Required for non-M PAL modes.
Definition at line 1721 of file i915_reg.h.
#define TV_PROGRESSIVE (1 << 17) |
Selects progressive mode rather than interlaced.
Definition at line 1719 of file i915_reg.h.
#define TV_RU_MASK 0x07ff0000 |
Definition at line 1830 of file i915_reg.h.
#define TV_RU_SHIFT 16 |
Definition at line 1831 of file i915_reg.h.
#define TV_RV_MASK 0x0fff0000 |
Definition at line 1847 of file i915_reg.h.
#define TV_RV_SHIFT 16 |
Definition at line 1848 of file i915_reg.h.
#define TV_RY_MASK 0x07ff0000 |
Definition at line 1813 of file i915_reg.h.
#define TV_RY_SHIFT 16 |
Definition at line 1814 of file i915_reg.h.
#define TV_SATURATION_MASK 0x0000ff00 |
Saturation adjustment, as a 2.6 unsigned floating point number.
Definition at line 1871 of file i915_reg.h.
#define TV_SATURATION_SHIFT 8 |
Definition at line 1872 of file i915_reg.h.
#define TV_SC_CTL_1 0x68060 |
Definition at line 2012 of file i915_reg.h.
#define TV_SC_CTL_2 0x68064 |
Definition at line 2034 of file i915_reg.h.
#define TV_SC_CTL_3 0x68068 |
Definition at line 2042 of file i915_reg.h.
#define TV_SC_DDA1_EN (1UL << 31) |
Turns on the first subcarrier phase generation DDA.
Definition at line 2014 of file i915_reg.h.
#define TV_SC_DDA2_EN (1 << 30) |
Turns on the first subcarrier phase generation DDA.
Definition at line 2016 of file i915_reg.h.
#define TV_SC_DDA3_EN (1 << 29) |
Turns on the first subcarrier phase generation DDA.
Definition at line 2018 of file i915_reg.h.
#define TV_SC_RESET_EVERY_2 (0 << 24) |
Sets the subcarrier DDA to reset frequency every other field.
Definition at line 2020 of file i915_reg.h.
#define TV_SC_RESET_EVERY_4 (1 << 24) |
Sets the subcarrier DDA to reset frequency every fourth field.
Definition at line 2022 of file i915_reg.h.
#define TV_SC_RESET_EVERY_8 (2 << 24) |
Sets the subcarrier DDA to reset frequency every eighth field.
Definition at line 2024 of file i915_reg.h.
#define TV_SC_RESET_NEVER (3 << 24) |
Sets the subcarrier DDA to never reset the frequency.
Definition at line 2026 of file i915_reg.h.
#define TV_SCDDA1_INC_MASK 0x00000fff |
Sets the increment of the first subcarrier phase generation DDA.
Definition at line 2031 of file i915_reg.h.
#define TV_SCDDA1_INC_SHIFT 0 |
Definition at line 2032 of file i915_reg.h.
#define TV_SCDDA2_INC_MASK 0x00007fff |
Sets the increent of the second subcarrier phase generation DDA.
Definition at line 2039 of file i915_reg.h.
#define TV_SCDDA2_INC_SHIFT 0 |
Definition at line 2040 of file i915_reg.h.
#define TV_SCDDA2_SIZE_MASK 0x7fff0000 |
Sets the rollover for the second subcarrier phase generation DDA.
Definition at line 2036 of file i915_reg.h.
#define TV_SCDDA2_SIZE_SHIFT 16 |
Definition at line 2037 of file i915_reg.h.
#define TV_SCDDA3_INC_MASK 0x00007fff |
Sets the increent of the third subcarrier phase generation DDA.
Definition at line 2047 of file i915_reg.h.
#define TV_SCDDA3_INC_SHIFT 0 |
Definition at line 2048 of file i915_reg.h.
#define TV_SCDDA3_SIZE_MASK 0x7fff0000 |
Sets the rollover for the third subcarrier phase generation DDA.
Definition at line 2044 of file i915_reg.h.
#define TV_SCDDA3_SIZE_SHIFT 16 |
Definition at line 2045 of file i915_reg.h.
#define TV_SLOW_SYNC (1 << 20) |
Enables slow sync generation (945GM only)
Definition at line 1709 of file i915_reg.h.
#define TV_TEST_MODE_MASK (7 << 0) |
Definition at line 1759 of file i915_reg.h.
#define TV_TEST_MODE_MONITOR_DETECT (7 << 0) |
This test mode forces the DACs to 50% of full output.
This is used for load detection in combination with TVDAC_SENSE_MASK
Definition at line 1758 of file i915_reg.h.
#define TV_TEST_MODE_NORMAL (0 << 0) |
Normal operation.
Definition at line 1742 of file i915_reg.h.
#define TV_TEST_MODE_PATTERN_1 (1 << 0) |
Encoder test pattern 1 - combo pattern.
Definition at line 1744 of file i915_reg.h.
#define TV_TEST_MODE_PATTERN_2 (2 << 0) |
Encoder test pattern 2 - full screen vertical 75% color bars.
Definition at line 1746 of file i915_reg.h.
#define TV_TEST_MODE_PATTERN_3 (3 << 0) |
Encoder test pattern 3 - full screen horizontal 75% color bars.
Definition at line 1748 of file i915_reg.h.
#define TV_TEST_MODE_PATTERN_4 (4 << 0) |
Encoder test pattern 4 - random noise.
Definition at line 1750 of file i915_reg.h.
#define TV_TEST_MODE_PATTERN_5 (5 << 0) |
Encoder test pattern 5 - linear color ramps.
Definition at line 1752 of file i915_reg.h.
#define TV_TRILEVEL_SYNC (1 << 21) |
Definition at line 1707 of file i915_reg.h.
#define TV_V_CHROMA_0 0x68400 |
Definition at line 2170 of file i915_reg.h.
#define TV_V_CHROMA_42 0x684a8 |
Definition at line 2171 of file i915_reg.h.
#define TV_V_CTL_1 0x6803c |
Definition at line 1911 of file i915_reg.h.
#define TV_V_CTL_2 0x68040 |
Definition at line 1922 of file i915_reg.h.
#define TV_V_CTL_3 0x68044 |
Definition at line 1938 of file i915_reg.h.
#define TV_V_CTL_4 0x68048 |
Definition at line 1956 of file i915_reg.h.
#define TV_V_CTL_5 0x6804c |
Definition at line 1970 of file i915_reg.h.
#define TV_V_CTL_6 0x68050 |
Definition at line 1984 of file i915_reg.h.
#define TV_V_CTL_7 0x68054 |
Definition at line 1998 of file i915_reg.h.
#define TV_V_FILTER_BYPASS (1 << 29) |
Disables the vertical filter.
This is required on modes more than 1024 pixels wide
Definition at line 2082 of file i915_reg.h.
#define TV_V_LUMA_0 0x68300 |
Definition at line 2168 of file i915_reg.h.
#define TV_V_LUMA_42 0x683a8 |
Definition at line 2169 of file i915_reg.h.
#define TV_VADAPT (1 << 28) |
Enables adaptive vertical filtering.
Definition at line 2084 of file i915_reg.h.
#define TV_VADAPT_MODE_LEAST (0 << 26) |
Selects the least adaptive vertical filtering mode.
Definition at line 2087 of file i915_reg.h.
#define TV_VADAPT_MODE_MASK (3 << 26) |
Definition at line 2085 of file i915_reg.h.
#define TV_VADAPT_MODE_MODERATE (1 << 26) |
Selects the moderately adaptive vertical filtering mode.
Definition at line 2089 of file i915_reg.h.
#define TV_VADAPT_MODE_MOST (3 << 26) |
Selects the most adaptive vertical filtering mode.
Definition at line 2091 of file i915_reg.h.
#define TV_VBURST_END_F1_MASK 0x000000ff |
Offset to the end of vertical colorburst, measured in one less than the number of lines from the start of NBR.
Definition at line 1967 of file i915_reg.h.
#define TV_VBURST_END_F1_SHIFT 0 |
Definition at line 1968 of file i915_reg.h.
#define TV_VBURST_END_F2_MASK 0x000000ff |
Offset to the end of vertical colorburst, measured in one less than the number of lines from the start of NBR.
Definition at line 1981 of file i915_reg.h.
#define TV_VBURST_END_F2_SHIFT 0 |
Definition at line 1982 of file i915_reg.h.
#define TV_VBURST_END_F3_MASK 0x000000ff |
Offset to the end of vertical colorburst, measured in one less than the number of lines from the start of NBR.
Definition at line 1995 of file i915_reg.h.
#define TV_VBURST_END_F3_SHIFT 0 |
Definition at line 1996 of file i915_reg.h.
#define TV_VBURST_END_F4_MASK 0x000000ff |
Offset to the end of vertical colorburst, measured in one less than the number of lines from the start of NBR.
Definition at line 2009 of file i915_reg.h.
#define TV_VBURST_END_F4_SHIFT 0 |
Definition at line 2010 of file i915_reg.h.
#define TV_VBURST_START_F1_MASK 0x003f0000 |
Offset to start of vertical colorburst, measured in one less than the number of lines from vertical start.
Definition at line 1961 of file i915_reg.h.
#define TV_VBURST_START_F1_SHIFT 16 |
Definition at line 1962 of file i915_reg.h.
#define TV_VBURST_START_F2_MASK 0x003f0000 |
Offset to start of vertical colorburst, measured in one less than the number of lines from vertical start.
Definition at line 1975 of file i915_reg.h.
#define TV_VBURST_START_F2_SHIFT 16 |
Definition at line 1976 of file i915_reg.h.
#define TV_VBURST_START_F3_MASK 0x003f0000 |
Offset to start of vertical colorburst, measured in one less than the number of lines from vertical start.
Definition at line 1989 of file i915_reg.h.
#define TV_VBURST_START_F3_SHIFT 16 |
Definition at line 1990 of file i915_reg.h.
#define TV_VBURST_START_F4_MASK 0x003f0000 |
Offset to start of vertical colorburst, measured in one less than the number of lines from vertical start.
Definition at line 2003 of file i915_reg.h.
#define TV_VBURST_START_F4_SHIFT 16 |
Definition at line 2004 of file i915_reg.h.
#define TV_VEQ_LEN_MASK 0x007f0000 |
Length of vsync, in half lines.
Definition at line 1942 of file i915_reg.h.
#define TV_VEQ_LEN_SHIFT 16 |
Definition at line 1943 of file i915_reg.h.
#define TV_VEQ_START_F1_MASK 0x0007f00 |
Offset of the start of equalization in field 1, measured in one less than the number of half lines.
Definition at line 1947 of file i915_reg.h.
#define TV_VEQ_START_F1_SHIFT 8 |
Definition at line 1948 of file i915_reg.h.
#define TV_VEQ_START_F2_MASK 0x000007f |
Offset of the start of equalization in field 2, measured in one less than the number of half lines.
Definition at line 1953 of file i915_reg.h.
#define TV_VEQ_START_F2_SHIFT 0 |
Definition at line 1954 of file i915_reg.h.
#define TV_VI_END_F1_MASK 0x00003f00 |
Definition at line 1917 of file i915_reg.h.
#define TV_VI_END_F1_SHIFT 8 |
XXX.
Definition at line 1916 of file i915_reg.h.
#define TV_VI_END_F2_MASK 0x0000003f |
Definition at line 1920 of file i915_reg.h.
#define TV_VI_END_F2_SHIFT 0 |
XXX.
Definition at line 1919 of file i915_reg.h.
#define TV_VSCALE_FRAC_MASK 0x00007fff |
Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
Definition at line 2116 of file i915_reg.h.
#define TV_VSCALE_FRAC_SHIFT 0 |
Definition at line 2117 of file i915_reg.h.
#define TV_VSCALE_INT_MASK 0x00038000 |
Sets the integer part of the 3.15 fixed-point vertical scaling factor.
TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
Definition at line 2109 of file i915_reg.h.
#define TV_VSCALE_INT_SHIFT 15 |
Definition at line 2110 of file i915_reg.h.
#define TV_VSCALE_IP_FRAC_MASK 0x00007fff |
Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
Definition at line 2136 of file i915_reg.h.
#define TV_VSCALE_IP_FRAC_SHIFT 0 |
Definition at line 2137 of file i915_reg.h.
#define TV_VSCALE_IP_INT_MASK 0x00038000 |
Sets the integer part of the 3.15 fixed-point vertical scaling factor.
TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
Definition at line 2127 of file i915_reg.h.
#define TV_VSCALE_IP_INT_SHIFT 15 |
Definition at line 2128 of file i915_reg.h.
#define TV_VSYNC_LEN_MASK 0x07ff0000 |
Length of vsync, in half lines.
Definition at line 1924 of file i915_reg.h.
#define TV_VSYNC_LEN_SHIFT 16 |
Definition at line 1925 of file i915_reg.h.
#define TV_VSYNC_START_F1_MASK 0x00007f00 |
Offset of the start of vsync in field 1, measured in one less than the number of half lines.
Definition at line 1929 of file i915_reg.h.
#define TV_VSYNC_START_F1_SHIFT 8 |
Definition at line 1930 of file i915_reg.h.
#define TV_VSYNC_START_F2_MASK 0x0000007f |
Offset of the start of vsync in field 2, measured in one less than the number of half lines.
Definition at line 1935 of file i915_reg.h.
#define TV_VSYNC_START_F2_SHIFT 0 |
Definition at line 1936 of file i915_reg.h.
#define TV_WIN_POS 0x68070 |
Definition at line 2050 of file i915_reg.h.
#define TV_WIN_SIZE 0x68074 |
Definition at line 2058 of file i915_reg.h.
#define TV_XPOS_MASK 0x1fff0000 |
X coordinate of the display from the start of horizontal active.
Definition at line 2052 of file i915_reg.h.
#define TV_XPOS_SHIFT 16 |
Definition at line 2053 of file i915_reg.h.
#define TV_XSIZE_MASK 0x1fff0000 |
Horizontal size of the display window, measured in pixels.
Definition at line 2060 of file i915_reg.h.
#define TV_XSIZE_SHIFT 16 |
Definition at line 2061 of file i915_reg.h.
#define TV_YC_SKEW_MASK (7 << 12) |
Field for setting delay of Y compared to C.
Definition at line 1723 of file i915_reg.h.
#define TV_YPOS_MASK 0x00000fff |
Y coordinate of the display from the start of vertical active (NBR)
Definition at line 2055 of file i915_reg.h.
#define TV_YPOS_SHIFT 0 |
Definition at line 2056 of file i915_reg.h.
#define TV_YSIZE_MASK 0x00000fff |
Vertical size of the display window, measured in pixels.
Must be even for interlaced modes.
Definition at line 2067 of file i915_reg.h.
#define TV_YSIZE_SHIFT 0 |
Definition at line 2068 of file i915_reg.h.
#define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ |
Definition at line 1048 of file i915_reg.h.
#define TVDAC_A_SENSE (1 << 30) |
Reports that DAC A voltage is above the detect threshold.
Definition at line 1771 of file i915_reg.h.
#define TVDAC_A_SENSE_CTL (1 << 26) |
Sets the DAC A sense value to high.
Definition at line 1784 of file i915_reg.h.
#define TVDAC_B_SENSE (1 << 29) |
Reports that DAC B voltage is above the detect threshold.
Definition at line 1773 of file i915_reg.h.
#define TVDAC_B_SENSE_CTL (1 << 25) |
Sets the DAC B sense value to high.
Definition at line 1786 of file i915_reg.h.
#define TVDAC_C_SENSE (1 << 28) |
Reports that DAC C voltage is above the detect threshold.
Definition at line 1775 of file i915_reg.h.
#define TVDAC_C_SENSE_CTL (1 << 24) |
Sets the DAC C sense value to high.
Definition at line 1788 of file i915_reg.h.
#define TVDAC_SENSE_MASK (7 << 28) |
Definition at line 1769 of file i915_reg.h.
#define TVDAC_STATE_CHG (1UL << 31) |
Reports that DAC state change logic has reported change (RO).
This gets cleared when TV_DAC_STATE_EN is cleared
Definition at line 1768 of file i915_reg.h.
#define TVDAC_STATE_CHG_EN (1 << 27) |
Enables DAC state detection logic, for load-based TV detection.
The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set to off, for load detection to work.
Definition at line 1782 of file i915_reg.h.
#define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ |
Definition at line 1050 of file i915_reg.h.
#define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ |
Definition at line 1049 of file i915_reg.h.
#define TVIDEO_DIP_CTL | ( | pipe | ) | _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) |
Definition at line 3431 of file i915_reg.h.
#define TVIDEO_DIP_DATA | ( | pipe | ) | _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) |
Definition at line 3432 of file i915_reg.h.
#define TVIDEO_DIP_GCP | ( | pipe | ) | _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) |
Definition at line 3433 of file i915_reg.h.
#define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ |
Definition at line 1047 of file i915_reg.h.
#define UTIL_PIN_CTL 0x48400 |
Definition at line 1666 of file i915_reg.h.
#define UTIL_PIN_ENABLE (1 << 31) |
Definition at line 1667 of file i915_reg.h.
#define UTIL_PIN_MODE_MASK (0xf << 24) |
Definition at line 1672 of file i915_reg.h.
#define UTIL_PIN_MODE_PWM (1 << 24) |
Definition at line 1671 of file i915_reg.h.
Definition at line 1669 of file i915_reg.h.
#define UTIL_PIN_PIPE_MASK (3 << 29) |
Definition at line 1670 of file i915_reg.h.
#define UTIL_PIN_POLARITY (1 << 22) |
Definition at line 1673 of file i915_reg.h.
#define VALLEYVIEW_CURSOR_MAX_WM 64 |
Definition at line 2564 of file i915_reg.h.
#define VALLEYVIEW_FIFO_SIZE 255 |
Definition at line 2541 of file i915_reg.h.
#define VALLEYVIEW_MAX_WM 0xff |
Definition at line 2549 of file i915_reg.h.
#define VBLANK | ( | trans | ) | _TRANSCODER(trans, _VBLANK_A, _VBLANK_B) |
Definition at line 1253 of file i915_reg.h.
#define VERT_AUTO_SCALE (1 << 9) |
Definition at line 1559 of file i915_reg.h.
#define VERT_INTERP_BILINEAR (1 << 10) |
Definition at line 1557 of file i915_reg.h.
#define VERT_INTERP_DISABLE (0 << 10) |
Definition at line 1556 of file i915_reg.h.
#define VERT_INTERP_MASK (3 << 10) |
Definition at line 1558 of file i915_reg.h.
#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) |
Definition at line 1143 of file i915_reg.h.
#define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) |
Definition at line 2996 of file i915_reg.h.
#define VGA0 0x6000 |
Definition at line 876 of file i915_reg.h.
#define VGA0_PD_P1_DIV_2 (1 << 5) |
Definition at line 880 of file i915_reg.h.
#define VGA0_PD_P1_MASK (0x1f << 0) |
Definition at line 882 of file i915_reg.h.
#define VGA0_PD_P1_SHIFT 0 |
Definition at line 881 of file i915_reg.h.
#define VGA0_PD_P2_DIV_4 (1 << 7) |
Definition at line 879 of file i915_reg.h.
#define VGA1 0x6004 |
Definition at line 877 of file i915_reg.h.
#define VGA1_PD_P1_DIV_2 (1 << 13) |
Definition at line 884 of file i915_reg.h.
#define VGA1_PD_P1_MASK (0x1f << 8) |
Definition at line 886 of file i915_reg.h.
#define VGA1_PD_P1_SHIFT 8 |
Definition at line 885 of file i915_reg.h.
#define VGA1_PD_P2_DIV_4 (1 << 15) |
Definition at line 883 of file i915_reg.h.
#define VGA_2X_MODE (1 << 30) |
Definition at line 2960 of file i915_reg.h.
#define VGA_AR_DATA_READ 0x3c1 |
Definition at line 127 of file i915_reg.h.
#define VGA_AR_DATA_WRITE 0x3c0 |
Definition at line 126 of file i915_reg.h.
#define VGA_AR_INDEX 0x3c0 |
Definition at line 124 of file i915_reg.h.
#define VGA_AR_VID_EN (1<<5) |
Definition at line 125 of file i915_reg.h.
#define VGA_CR_DATA_CGA 0x3d5 |
Definition at line 150 of file i915_reg.h.
#define VGA_CR_DATA_MDA 0x3b5 |
Definition at line 148 of file i915_reg.h.
#define VGA_CR_INDEX_CGA 0x3d4 |
Definition at line 149 of file i915_reg.h.
#define VGA_CR_INDEX_MDA 0x3b4 |
Definition at line 147 of file i915_reg.h.
#define VGA_DACDATA 0x3c9 |
Definition at line 145 of file i915_reg.h.
#define VGA_DACMASK 0x3c6 |
Definition at line 142 of file i915_reg.h.
#define VGA_DACRX 0x3c7 |
Definition at line 143 of file i915_reg.h.
#define VGA_DACWX 0x3c8 |
Definition at line 144 of file i915_reg.h.
#define VGA_DISP_DISABLE (1UL << 31) |
Definition at line 2959 of file i915_reg.h.
#define VGA_GR_DATA 0x3cf |
Definition at line 130 of file i915_reg.h.
#define VGA_GR_INDEX 0x3ce |
Definition at line 129 of file i915_reg.h.
#define VGA_GR_MEM_A0000_AFFFF 0 |
Definition at line 137 of file i915_reg.h.
#define VGA_GR_MEM_A0000_BFFFF 1 |
Definition at line 138 of file i915_reg.h.
#define VGA_GR_MEM_B0000_B7FFF 2 |
Definition at line 139 of file i915_reg.h.
#define VGA_GR_MEM_B0000_BFFFF 3 |
Definition at line 140 of file i915_reg.h.
#define VGA_GR_MEM_MODE_MASK 0xc |
Definition at line 135 of file i915_reg.h.
#define VGA_GR_MEM_MODE_SHIFT 2 |
Definition at line 136 of file i915_reg.h.
#define VGA_GR_MEM_READ_MODE_PLANE 1 |
Definition at line 133 of file i915_reg.h.
#define VGA_GR_MEM_READ_MODE_SHIFT 3 |
Definition at line 132 of file i915_reg.h.
#define VGA_MSR_CGA_MODE (1<<0) |
Definition at line 119 of file i915_reg.h.
#define VGA_MSR_MEM_EN (1<<1) |
Definition at line 118 of file i915_reg.h.
#define VGA_MSR_READ 0x3cc |
Definition at line 117 of file i915_reg.h.
#define VGA_MSR_WRITE 0x3c2 |
Definition at line 116 of file i915_reg.h.
#define VGA_PD 0x6010 |
Definition at line 878 of file i915_reg.h.
#define VGA_PIPE_B_SELECT (1 << 29) |
Definition at line 2961 of file i915_reg.h.
#define VGA_SR_DATA 0x3c5 |
Definition at line 122 of file i915_reg.h.
#define VGA_SR_INDEX 0x3c4 |
Definition at line 121 of file i915_reg.h.
#define VGA_ST01_CGA 0x3da |
Definition at line 114 of file i915_reg.h.
#define VGA_ST01_MDA 0x3ba |
Definition at line 113 of file i915_reg.h.
#define VGACNTRL 0x71400 |
Definition at line 2958 of file i915_reg.h.
#define VIDEO_DIP_CTL 0x61170 |
Definition at line 1490 of file i915_reg.h.
#define VIDEO_DIP_DATA 0x61178 |
Definition at line 1485 of file i915_reg.h.
#define VIDEO_DIP_DATA_SIZE 32 |
Definition at line 1489 of file i915_reg.h.
#define VIDEO_DIP_ENABLE (1UL << 31) |
Definition at line 1492 of file i915_reg.h.
#define VIDEO_DIP_ENABLE_AVI (1 << 21) |
Definition at line 1498 of file i915_reg.h.
#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) |
Definition at line 1513 of file i915_reg.h.
#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) |
Definition at line 1500 of file i915_reg.h.
#define VIDEO_DIP_ENABLE_GCP (1 << 25) |
Definition at line 1497 of file i915_reg.h.
#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) |
Definition at line 1512 of file i915_reg.h.
#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) |
Definition at line 1515 of file i915_reg.h.
#define VIDEO_DIP_ENABLE_SPD (8 << 21) |
Definition at line 1501 of file i915_reg.h.
#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) |
Definition at line 1516 of file i915_reg.h.
#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) |
Definition at line 1499 of file i915_reg.h.
#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) |
Definition at line 1514 of file i915_reg.h.
#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) |
Definition at line 1511 of file i915_reg.h.
#define VIDEO_DIP_FREQ_2VSYNC (2 << 16) |
Definition at line 1508 of file i915_reg.h.
#define VIDEO_DIP_FREQ_MASK (3 << 16) |
Definition at line 1509 of file i915_reg.h.
#define VIDEO_DIP_FREQ_ONCE (0 << 16) |
Definition at line 1506 of file i915_reg.h.
#define VIDEO_DIP_FREQ_VSYNC (1 << 16) |
Definition at line 1507 of file i915_reg.h.
#define VIDEO_DIP_PORT_B (1 << 29) |
Definition at line 1493 of file i915_reg.h.
#define VIDEO_DIP_PORT_C (2 << 29) |
Definition at line 1494 of file i915_reg.h.
#define VIDEO_DIP_PORT_D (3 << 29) |
Definition at line 1495 of file i915_reg.h.
#define VIDEO_DIP_PORT_MASK (3 << 29) |
Definition at line 1496 of file i915_reg.h.
#define VIDEO_DIP_SELECT_AVI (0 << 19) |
Definition at line 1502 of file i915_reg.h.
#define VIDEO_DIP_SELECT_MASK (3 << 19) |
Definition at line 1505 of file i915_reg.h.
#define VIDEO_DIP_SELECT_SPD (3 << 19) |
Definition at line 1504 of file i915_reg.h.
#define VIDEO_DIP_SELECT_VENDOR (1 << 19) |
Definition at line 1503 of file i915_reg.h.
#define VLV_ADPA (VLV_DISPLAY_BASE + ADPA) |
Definition at line 1261 of file i915_reg.h.
#define VLV_DDL1 0x70050 |
Definition at line 2523 of file i915_reg.h.
#define VLV_DDL2 0x70054 |
Definition at line 2529 of file i915_reg.h.
#define VLV_DISPLAY_BASE 0x180000 |
Definition at line 518 of file i915_reg.h.
#define VLV_DPFLIPSTAT 0x70028 |
Definition at line 2457 of file i915_reg.h.
#define VLV_GUNIT_CLOCK_GATE 0x182060 |
Definition at line 525 of file i915_reg.h.
#define VLV_IER 0x1820a0 |
Definition at line 528 of file i915_reg.h.
#define VLV_IIR 0x1820a4 |
Definition at line 529 of file i915_reg.h.
#define VLV_IIR_RW 0x182084 |
Definition at line 527 of file i915_reg.h.
#define VLV_IMR 0x1820a8 |
Definition at line 530 of file i915_reg.h.
#define VLV_ISR 0x1820ac |
Definition at line 531 of file i915_reg.h.
#define VLV_MASTER_IER 0x4400c /* Gunit master IER */ |
Definition at line 3127 of file i915_reg.h.
#define VLV_TVIDEO_DIP_CTL | ( | pipe | ) | _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B) |
Definition at line 3443 of file i915_reg.h.
#define VLV_TVIDEO_DIP_DATA | ( | pipe | ) | _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B) |
Definition at line 3445 of file i915_reg.h.
#define VLV_TVIDEO_DIP_GCP | ( | pipe | ) | _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B) |
Definition at line 3447 of file i915_reg.h.
#define VLV_VIDEO_DIP_CTL_A 0x60200 |
Definition at line 3435 of file i915_reg.h.
#define VLV_VIDEO_DIP_CTL_B 0x61170 |
Definition at line 3439 of file i915_reg.h.
#define VLV_VIDEO_DIP_DATA_A 0x60208 |
Definition at line 3436 of file i915_reg.h.
#define VLV_VIDEO_DIP_DATA_B 0x61174 |
Definition at line 3440 of file i915_reg.h.
#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210 |
Definition at line 3437 of file i915_reg.h.
#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178 |
Definition at line 3441 of file i915_reg.h.
#define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ |
Definition at line 1043 of file i915_reg.h.
#define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ |
Definition at line 1042 of file i915_reg.h.
#define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ |
Definition at line 1063 of file i915_reg.h.
#define VS_TIMER_DISPATCH (1 << 6) |
Definition at line 500 of file i915_reg.h.
#define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ |
Definition at line 1041 of file i915_reg.h.
#define VSYNC | ( | trans | ) | _TRANSCODER(trans, _VSYNC_A, _VSYNC_B) |
Definition at line 1254 of file i915_reg.h.
#define VSYNC_ACTIVE_HIGH (1 << 4) |
Definition at line 3722 of file i915_reg.h.
#define VSYNCSHIFT | ( | trans | ) | _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) |
Definition at line 1256 of file i915_reg.h.
#define VTOTAL | ( | trans | ) | _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B) |
Definition at line 1252 of file i915_reg.h.
#define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) |
Definition at line 1083 of file i915_reg.h.
#define WM0_PIPE_CURSOR_MASK (0x1f) |
Definition at line 2575 of file i915_reg.h.
#define WM0_PIPE_PLANE_MASK (0x7f<<16) |
Definition at line 2571 of file i915_reg.h.
#define WM0_PIPE_PLANE_SHIFT 16 |
Definition at line 2572 of file i915_reg.h.
#define WM0_PIPE_SPRITE_MASK (0x3f<<8) |
Definition at line 2573 of file i915_reg.h.
#define WM0_PIPE_SPRITE_SHIFT 8 |
Definition at line 2574 of file i915_reg.h.
#define WM0_PIPEA_ILK 0x45100 |
Definition at line 2570 of file i915_reg.h.
#define WM0_PIPEB_ILK 0x45104 |
Definition at line 2577 of file i915_reg.h.
#define WM0_PIPEC_IVB 0x45200 |
Definition at line 2578 of file i915_reg.h.
#define WM1_LP_CURSOR_MASK (0x3f) |
Definition at line 2587 of file i915_reg.h.
#define WM1_LP_FBC_MASK (0xf<<20) |
Definition at line 2583 of file i915_reg.h.
#define WM1_LP_FBC_SHIFT 20 |
Definition at line 2584 of file i915_reg.h.
#define WM1_LP_ILK 0x45108 |
Definition at line 2579 of file i915_reg.h.
#define WM1_LP_LATENCY_MASK (0x7f<<24) |
Definition at line 2582 of file i915_reg.h.
#define WM1_LP_LATENCY_SHIFT 24 |
Definition at line 2581 of file i915_reg.h.
#define WM1_LP_SR_EN (1UL<<31) |
Definition at line 2580 of file i915_reg.h.
#define WM1_LP_SR_MASK (0x1ff<<8) |
Definition at line 2585 of file i915_reg.h.
#define WM1_LP_SR_SHIFT 8 |
Definition at line 2586 of file i915_reg.h.
#define WM1S_LP_EN (1UL<<31) |
Definition at line 2595 of file i915_reg.h.
#define WM1S_LP_ILK 0x45120 |
Definition at line 2592 of file i915_reg.h.
#define WM2_LP_EN (1UL<<31) |
Definition at line 2589 of file i915_reg.h.
#define WM2_LP_ILK 0x4510c |
Definition at line 2588 of file i915_reg.h.
#define WM2S_LP_IVB 0x45124 |
Definition at line 2593 of file i915_reg.h.
#define WM3_LP_EN (1UL<<31) |
Definition at line 2591 of file i915_reg.h.
#define WM3_LP_ILK 0x45110 |
Definition at line 2590 of file i915_reg.h.
#define WM3S_LP_IVB 0x45128 |
Definition at line 2594 of file i915_reg.h.
#define WM_DBG 0x45280 |
Definition at line 4374 of file i915_reg.h.
#define WM_DBG_DISALLOW_MAXFIFO (1<<1) |
Definition at line 4376 of file i915_reg.h.
#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) |
Definition at line 4375 of file i915_reg.h.
#define WM_DBG_DISALLOW_SPRITE (1<<2) |
Definition at line 4377 of file i915_reg.h.
#define WRPLL_CTL1 0x46040 |
Definition at line 4306 of file i915_reg.h.
#define WRPLL_CTL2 0x46060 |
Definition at line 4307 of file i915_reg.h.
Definition at line 4315 of file i915_reg.h.
Definition at line 4314 of file i915_reg.h.
Definition at line 4313 of file i915_reg.h.
#define WRPLL_PLL_ENABLE (1UL<<31) |
Definition at line 4308 of file i915_reg.h.
#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) |
Definition at line 4311 of file i915_reg.h.
#define WRPLL_PLL_SELECT_NON_SSC (0x02<<28) |
Definition at line 4310 of file i915_reg.h.
#define WRPLL_PLL_SELECT_SSC (0x01<<28) |
Definition at line 4309 of file i915_reg.h.
#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) |
Definition at line 266 of file i915_reg.h.
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) |
Definition at line 265 of file i915_reg.h.
#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ |
Definition at line 275 of file i915_reg.h.
#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ |
Definition at line 274 of file i915_reg.h.
#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) |
Definition at line 267 of file i915_reg.h.
#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) |
Definition at line 268 of file i915_reg.h.
#define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ |
Definition at line 1075 of file i915_reg.h.