coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <console/console.h>
4 #include <fsp/api.h>
5 #include <gpio.h>
6 #include "gpio.h"
7 #include <soc/romstage.h>
8 #include <soc/gpio.h>
9 #include "spd/spd.h"
10 #include <spd_bin.h>
11 #include "board_id.h"
12 
13 void mainboard_memory_init_params(FSPM_UPD *mupd)
14 {
15  FSP_M_CONFIG *mem_cfg;
16  mem_cfg = &mupd->FspmConfig;
17  u8 spd_index;
18  if (get_spd_index(&spd_index) < 0)
19  return;
20 
21  printk(BIOS_INFO, "SPD index %d\n", spd_index);
22 
23  mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0,
24  &mem_cfg->DqByteMapCh1);
25  mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0,
26  &mem_cfg->DqsMapCpu2DramCh1);
27  mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
28  mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
29 
30  if (CONFIG(BOARD_INTEL_KBLRVP3)) {
31  mem_cfg->DqPinsInterleaved = 0;
32  mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
33  /* Memory leak is ok since we have memory mapped boot media */
34  mem_cfg->MemorySpdPtr00 = spd_cbfs_map(spd_index);
35  if (!mem_cfg->MemorySpdPtr00)
36  die("spd.bin not found\n");
37  } else { /* CONFIG_BOARD_INTEL_KBLRVP7 and CONFIG_BOARD_INTEL_KBLRVP8 */
38  struct spd_block blk = {
39  .addr_map = { 0x50, 0x51, 0x52, 0x53, },
40  };
41 
42  mem_cfg->DqPinsInterleaved = 1;
43  get_spd_smbus(&blk);
44  mem_cfg->MemorySpdDataLen = blk.len;
45  mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
46  mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2];
47 
48  switch (get_board_id()) {
49  case BOARD_ID_KBL_RVP8:
50  case BOARD_ID_KBL_RVP11:
51  mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1];
52  mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3];
53  break;
54  default:
55  break;
56  }
57  }
58  mupd->FspmTestConfig.DmiVc1 = 1;
59 }
#define printk(level,...)
Definition: stdlib.h:16
void __noreturn die(const char *fmt,...)
Definition: die.c:17
@ CONFIG
Definition: dsi_common.h:201
#define FSP_M_CONFIG
Definition: fsp_upd.h:8
static size_t get_spd_index(void)
#define BOARD_ID_KBL_RVP11
Definition: board_id.h:12
#define BOARD_ID_KBL_RVP8
Definition: board_id.h:11
#define BIOS_INFO
BIOS_INFO - Expected events.
Definition: loglevel.h:113
void mainboard_memory_init_params(FSPM_UPD *mupd)
Definition: romstage.c:22
static const int spd_index[32]
Definition: memory.c:10
static uint8_t get_board_id(void)
Definition: boardid.c:14
static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1)
Definition: romstage.c:8
static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1)
Definition: romstage.c:19
static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
Definition: romstage.c:7
static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
Definition: romstage.c:13
void get_spd_smbus(struct spd_block *blk)
Definition: smbuslib.c:72
uintptr_t spd_cbfs_map(u8 spd_index)
Definition: spd_bin.c:217
unsigned long uintptr_t
Definition: stdint.h:21
uint8_t u8
Definition: stdint.h:45
Definition: ddr4.c:86
u8 addr_map[CONFIG_DIMM_MAX]
Definition: spd_bin.h:39
u8 * spd_array[CONFIG_DIMM_MAX]
Definition: spd_bin.h:40
uint16_t len
Definition: ddr4.c:89