coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <stdint.h>
#include <console/console.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <elog.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h>
#include <arch/cpu.h>
#include "ironlake.h"
Go to the source code of this file.
Functions | |
static void | ironlake_setup_bars (void) |
static void | early_cpu_init (void) |
void | ironlake_early_initialization (int chipset_type) |
Definition at line 39 of file early_init.c.
References cpuid_ext(), DESIRED_CORES, IA32_MISC_ENABLE, IA32_PERF_CTL, m, MSR_FSB_CLOCK_VCC, pci_update_config32(), QPI_NON_CORE, rdmsr(), and wrmsr().
Referenced by ironlake_early_initialization().
void ironlake_early_initialization | ( | int | chipset_type | ) |
Definition at line 77 of file early_init.c.
References DEFAULT_PMBASE, DEVEN, DEVEN_HOST, DEVEN_IGD, DEVEN_PEG10, early_cpu_init(), elog_boot_notify(), ibexpeak_setup_bars(), inl(), inw(), IRONLAKE_MOBILE, ironlake_setup_bars(), mchbar_clrsetbits32(), PCI_DEV, pci_read_config32(), pci_read_config8(), pci_write_config32(), pci_write_config8(), PM1_CNT, PM1_STS, SLP_TYP_S3, and WAK_STS.
Referenced by mainboard_romstage_entry().
Definition at line 16 of file early_init.c.
References BIOS_DEBUG, DMIBAR, EPBAR, MCHBAR, PCI_DEV, pci_write_config32(), pci_write_config8(), printk, QPD0F1_PAM, and QPI_SAD.
Referenced by ironlake_early_initialization().