37 #define LAST_TSHUT (1 << 24)
38 #define TSHUT_POL_HIGH (1 << 8)
39 #define SRC3_EN (1 << 7)
40 #define SRC2_EN (1 << 6)
41 #define SRC1_EN (1 << 5)
42 #define SRC0_EN (1 << 4)
43 #define AUTO_EN (1 << 0)
46 #define TSHUT_CRU_EN_SRC3 (1 << 11)
47 #define TSHUT_CRU_EN_SRC2 (1 << 10)
48 #define TSHUT_CRU_EN_SRC1 (1 << 9)
49 #define TSHUT_CRU_EN_SRC0 (1 << 8)
50 #define TSHUT_GPIO_EN_SRC3 (1 << 7)
51 #define TSHUT_GPIO_EN_SRC2 (1 << 6)
52 #define TSHUT_GPIO_EN_SRC1 (1 << 5)
53 #define TSHUT_GPIO_EN_SRC0 (1 << 4)
55 #define AUTO_PERIOD 10
56 #define AUTO_DEBOUNCE 4
57 #define AUTO_PERIOD_HT 10
58 #define AUTO_DEBOUNCE_HT 4
59 #define TSADC_CLOCK_HZ (8 * KHz)
62 #define TSADC_SHUT_VALUE 3437
static void write32(void *addr, uint32_t val)
#define setbits32(addr, set)
static struct rk3288_pmu_regs *const rk3288_pmu
#define TSHUT_CRU_EN_SRC1
#define TSHUT_GPIO_EN_SRC1
check_member(rk3288_tsadc_regs, auto_period_ht, 0x6c)
#define TSHUT_GPIO_EN_SRC2
#define TSHUT_CRU_EN_SRC2
struct rk3288_tsadc_regs * rk3288_tsadc
void rkclk_configure_tsadc(unsigned int hz)
u32 reserved0[(0x20 - 0x10)/4]
u32 reserved1[(0x60 - 0x50)/4]