coreboot
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spi.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOC_INTEL_COMMON_BLOCK_SPI_H
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#define SOC_INTEL_COMMON_BLOCK_SPI_H
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#include <types.h>
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/*
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* Check if write protection for CSE RO is enabled or not.
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* Returns true if write protection for CSE RO is enabled, false otherwise.
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*/
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bool
is_spi_wp_cse_ro_en
(
void
);
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/* Gets CSE RO's write protected area's base address and limit */
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void
spi_get_wp_cse_ro_range
(
uint32_t
*
base
,
uint32_t
*limit);
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/*
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* SoC overrides
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*
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* All new SoC must implement below functionality.
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*/
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/* Function to convert input device function to bus number
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* Input: Device Function number
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* Output: -1 translate to Error, >=0 is bus number
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*/
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int
spi_soc_devfn_to_bus
(
unsigned
int
devfn);
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#endif
/* SOC_INTEL_COMMON_BLOCK_SPI_H */
base
uintptr_t base
Definition:
uart.c:17
spi_soc_devfn_to_bus
int spi_soc_devfn_to_bus(unsigned int devfn)
Definition:
spi.c:15
spi_get_wp_cse_ro_range
void spi_get_wp_cse_ro_range(uint32_t *base, uint32_t *limit)
Definition:
spi.c:95
is_spi_wp_cse_ro_en
bool is_spi_wp_cse_ro_en(void)
Definition:
spi.c:87
uint32_t
unsigned int uint32_t
Definition:
stdint.h:14
src
soc
intel
common
block
include
intelblocks
spi.h
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