3 #define __SIMPLE_DEVICE__
14 #include <soc/pci_devs.h>
19 #if !ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI)
21 .bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)},
27 #define MMIO_BIOS_GPR0 0x98
#define assert(statement)
const struct spi_ctrlr gspi_ctrlr
const struct spi_ctrlr fast_spi_flash_ctrlr
static __always_inline uint32_t read32p(const uintptr_t addr)
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
#define PCI_BASE_ADDRESS_MEM_ATTR_MASK
#define PCI_BASE_ADDRESS_0
void pci_dev_enable_resources(struct device *dev)
void pci_dev_read_resources(struct device *dev)
struct pci_operations pci_dev_ops_pci
Default device operation for PCI devices.
void pci_dev_set_resources(struct device *dev)
#define PCI_DID_INTEL_ICP_SPI1
#define PCI_DID_INTEL_GLK_SPI0
#define PCI_DID_INTEL_ADP_P_HWSEQ_SPI
#define PCI_DID_INTEL_ADP_P_SPI5
#define PCI_DID_INTEL_SPR_HWSEQ_SPI
#define PCI_DID_INTEL_CNP_H_SPI1
#define PCI_DID_INTEL_TGP_H_GSPI3
#define PCI_DID_INTEL_CNL_SPI0
#define PCI_DID_INTEL_CMP_H_SPI2
#define PCI_DID_INTEL_ADP_S_SPI5
#define PCI_DID_INTEL_APL_HWSEQ_SPI
#define PCI_DID_INTEL_ADP_P_SPI2
#define PCI_DID_INTEL_CNL_HWSEQ_SPI
#define PCI_DID_INTEL_ADP_P_SPI1
#define PCI_DID_INTEL_ICP_SPI0
#define PCI_DID_INTEL_ADP_P_SPI3
#define PCI_DID_INTEL_LWB_SPI
#define PCI_DID_INTEL_CNL_SPI1
#define PCI_DID_INTEL_JSP_SPI2
#define PCI_DID_INTEL_MTL_GSPI0
#define PCI_DID_INTEL_MCC_GSPI1
#define PCI_DID_INTEL_ADP_M_N_SPI0
#define PCI_DID_INTEL_TGP_SPI0
#define PCI_DID_INTEL_MTL_GSPI1
#define PCI_DID_INTEL_JSP_HWSEQ_SPI
#define PCI_DID_INTEL_ADP_M_N_SPI1
#define PCI_DID_INTEL_CMP_HWSEQ_SPI
#define PCI_DID_INTEL_ADP_S_SPI6
#define PCI_DID_INTEL_CNP_H_SPI0
#define PCI_DID_INTEL_ADP_S_SPI3
#define PCI_DID_INTEL_ADP_P_SPI6
#define PCI_DID_INTEL_APL_SPI1
#define PCI_DID_INTEL_TGP_GSPI2
#define PCI_DID_INTEL_TGP_GSPI5
#define PCI_DID_INTEL_ADP_S_HWSEQ_SPI
#define PCI_DID_INTEL_TGP_H_GSPI2
#define PCI_DID_INTEL_APL_SPI2
#define PCI_DID_INTEL_MCC_SPI0
#define PCI_DID_INTEL_JSP_SPI0
#define PCI_DID_INTEL_TGP_H_GSPI1
#define PCI_DID_INTEL_CMP_SPI0
#define PCI_DID_INTEL_SPT_SPI2
#define PCI_DID_INTEL_TGP_GSPI6
#define PCI_DID_INTEL_ADP_P_SPI0
#define PCI_DID_INTEL_CNL_SPI2
#define PCI_DID_INTEL_ADP_M_N_HWSEQ_SPI
#define PCI_DID_INTEL_LWB_SPI_SUPER
#define PCI_DID_INTEL_ADP_M_SPI2
#define PCI_DID_INTEL_ADP_P_SPI4
#define PCI_DID_INTEL_TGP_H_SPI0
#define PCI_DID_INTEL_ICP_SPI2
#define PCI_DID_INTEL_CMP_SPI2
#define PCI_DID_INTEL_MCC_GSPI0
#define PCI_DID_INTEL_TGP_GSPI4
#define PCI_DID_INTEL_CMP_SPI1
#define PCI_DID_INTEL_ADP_S_SPI0
#define PCI_DID_INTEL_TGP_GSPI0
#define PCI_DID_INTEL_JSP_SPI1
#define PCI_DID_INTEL_ICP_HWSEQ_SPI
#define PCI_DID_INTEL_CNP_H_HWSEQ_SPI
#define PCI_DID_INTEL_ADP_S_SPI1
#define PCI_DID_INTEL_GLK_SPI1
#define PCI_DID_INTEL_SPT_SPI1
#define PCI_DID_INTEL_MCC_GSPI2
#define PCI_DID_INTEL_TGP_H_GSPI0
#define PCI_DID_INTEL_GLK_SPI2
#define PCI_DID_INTEL_TGP_GSPI3
#define PCI_DID_INTEL_MTL_GSPI2
#define PCI_DID_INTEL_MTL_HWSEQ_SPI
#define PCI_DID_INTEL_TGP_GSPI1
#define PCI_DID_INTEL_CMP_H_SPI1
#define PCI_DID_INTEL_CMP_H_SPI0
#define PCI_DID_INTEL_CMP_H_HWSEQ_SPI
#define PCI_DID_INTEL_CNP_H_SPI2
#define PCI_DID_INTEL_ADP_S_SPI2
#define PCI_DID_INTEL_SPT_SPI3
#define PCI_DID_INTEL_APL_SPI0
#define PCI_DID_INTEL_ADP_S_SPI4
void scan_generic_bus(struct device *bus)
const struct spi_ctrlr_buses spi_ctrlr_bus_map[]
const size_t spi_ctrlr_bus_map_count
int spi_soc_devfn_to_bus(unsigned int devfn)
static const struct pci_driver pch_spi __pci_driver
static struct device_operations spi_dev_ops
static uint32_t spi_get_wp_cse_ro_limit(union spi_bios_gpr0 bios_gpr0)
static int spi_dev_to_bus(struct device *dev)
static struct spi_bus_operations spi_bus_ops
static uint32_t spi_get_wp_cse_ro_start_offset(union spi_bios_gpr0 bios_gpr0)
static const unsigned short pci_device_ids[]
static uint32_t spi_read_bios_gpr0(void)
void spi_get_wp_cse_ro_range(uint32_t *base, uint32_t *limit)
static uintptr_t get_spi_bar(pci_devfn_t dev)
static uint32_t spi_read_bar(pci_devfn_t dev, uint32_t offset)
bool is_spi_wp_cse_ro_en(void)
void(* read_resources)(struct device *dev)
int(* dev_to_bus)(struct device *dev)
const struct spi_ctrlr * ctrlr
uint32_t protect_range_base
uint32_t protect_range_limit
struct spi_bios_gpr0::@549 fields
uint32_t write_protect_en