coreboot
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lpss.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOC_INTEL_COMMON_BLOCK_LPSS_H
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#define SOC_INTEL_COMMON_BLOCK_LPSS_H
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#include <
device/device.h
>
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#include <
stdint.h
>
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/* D0 and D3 enable config */
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enum
lpss_pwr_state
{
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STATE_D0
= 0,
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STATE_D3
= 3
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};
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/* Gets controller out of reset */
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void
lpss_reset_release
(
uintptr_t
base
);
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/*
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* Update clock divider parameters. Clock frequency is dependent on source
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* clock frequency of each IP block. Resulting clock will be src_freq * (M / N).
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*/
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void
lpss_clk_update
(
uintptr_t
base
,
uint32_t
clk_m_val,
uint32_t
clk_n_val);
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/* Check if controller is in reset. */
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bool
lpss_is_controller_in_reset
(
uintptr_t
base
);
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/* Set controller power state to D0 or D3*/
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void
lpss_set_power_state
(
pci_devfn_t
devfn,
enum
lpss_pwr_state
state
);
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#endif
/* SOC_INTEL_COMMON_BLOCK_LPSS_H */
device.h
lpss_set_power_state
void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state)
Definition:
lpss.c:68
lpss_reset_release
void lpss_reset_release(uintptr_t base)
Definition:
lpss.c:47
lpss_is_controller_in_reset
bool lpss_is_controller_in_reset(uintptr_t base)
Definition:
lpss.c:36
lpss_clk_update
void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val)
Definition:
lpss.c:55
lpss_pwr_state
lpss_pwr_state
Definition:
lpss.h:10
STATE_D3
@ STATE_D3
Definition:
lpss.h:12
STATE_D0
@ STATE_D0
Definition:
lpss.h:11
state
state
Definition:
raminit.c:1787
pci_devfn_t
u32 pci_devfn_t
Definition:
pci_type.h:8
base
uintptr_t base
Definition:
uart.c:17
stdint.h
uint32_t
unsigned int uint32_t
Definition:
stdint.h:14
uintptr_t
unsigned long uintptr_t
Definition:
stdint.h:21
src
soc
intel
common
block
include
intelblocks
lpss.h
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