coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
lpss.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef SOC_INTEL_COMMON_BLOCK_LPSS_H
4 #define SOC_INTEL_COMMON_BLOCK_LPSS_H
5 
6 #include <device/device.h>
7 #include <stdint.h>
8 
9 /* D0 and D3 enable config */
11  STATE_D0 = 0,
12  STATE_D3 = 3
13 };
14 
15 /* Gets controller out of reset */
17 
18 /*
19  * Update clock divider parameters. Clock frequency is dependent on source
20  * clock frequency of each IP block. Resulting clock will be src_freq * (M / N).
21  */
22 void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val);
23 
24 /* Check if controller is in reset. */
26 
27 /* Set controller power state to D0 or D3*/
29 
30 #endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */
void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state)
Definition: lpss.c:68
void lpss_reset_release(uintptr_t base)
Definition: lpss.c:47
bool lpss_is_controller_in_reset(uintptr_t base)
Definition: lpss.c:36
void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val)
Definition: lpss.c:55
lpss_pwr_state
Definition: lpss.h:10
@ STATE_D3
Definition: lpss.h:12
@ STATE_D0
Definition: lpss.h:11
state
Definition: raminit.c:1787
u32 pci_devfn_t
Definition: pci_type.h:8
uintptr_t base
Definition: uart.c:17
unsigned int uint32_t
Definition: stdint.h:14
unsigned long uintptr_t
Definition: stdint.h:21